35128915 implementation of a FPGA based architecture of prew

Implementation of a FPGA based Architecture of Prewitt Edge detection Algorithm using Verilog HDL Mohammad Naz mul Haque Department of Computer Science & Engineering Daffodil Internati

Implementation of a FPGA based Architecture of Prewitt

Edge detection Algorithm using Verilog HDL

Mohammad Naz mul Haque

Department of Computer Science & Engineering Daffodil International University, Dhaka, Bangladesh e-mail: nazmul@daffodilvarsity.edu.bd

This paper pres ents FPGA based architecture for Pre witt edge detection operator Typical us e of Edge detection is in the computer v ision, robotics and artificia l intelligence sys tem Currently the image processing algorith ms has been limited to software imp le mentation which is slower due to the limited processor speed So a dedicated processor for edge detection has been required which was not possible until advancement in VLSI technology Now more co mp le x system can be integrated

on a single chip providing a platform to proces s realtime a lgorith ms on hardware This arch itecture is imp le mented using Verilog HDL language and verified by Simulat ion using ModelSim

Ke ywords: Edge detection algorithms, hard ware imp le mentation, prewitt operators, VLSI, Verilog HDL

I Introduction

An edge can be defined as an abrupt change in brightness as we move fro m one pixe l to its neighbor in an image In d igital image

process ing, each image is quantized into pixe ls In gray-scale each pixel i(x,y) in the image indicates the amplitude of intensity i

of the image in a particula r s patial coordinate (x,y) The intensity value 0 repres ents black, and with 8-bit p ixe ls, 255 repres ent

white An edge is an abrupt change in the intensity (gray scale level) of the pixe ls Detecting edges is an important task in boundary detection, motion detection/estimation, te xture analysis, segmentation, and object identification Human eye can detect edges very quickly But it is most difficu lt for machine such as computer vision, robotics etc

II Edge Detection

Edge information for a particula r pixel is obtained by exploring the intensity of pixels in the neighborhood of that pixe l If a ll of the pixe ls in the ne ighborhood have almost the same brightness, then there is probably no edge at that point However, if so me of the neighbors are much brighter than the others, then there is a probably an edge at that point Measuring the relative brightness of pixe ls in a ne ighborhood is mathemat ically analogous to calculating the derivative of brightness The image illus trates an exa mple

of Hard and Soft Edges on an image Brightness values are discrete, not continuous, so we approximate the derivative function Diffe rent edge detection methods (Prewitt, Laplac ian, Roberts, Sobel and Canny) use different discrete approximations of the derivative function [1–6]

Figure 1: Types of Edges III FP GA Pri mer

In early processes, the edge detection was ma inly performed on software due to its large hard ware equip ment and also the application specific integrated circu its have not gain much advancement But present researches on programmable devices ma ke it possible to imp le ment edge detection algorith ms on these devices whose design turnaround time varies from few hours to few days

During the recent years fie ld programmab le gate arrays (FPGA’s) have beco me the prevailing form of programmable logic [8-12]

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IV Pre witt Edge Detection Algorithm

Prewitt is gradient based edge detection algorithm The grad ient method looks the edges by finding ma ximu m and minimu m in the first derivative of the image Prewitt a lgorith m performs a 2-D s patial gradient meas urement on an image It uses a pair of 3X3 convolution masks, one estimat ing gradient in x-d irection and other in y-direction Then resultant magnitude is co mputed

fro m the above two gradients The gradient of the 2-D image i(x,y) at spatial coordinate (x,y) is defined as the vector

is obtained by:

The Pre witt Edge filter is us e to detect edges based applying a horizontal and vertica l filter in sequence Both filters are applied to the image and s ummed to form the fina l result The two filters are bas ic convolution filters of the form:

a) X-directional convolution mask Gx b) Y-directional convolution mask Gy c) Image Neighborhoo d

Figure 2 : Image Ke rrnel and Pre witt Convolution Masks

Fro m the outputs of these convolution blocks resultant absolute magnitude is co mputed This magnitude is the final output of the Prewitt edge detection output If the X-d irectional convolution mask is placed on p5 pixel then we get:

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By plac ing Y-direct ional mask on kernel the new value is given by:

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The new value of that ke rnel’s center pixel p5 will be given by:

By applying this procedure to all over the image the edges of x and y direct ion will be gotten

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X-Mask Gx = (12+167+120)

– (1+123+25) Gx=150

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Gy = (120+23+25) – (12+50+1) Gy=105

255

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Figure 3: Convolution Example for Image Pixel

IV Hardware Architecture of Prewitt Edge Detector Instance

P1, P2, P3, P4, P6, P7, P8 and P9 repres ent the eight 8bit pixel inputs of the image Kernel to the Prewitt Module The mod ule consists of signed subtractors, shift registers and modulus operators The output of the final adder b lock will be 11 b its (10 bits for the data as the ma ximu m va lue of the adder output is 4*255 and the 11th b it as the sign bit) The output data is compared to limit the value to a ma ximu m of 255 as the output image is also composed of 8-bit wide pixels The Pre witt output for one group of pixe ls calculated as per |Gx| + |Gy |

Figure 4: RTL View of Prewitt Module

VI Res ults

The architecture for Prewitt edge detection operator was imp le mented on VerilogHDL [7–10] and simulat ion on Modelsim Altera

Figure 5: Simulation Output of Prewitt Hardware Module

Figure 6: Hardware Architecture Validation

VII Conclusion and Future Scope

The FPGA based architecture for Pre witt edge detection operator is proposed This architecture is capable of operating at much higher speed than processing images on software p latform using high leve l programming languages like C or C++ This architecture the result of edge detection can be found out for big images (like of size 1024 × 1024 pixels) in just 7.8 ms Fu rther improve ment in speed could be achieved by appending more pipelining stages at decoder and processing blocks level but it may increase silicon area considerably

References

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[2] Chanda, B.and Dutta, D Majumdar Digital Image Processing and Analysis,Prentice Hall of India

[3] Gonzalez, Rafael C and Woods, Richard E Digital Image Processing, Pearson Education, Inc

[4] J F Canny A computational approach to edge detection IEEE Transactions on Pattern Analysis and Machine Intelligence, 8(6):769–798, November 1986 [5] Pratt,W K Digital Image Processing, John Wiley & Son s, Inc

[6] Heath, Mike, Sarkar, Sudeep, Sanocki, Thomas, and Bowyer, Kevin, Comparison of

Edge Detectors: A Methodology and Initial Study

[7] Palnitkar, Samir Verilog HDL-A Guide to Digital Design and Synthesis, Pearson Education

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implementation of IIR filters for Real tim e edge detection International Conference on image processing (ICIP-97) Volume 2 Oct 1997

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