Vi điều khiển và ứng dụng OutputCompare

Các chế độ hoạt độngSingle compare match mode, Dual compare match mode generating either one output pulse or a sequence of output pulses, Pulse Width Modulation PWM mode... Single com

Output Compare

Chuyên đề II

Vi điều khiển và ứng dụng

OC with DsPIC

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Chi tiết

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Chức năng

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Các chế độ hoạt động

Single compare match mode,

Dual compare match mode generating either one output pulse or a sequence of output pulses,

Pulse Width Modulation (PWM) mode

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Single compare match

OCx pin is high, initial state is low, and interrupt is generated,

OCx pin is low, initial state is high, and interrupt is generated,

State of OCx pin toggles and interrupt is generated

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OCx pin is high control bits OCM<2:0> are set to 001

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OCx pin is low

OCM<2:0> are set to 010

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Single compare match, pin OCx toggles

OCM<2:0> areset to 011

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Ví dụ

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Dual compare match

mode

single pulse and an interrupt request,

a sequence of pulses and an interrupt request

control bits OCM<2:0> are set to 100 or 101

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Single output pulse at pin Ocx

OCM<2:0> are set to 100

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Sequence of output pulses at pin Ocx

control bits OCM<2:0> are set to 101

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Ví dụ

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The Pulse Width

PWM mode without fault protection input

 Set the PWM period by writing to the selected

timer period register, PRy.

 Set the PWM duty cycle by writing to the OCxRS register.

 Write the OCxR register with the initial duty cycle.

 Enable interrupts for the selected timer.

 Configure the output compare module for one of two PWM operation modes by writing 100 to

control bits OCM<2:0> (OCxCON<2:0>).

 Set the TMRy prescale value and enable the

selected time base.

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PWM mode with fault

protection input pin

Input pin OCxFA for the output compare

PWM period and duty

Calculation of the PWM period for a microcontroller having

a 10MHz clock with x4 PLL, Device clock rate is 40MHz The instruction clock frequency is FCY=FOSC/4, i.e

10MHz Timer 2 prescale setting is 4 Calculate the PWM period for the maximum value PR2=0xFFFF=65535.

TPWM = (65535+1) x 0.1µs x (4) = 26.21 ms, i.e fPWM = 1/TPWM = 38.14 Hz.

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PWM duty cycle

If the duty cycle register,OCxR, is loaded

with 0000, the duty cycle is zero and pin OCx will remain low throughout the PWM period

If the duty cycle register is greater that PRy, the output pin OCx will remain high

throughout the PWM period (100% duty cycle)

If OCxR is equal to PRy, the OCx pin will be high in the first PWM cycle and low in the subsequent PWM cycle

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Ví dụ

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Mạch D/A

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Ví dụ sóng vuông

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Ví dụ sóng hình thang

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Sóng hình sin

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A second order filter

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Ví dụ ứng dụng

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Circular buffer

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Circular buffer

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Circular Buffer

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Phương pháp hoạt động

Difficulites

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Xử lý lỗi

Always Keep One Slot Open

Use a Fill Count

Read / Write Counts

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Ví dụ

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