Analysis and design of power electronic cell for modular power electronic systems DC AC converter configurations

... “Plug-n-Play” using standard cells 1.2.2 Conceptual Design of A Universal Power Electronic Cell Power electronic converters can be broadly classified as DC/ DC, DC/ AC, AC /DC and AC/ AC converters We can... applications: a )DC to AC inverter, b )AC to DC converter, c )DC to AC motor controller, d )AC to DC 18 boost converter and e )DC to DC boost converter PEBB-2, the second phase focuses on developing and defining... concerns for 33 Motor Filter AC /DC DC /AC Load Rec & Filter AC Power Supply DC/ DC Filter DC/ AC Motor DC Power Distribution Bus Figure 2.9: A PEBB-based Distributed Power System [5] the DPS, because each

Modular Power Electronic Systems: DC-AC

Converter Configurations

YONGHONG JIANG

A THESIS SUBMITTEDFOR THE DEGREE OF MASTER OF ENGINEERING

DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

2003

To my dearest Yijun

The author would like to thank many people who have contributed to this work.Foremost among them is my research supervisor, Dr.Ashwin M Khambadkoneand Prof Oruganti, Ramesh , to whom I would like to record my sincere appreci-ation and gratitude for his valuable guidance and helpful suggestion And also for hispatience and helpfulness, which was most certainly valuable an deeply appreciatedthroughout the course of the work

Thanks to Mr Teo Thiam Teck, the lab technician of the Power Electronics oratory Mr Teo had offered the author plenty of technical support and in many waysaccelerated And also thanks to Mr Woo and Mr Chandra of Electrical MachinesLaboratory for their help with laboratory equipments

Lab-Thanks to my friends Tripathi Anshuman, Kanakasabai Viswanathan, Zhang Tao,Deng Heng, Kong xin, Low Jim Meng for their concerned support and help me with-out reservation

With a deep sense of love and gratitude I thank my dearest husband Yijun As

my life partner, he gave me the most care, understanding and support during thosehard moments

Last, but not least, the author would like to thank all those who have helped herdirectly or indirectly in this project

1.1 General Statement 1

1.2 The Concept of Basic Universal Power Electronic Cell 3

1.2.1 Introduction 3

1.2.2 Conceptual Design of A Universal Power Electronic Cell 4

1.3 The Concept Of Building Distributed Power Systems Using UPEC Cells 6 1.3.1 Parallel input parallel output operation 6

1.3.2 Parallel input serial output full bridge operation 7

1.3.3 Parallel input serial output three phase operation 8

1.4 Thesis Layout 8

2 Literature Review 10 2.1 Distributed Power Systems 10

2.2 Overview Of Power Electronics Building Blocks (PEBB) 12

2.2.1 Overview 12

2.2.2 The PEBB Concept 14

2.2.3 Three Design phases of PEBB 16

2.3 The Investments in PEBB Program 18

2.3.1 Plug and Play Power 19

2.3.2 Cellular Design, PEBB Partition 20

2.3.3 Hierarchical Design 21

2.4 Design Issues in PEBB System Integration 22

2.4.1 Hard Switching PEBB 22

2.4.2 Soft Switching Techniques for PEBB 24

2.4.3 Power Electronics Packaging Technology for PEBB 28

2.4.4 EMI Issues in PEBB System Integration 31

2.4.5 Power Integration Issues of PEBB 32

2.5 Distributed Software Architectures of PEBB-based DPS 33

2.5.1 Centralized Architecture 34

2.5.2 Distributed Architecture 35

2.6 Motivation and Objective 40

3 The Basic UPEC Cell 43 3.1 Circuit Structure 43

3.1.1 The Specifications 44

3.1.2 Design Consideration 44

3.1.3 Sine Triangle PWM Scheme 52

3.2 Control Analysis and Design for The Single UPEC Cell 55

3.3 Close Loop Control Design 57

3.3.1 Inner Current Control Loop 58

3.3.2 Outer Voltage Controller 61

3.3.3 Controller Implementation 64

3.4 Circuit Implementation 66

3.4.1 Power Circuit Components 67

3.4.2 Driver Auxiliary Circuit 67

3.4.3 Layout Consideration 70

3.5 Discussion of Simulation and Experimental Results 73

3.6 Summary 74

4 Distribution Power Systems - Parallel-Parallel Operation Using UPEC Cells 80 4.1 Introduction 80

4.2 Circuit Implementation 81

4.3 Synchronization Scheme For Parallel Parallel Configuration of UPEC Cells 86

4.3.1 Phase-Lock-Loop 87

4.3.2 Internal Generated Sine Reference 87

4.3.3 A New Synchronization Scheme 90

4.4 Imbalance Problem In Power Distribution System 97

4.5 Load Current Sharing Problem 103

4.5.1 The Analysis for Load Current Sharing 103

4.5.2 Different Scheme For Load Sharing Distribution 108

4.5.3 The Load Current Sharing Scheme Analysis Using In Parallel Parallel Configuration 110

4.6 Summary 115

5 Distribution Power Systems - Full Bridge Operation and Three Phase Operation Using UPEC Cells 121 5.1 Full Bridge Operation Using UPEC Cells 121

5.2 Full Bridge Configuration Using UPEC Cells 122

5.2.1 Synchronization Problems 128

5.2.2 The Simulation and Experimental Results 129

5.3 Parallel Input Three Phase Output Operation 130

5.3.1 Three Phase Inverter Investigation 130

5.3.2 Configuration Using UPEC Cells 132

5.3.3 Synchronization Problems 136

5.3.4 The Simulation and Experimental Results 137

5.3.5 Multi-phase systems 139

5.4 Summary 140

6 Network Communication Investigation 147 6.1 Survey of Local Area Network Architecture 148

6.1.1 Star Topology 148

6.1.2 CSMA/CD Topology 149

6.1.3 Token-Ring Topology 150

6.1.4 Token-Bus Topology 151

6.2 Deterministic Ethernet Real-Time Control 152

6.2.1 Network Requirement of Hard Real-Time Systems 152

6.2.2 Non-Determinism in Ethernet CSMA/CD 153

6.2.3 Investigation of CSMA/DCR Deterministic Collision Resolu-tion Algorithm 153

6.3 The Investigation Of UPEC Communication Protocol 154

6.3.1 Structure Of Communication Topology 154

6.3.2 System Overview 156

6.4 Summary 161

if such cells are used to obtain multi-phase systems In this thesis, the focus is

on the DC/AC systems using the basic cell The report first introduces the basicconcept of the UPEC cell The basic cell is based on the most common half-bridgeleg structure because it is the commonly used switching topologies that can be found

in AC/DC, DC/DC, and DC/AC conversion In this report, only hard switchedDC/AC converters structures are used This kind of structure can also be easilyextended to the other two converter configuration by changing the reference wave.The cell includes power semiconductors devices, the required passive components, thedriver electronic circuits and the controller to get a standard, self-contained units.After introducing the basic structure and operating concept of the UPEC cell,the cell is designed to meet certain performance criteria such as the output powerrating, carrier frequency and harmonic content etc A digital closed loop controller

is designed and implemented on the DSP TMS320F243 to control the function of thecell Experimental results of the close-loop controlled P.E system are provided.Based on the analysis of the basic UPEC cell structure and development, parallelinput parallel output, full bridge and three phase configurations can be implemented

by using it In the parallel-parallel configuration, the main problem is of nization and circulating current The output voltage and phase angle of the respec-tive inverters must have the same value for the parallel operation at every instant,otherwise, the circulating current will occur between the power cells To solve thesynchronization problem, we normally use the phase lock loop (PLL) method [1].However, a simple and practical way is used to solve the synchronization problem.Using the simple serial data communication to transfer synchronization information, agood synchronization is achieved Furthermore, it is very easy to extend the synchro-nization method to more cells Parallel connection can also be realized because this

synchro-synchronization method does not depend on the cell number and configuration Thusfull bridge and three phase connection can be realized In the parallel-parallel con-figuration, the average current sharing scheme is used to solve the circulating currentproblem This method can also reduce the effect of difference in circuit parameters

of parallel cells

Finally, a study of communication delays and errors is carried out to bench markthe requirements of a future communication network

List of Figures

1.1 Basic UPEC Cell Topology 5

2.1 Basic DPS Structures [2] 12

2.2 The View of A PEBB Module [3] 14

2.3 Some of The Common Switching Topologies 16

2.4 A Power Electronics Building Block (Hard-switching) 17

2.5 Power Electronic Building Block [4] 17

2.6 Hard Switching PEBB With Parasitics 22

2.7 Topology of ARCP Soft Switching PEBB 26

2.8 Topology of Improved ZCT Soft Switching PEBB 27

2.9 A PEBB-based Distributed Power System [5] 33

2.10 Plug and Play Power Electronics System Architecture [6] 36

2.11 Block Diagram of Designed Application Manager [6] 37

2.12 Block Diagram of Designed Hardware Manager [7] 38

2.13 Data Formats In Distributed Controller Network [7] 40

3.1 The Single UPEC 43

3.2 Input Capacitor Circuit 45

3.3 Output L-C Filter Circuit 46

3.4 Cut-off Frequency Simulation of The Output Voltage Total THD Vs Carrier Frequency For 10KHz 49

3.5 Pulse-Width Modulation 53

3.6 One-leg switch-mode inverter 54

3.7 Equivalent Circuit of The Basic UPEC 57

3.8 Current Controller Block Diagram 59

3.9 Unit Step Response of The Close-loop Current Control 60

3.10 Different PI Gain Values 60

3.11 Voltage Controller Block Diagram 62

3.12 Unit Step Response of The Close-loop Voltage Control 63

3.13 Different PI Gain Values 64

3.14 Proposed Control System Block Diagram 64

3.15 Current and Sensing Interface Block Diagram 65

3.16 Driver Auxiliary Circuit 68

3.17 Driver Output Signals(experimental) (1)The top driver signal(20V/Div), (3)The bottom driver signal(20V/Div) 69

3.18 Current and Voltage Sensing and Scaling Block Diagram 70

3.19 Current and Sensing Interface Block Diagram 71

3.20 Junction Between Two Wide Copper Tracks Is Less Inductive When Several Spaced Links Are Used Rather Than A Single Link 71

3.21 Configuration of Decoupling Capacitors 72

3.22 Linear Power Path-Minimize Noise Coupling From Switching Circuits Into Input And Outputs 72

3.23 IGBT switches output waveform (experimental).(2)IGBT switches out-put voltage waveform (500V/Div), (M)the spectrum analysis 73

3.24 IGBT switch over shot voltage when turn off (experimental) (4)the bottom IGBT (500V/Div) 74

3.25 The basic UPEC output current and voltage waveforms (simulated).(i)output current(5A/Div), (ii)output voltage(200V/Div) 75

3.26 The basic UPEC output current and voltage waveforms (experimen-tal).(3)output current(10A/Div), (4)output voltage(200V/Div) 76

3.27 The dynamic response when load changes(simulated).(i)output cur-rent(5A/Div), (ii)output voltage(200V/Div) 76

3.28 The dynamic response when load changes(experimental).(3)output cur-rent(5A/Div), (4)output voltage(200V/Div) 77

3.29 The detail of the dynamic response when load changes(experimental).(3)output current(5A/Div), (4)output voltage(200V/Div) 77

3.30 Main Program Flow Chart 78

3.31 ISR Flow Chart 79

4.1 Parallel Parallel Configuration Using Two UPEC Cells 82

4.2 Two Parallel Connected UPEC Cells 82

4.3 The Demonstration of Counter 89

4.4 The Flow Chart of Using GPIO Pins 91

4.5 The Demonstration Using Switch 92

4.6 The error voltage between two parallel parallel configuration UPEC cells’ voltages(experimental) (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1−V4) voltage(100V/Div) 93 4.7 Parallel Parallel Voltage Error VS Time Delay of Vcarrier 94

4.8 Parallel Parallel Voltage Error VS Time Delay of Vref 95

4.9 The Flow Chart of Synchronization Using SPI Module 96

4.10 The error voltage every 5 fundamental cycles’ synchronization rate(experimental).(1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output volt-

age(50V/Div), (3)Error (V1− V4) voltage(20V/Div) 974.11 The error voltage every 1 fundamental cycles’ synchronization rate(experimental).(1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output volt-

age(50V/Div), (3)Error (V1− V4) voltage(10V/Div) 984.12 The error voltage every 14 fundamental cycles’ synchronization rate(experimental).(1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output volt-

age(50V/Div), (3)Error (V1− V4) voltage(10V/Div) 994.13 The error voltage after different L-C filter(experimental) (1)UPEC

cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div),

(3)Error (V1− V4) voltage(10V/Div) 1004.14 The error voltage after different L-C filter(simulated) (1)UPEC cell1

output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div),

(3)Error (V1− V4) voltage(5V/Div) 1014.15 Error Voltage Between Two UPEC Cells 1024.16 The Analysis for The Variation of L-C Filter Parameters X = ZL1/ZL2,

Y = ZC1/ZC2, Z = ZC1

ZC1+ZL1 − Z C2

ZC2+ZL2 1034.17 Block Diagram of Two UPEC cells Under Single-Loop Control 1044.18 Equivalent Circuit of Two Parallel Connected UPEC Cells Under Single-

Loop Control 1054.19 Current Sharing Block Diagram Of The Parallel Parallel UPEC Cells 1114.20 Control Loop Diagram Using Average Current Sharing 1124.21 Block Diagram of Two Parallel-Connected UPEC Cells Using Auto-

matic Current Sharing Average Current Method 1134.22 The error voltage using load current sharing control(simulated) (i)UPEC

cell1 output voltage(100V/Div), (ii)UPEC cell2 output voltage(100V/Div),(iii)Error (Vi− Vii) voltage(10V/Div) 1144.23 The error voltage using load current sharing control(experimental)

(1)UPEC cell1 output voltage(200V/Div), (4)UPEC cell2 output

volt-age(200V/Div), (3)Error (V1− V4) voltage(50V/Div) 1154.24 The output current and voltage waveforms in parallel parallel con-

nection (simulated) (i)Output voltage(100V/Div), (ii)Output

cur-rent(2A/Div) 1164.25 The output current and voltage waveforms in parallel parallel con-

nection (experimental) (1)Output current(5A/Div), (2)Output

volt-age(100V/Div) 1174.26 The output current waveforms in parallel parallel connection(simulated)

(i)Output current(2.5A/Div), (ii)UPEC cell1 output current(1A/Div),

(iii)UPEC cell2 output current(1A/Div) 117

4.27 The output current waveforms in parallel parallel connection(experimental).

(3)Output current(2A/Div), (1)UPEC cell1 output current(2A/Div),

(2)UPEC cell2 output current(2A/Div) 118

4.28 The output current dynamic response when load changes(simulated)

(i)Output current(5A/Div), (ii)UPEC cell1 output current(2.5A/Div),

(iii)UPEC cell2 output current(2.5A/Div) 118

4.29 The output current dynamic response when load changes(simulated)

(1)UPEC cell1 output current(2A/Div), (2)UPEC cell2 output

5.1 Single-phase full-bridge inverter 122

5.2 Full-Bridge Single Phase Configuration Using Two UPEC Cells 123

5.3 Full Bridge Output Voltage Between Two UPEC Cells 125

5.4 The Control Block Diagram in Full Bridge Operation 129

5.5 The output voltage waveforms of full bridge connection UPEC

(simu-lated) (i)full bridge output voltage(200V/Div),(ii)Cell1 output

volt-age(100V/Div), (iii)Cell2 output voltage(100V/Div) 130

5.6 The output voltage waveforms of full bridge connection UPEC

(ex-perimental) (4)full bridge output voltage(200V/Div),(2)Cell1 output

voltage(100V/Div), (3)Cell2 output voltage(100V/Div) 131

5.7 The output current and voltage waveforms of full bridge connection

UPEC (simulated) (i)full bridge output current(5A/Div),(ii)full bridge

output voltage(200V/Div) 132

5.8 The output current and voltage waveforms of full bridge connection

UPEC (experimental) (1)full bridge output current(5A/Div),(4)full

bridge output voltage(200V/Div) 133

5.9 The dynamic response of output current and voltage waveforms of

full bridge connection UPEC (simulated) (i)full bridge output

cur-rent(10A/Div),(ii)full bridge output voltage(200V/Div) 134

5.10 The dynamic response of output current and voltage waveforms of

full bridge connection UPEC (experimental) (1)full bridge output

current(5A/Div),(4)full bridge output voltage(200V/Div) 135

5.11 Three phase inverter 136

5.12 Three Phase Configuration Using Three UPEC Cells With Delta Load 137

5.13 Three Phase Configuration Using Three UPEC Cells With Star Load 138

5.14 Three Phase Vector Relation Diagram 139

5.15 The Control Block Diagram in Three Phase Operation 141

5.16 The phase(line-to-line) voltage waveforms of three phase connection

UPEC with Delta Load Connection (50V/Div)(simulated) 142

5.17 The phase(line-to-line) voltage waveforms of three phase connection UPEC with Delta Load Connection 100V/Div(experimental) 142

5.18 The phase and line-to-line current waveforms of three phase connection UPEC with Delta Load Connection (simulated) (i)Line-to-line current wavefomrs(10A/Div),(ii)Phase current waveforms(5A/Div), 143

5.19 Output Phase Current with Delta Load Connection 5A/Div (experi-mental) 143

5.20 Output Line-to-Line Current with Delta Load Connection 5A/Div (ex-perimental) 144

5.21 The output voltage waveforms of three phase connection UPEC (sim-ulated) (i)Output line-to-line voltage(200V/Div) (ii)Output phase voltage(100V/Div) 144

5.22 The line-to-line voltage waveforms of three phase connection UPEC with Star Load Conncection 100V/Div(experimental) 145

5.23 The phase current waveforms of three phase connection UPEC with Star Load Conncection 1A/Div(experimental) 145

5.24 The line-to-line voltage waveforms of three phase connection UPEC with Star Load Connection 100V/Div(Simulated) 146

5.25 The phase voltage waveforms of three phase connection UPEC with Star Load Connection 20V/Div(experimental) 146

6.1 Star Topology 149

6.2 CSMA/CD Topology 150

6.3 Token-Ring Topology 150

6.4 Token-Bus Topology 151

6.5 UPEC Bus Topology 155

6.6 Communication Hierarchy 155

6.7 State Transition Diagram for Communication Controller 157

6.8 Data Format of Start-Up Frame 159

Abbreviation and Symbols

PEBB Power Electronic Building Block

UPEC Universal Power Electronic Cell

VLSI Very-Large-Scale-Integrated

ZVS Zero-Voltage Switching

IGBT Insulated Gate Bipolar transistor

GTO Gate Turn-off Thyristor

EMI Electro Magnetic Interference

PEOS Power Electronics Operating System

THD Total Harmonic Distortion

VSI Voltage Source Inverter

CSI Current Source Inverter

ISR Interrupt Service Routine

SPI Serial Peripheral Interface

DSP Digital Signal Processor

GPIO General Purpose Input and Output

CSMA/CD Carrier Sense with Multiple Access/Collision detection

η Efficiency of Power Supply

ζ Damping Ratio

ω Natural Frequency

fs Carrier Frequency

f1 Modulating Frequency

ma Amplitude Modulation Ratio

mf Frequency Modulation Ratio

kp Proportional Gain

Ti Integral Gain

2010, it is expected that up to 80% of electrical power will be processed by powerelectronics equipment and systems With the widespread use of cost-effective powerelectronics technologies, the total energy consumption can be reduced by more than

To process such a huge amount of electric energy, power electronics and relatedpower processing technologies have become an enabling infrastructure technologywith a significant potential impact on the economy This is manifested through theincreased energy efficiency of equipment and processes using electrical power, andthrough higher industrial productivity and higher product quality, which results fromthe ability to control precisely the electrical power for manufacturing operations.Sales of power electronics equipment exceeded $60 billion each year, and another $1trillion in hardware electronics sales [3]

Power electronics plays a major part in most industrial and commercial systems.For efficient use of power in these systems, switched mode power converters are nec-essary Requirements of many of these system are unique, hence, power convertershave to be specifically designed for each of them The design includes, not only thepower semiconductors devices, but energy storage elements such as inductors andcapacitors In addition, protection, signal processing and control systems have to

be integrated The whole converter system needs to be packaged for high thermalefficiency and EMC compliance All these factors make the design of power electronicsystem very complex Furthermore, the design process is compounded by strong influ-ences of parasitic effects of different subsystems For example, the design of magneticcomponents such as inductors and transformers is fairly involved process Parameterssuch as operating frequency, VA rating greatly influence the design and choice of ma-

terial Therefore engineering cost of power electronic systems tend to be substantial.Can these cost be reduced? Can we design a universal power electronic cell that can

be programmed to perform as any of the several converter topologies? One of suchapproach is the use of Power electronic building blocks Power electronic buildingblocks is a new paradigm in designing power electronic systems Various conceptshave been proposed under this broad umbrella We would like to extend this ideafurther

to reduction of engineering costs in power electronic systems Once standardized

and produced in large numbers, the cost of this cells will be lower Engineeringimplementation of power electronic systems would then be reduced to “Plug-n-Play”using standard cells.

Cell

Power electronic converters can be broadly classified as DC/DC, DC/AC, AC/DCand AC/AC converters We can further classify them as hard-switched or softswitched converters Each of these converters consists of power electronic switchesand energy storage elements They form the power electronic circuit The control ofthe switch will depend on the mode of power conversion required Of the four topolo-gies described above, DC/DC and DC/AC are realized using controllable switches.AC/DC and AC/AC converters have been traditionally realized using line commu-tated devices such as thyristors and diodes However, these configurations lead to apoor power quality on the line side Switched mode rectifiers and boost-type recti-fiers can improve the power quality on the line side; but on the other hand, switchedmode configurations for AC/AC converters have not gained much ground However,AC/AC conversion can be carried out using an intermediate DC link Substantialbody of research exists for converters with a DC link Therefore, we can safely saythat, all converter modes described above can be realized using a basic configurationwith a DC link Using the above facts, we can conceptualize the basic cell

Converter topologies with DC link can be used to realize most of the power version modes Hence, we will choose a cell to have a DC link A basic half bridgeconfiguration with controllable switches and diodes can be used to produce DC/DC,DC/AC and AC/DC power converter modes In addition, we add filter componentssuch as an inductor and a capacitor; this would form the basic cell I use a hard-switched basic cell topology to explain the concept of cells and their use in variousconfigurations The basic cell topology is shown in Fig.1.1 It has 6 power terminals

WVL

C

Figure 1.1: Basic UPEC Cell Topology

and a control bus By connecting the terminal V to terminal M, and connecting theload between U and V, we can implement a basic half bridge topology This cell can

be operated either in DC/DC, DC/AC or AC/DC mode In my research work , Iconcentrate on the DC/AC operation using the cell U and W will be shorted forthis configuration The building of the basic UPEC cell will be discussed in detail inChapter 3

1.3 The Concept Of Building Distributed Power

Systems Using UPEC Cells

Modern electronic systems need more complex power electronic systems to meetthe requirements for reliability, high density and voltage regulation As a result, aconventional centralized power system with a single high power converter may not beoptimal for the systems of the future New trends in the field of high and mediumpower systems use Distributed Power Systems instead of large and lumped powerconverters [2] These allow standardized designs

For these reasons, we can find that the UPEC cell’s structure is very simple It

is the basic element for many other power converter topologies which are relativelycomplicated compared to the cell These standard cells can be connected to formdifferent circuit topologies and to implement different power conversion functions Inour works, the DPS is configured with a common DC bus and produces a constant

AC voltage output This system can be built by using the basic cells in variousconfigurations that will be described further

1.3.1 Parallel input parallel output operation

One approach to build a large power inverter system is the use of a cellular ture, in which many quasi-autonomous inverters, called cells, are paralleled to create

struc-a single inverter system [10], [11] The use of qustruc-asi-struc-autonomous cells mestruc-ans thstruc-at the

whole system performance will not be compromised by the failure of one cell Theproposed UPEC cell exactly has the quasi-autonomous characteristics In the paral-lel parallel configuration, the UPEC cells share the same input and output busses,but each cell process only to a fraction of the total system power The frequencyand phase of the paralleled cells sine output voltage should have the same values.This method is believed to be an appropriated solution to supply more reliable andflexible power However, we also need to solve problems such as the synchronization

of all paralleled cells in frequency, phase and amplitude to guarantee equalization ofparallel connection without circulating current; the output current sharing of the par-allel inverter to avoid internal dissipation between parallel cells more over the outputvoltage regulation which will cause the inverter switching interference and the outputvoltage oscillations [12], [13], [14] This problem is described in detail in Chapter4

1.3.2 Parallel input serial output full bridge operation

The other approach to build a large power inverter system is to use a full bridgeinverter With the same dc input voltage, the maximum output voltage of the fullbridge inverter is twice that of the half bridge inverter This implies that for thesame power, the output current and the switch currents are one-half of those for

a half bridge inverter At a high power level, this is a distinct advantage, since itrequires less paralleling of devices [15] In this configuration, the UPEC cells sharethe same DC input and the output is serially connected If we let the phase difference

of two cells output voltage 180o degree, we can realize the full bridge operation usingtwo standard UPEC cells.

1.3.3 Parallel input serial output three phase operation

In applications such as un-interruptible ac power supplies and ac motor drives,three phase inverters are commonly used to supply three phase loads It is possible

to supply a three phase load by means of three separate single-phase inverters, whereeach inverter produces an output displaced by 120o (of the fundamental frequency)with respect to each other [15] In this configuration, three UPEC cells share thesame DC input and the output is connected serially in star or delta style The details

of the full bridge and three phase configurations will be discussed in Chapter 6

Chapter 1 gives a brief introduction to the concept of the universal power tronics cell (UPEC) and the concept of building the distributed systems It alsointroduces the structure of this thesis

elec-Chapter 2 reviews the distributed power system development state of the search results related with PEBB such as the concepts, development, investment andthe distribution structures of the PEBB It also gives the difference between the PEBB

re-and UPEC re-and the aims of this research work.

Chapter 3 is mainly about the analysis, simulation and building of the basicUPEC module in detail The contents include mathematic model analysis, controlparameter derivation, circuit implementation, controller programming flow chart andthe comparison of simulated and experimental results of the cell

Chapter 4 and Chapter 5 form control part of the thesis These two chaptersanalyze the possibilities of building the distributed power systems using UPEC cellsfrom the power electronics (hardware) level In Chapter 4, we connect the UPECcells in parallel parallel mode In this mode, the synchronization and the output loadcurrent sharing between paralleled cells are the most important problems we need tosolve After solving the synchronization problem, In Chapter 5, we can realize thefull bridge and three phase operations according to the same principle

Chapter 6 investigates and discusses the possible communication protocols tween the UPEC cells from the viewpoint of power electronics

be-Chapter 2

Literature Review

Unlike modern digital technology, which utilizes an array of developed components

or cells to build a system, modern power systems lack a high degree of integration andstandardization [16] Power electronics products are essentially custom-designed, with

a long design cycle time The equipment is designed and manufactured largely usingnon-standard parts [3] As a result, designers are often forced to build entire systemsfrom scratch each time, which is costly in engineering time as well as system reliability[16] Manufacturing processes are labor-intensive, resulting in high cost and poorreliability The need for low-cost, high-reliability, easy to use power processing system

is becoming more and more pronounced Industrial firms are under constant pressure

to produce power electronics products that are more power density, dependable and

durable, smaller in size, lighter in weight, and less costly to the consumer Without

a significant paradigm shift in power electronics technology, those objectives cannot

be achieved [3]

The widespread use of the DPSs has given the power supply industry the portunity to develop a standardized modular approach to power processing Thisapproach will enable significant improvements in the design and manufacturing pro-cess and enhance system performance and reliability DPSs offer many advantages topower system designers: high power capability, high efficiency, reliability, modularity,redundancy, reduced development cost and tightly regulated output voltage as needed

op-by today’s sophisticated electronic loads For these reasons, DPS are becoming moreand more common in many industries

According to ref.[2], the basic DPS structures may be classified as follows: cading, paralleling, source splitting, load splitting and stacking These structuresare shown in Fig.2.1 These structures are based on a set of Power ProcessingUnits(PPU)

cas-Traditionally, most PPUs are DC/DC PWM switching converters With the duction of the DPS, why not develop an integrated systems approach to standardizepower electronics components and packaging techniques in the form of highly inte-grated PPUs in order to provide significant improvements in quality, reliability andcost of power electronics systems? The PEBB concept is the one to meet this chal-lenge

V i1

V i2

Vb

V i

E) Stacking Structure

R L

RL1

R L2

RL

V

s3 V

s1

Figure 2.1: Basic DPS Structures [2]

(PEBB)

The Office of Naval Research (ONR) is developing power processors – Power tronic Building Blocks (PEBBs) to achieve: increased power density, “user friendly”design (“plug and play” power modules), and multi-functionality Digital controls,integrated with higher frequency and more robust power circuits, enable modularpower systems with lower size, weight, and cost – while increasing performance [17]

Elec-It is expected that the impact of improvements in power electronics technology andsystem integration via the PEBB approach can be compared to the impact realized byimprovements in very-large-scale-integrated (VLSI) circuit technology Applications

of VLSI circuit technology enabled rapid advances in computer and tions equipment, accompanied by a steady increase of the levels of standardization,volume and manufacturing ability and a decrease in manufacturing cost The PEBBapproach will follow suit It makes possible to increase levels of integration in thecomponents that comprise a power electronics system-devices, circuits, controls, sen-sors and actuators-integrated into standardized manufacturable subassemblies andmodules that, in turn, are customized for a particular application [3]

telecommunica-While the need to develop PEBB and power processing using an integrated systemapproach is clear, the task of developing PEBB components and processes suitablefor standard use in customized power electronics applications is significantly morecomplex than for low-power VLSI circuits Issues unique to power electronics includethe use of high-current injection devices, the monolithic integration of high-voltagepower devices and low-voltage devices for controls and sensors, the interconnection

of high-power devices and control devices on a common substrate, thermal ment, inductance and capacitance minimization in three-dimensional device packag-ing, and the integration of passive high-power components Successfully addressingthese wide-ranging, multi-disciplinary issues is a prerequisite for realizing the fullpotential impact of power electronics [3]

manage-2.2.2 The PEBB Concept

Power electronics building blocks, or PEBBs, are integrated subassemblies or ules capable of processing electric power A PEBB is not a specific semiconductordevice, a passive component, or a circuit topology A typical PEBB may look like theone shown in Fig.2.2 [3] Although it looks similar to a typical commercially available

mod-Power Port (Output)

Communication

Port, System

Control

Power Port (Source)

Communication Port, System Control

Figure 2.2: The View of A PEBB Module [3]

power semiconductor module, the inside of a PEBB contains much more It includesgate drive, level shifting, sensing, protection, power supply and passive components,

in addition to power semiconductor devices [3] It integrates all these technologies ofelectrical, mechanical and thermal denominators [17] The goal of the PEBB develop-ment is to create a power processing component that moves most of the design, awayfrom specific circuit topology and power electronic switch and associated inductors,capacitors , and other ancillary component selection to a systems level [18]

As a building block, a PEBB has two types of interface ports for interconnections:

power ports and communication ports [3] Depending on the instructions given tothe communication ports, the PEBB can function as a DC/DC converter, an ACinverter, a synchronous rectifier, or a motor controller Several PEBBs can connecttogether through these ports to form power electronics systems as simple as smallDC/DC converters or as complicated as large distributed power systems MultiplePEBB modules working together would perform system-level functions, such as volt-age scaling, energy storage and conversion, and impedance matching [18] Like a set

of children’s interlocking blocks, PEBBs will be a rational and simple set of blocksand procedures that most any designer or architect can use to build electrical systems[17]

The essential design feature for PEBB is its commonality The ultimate design goalwould be to design as few as possible common PEBBs for most of the applications Inwidespread applications of power electronics, a minimal group of power semiconductorswitch configurations could satisfy most application requirements in a wide powerrange Even though it is impossible to find one or a few switching topologies thatcan cover all applications, these minimum-complexity PEBBs could be combinedwith other components to assemble most of the common power converters Fig.2.3shows some of the commonly used switching topologies that can be found in AC/DC,DC/DC and DC/AC conversion All converters in Fig.2.3 consist of the half-bridge legstructure as the building block In this case the voltage can be applied bi-directionally,and the current flows only in one direction

AC/DC Boost Rectifier

DC/AC VSI (Inverter)

DC/DC Converter (a) Voltage source

converters

Vo a

b

c

a b c Vg

AC/DC Boost Rectifier

DC/AC CSI (Inverter) (b) Current source

converters

Figure 2.3: Some of The Common Switching Topologies

Therefore, the half bridge inverter is defined as a PEBB and will be integrated asone three-terminal component as shown in Fig.2.4 [19]

According to refs.[17], [20] and [21], there are three design phases of the PEBBprogram

1 PEBB-1, the first phase demonstrated that multiple application could be

sat-Figure 2.4: A Power Electronics Building Block (Hard-switching)

isfied using the same set of hardware Each application had its own set ofsoftware instructions PEBB-1 proved that a single set of hardware could per-form many functions There are five power port in the first PEBB device - 2

DC and 3 AC/DC ports as shown in Fig.2.5, also see reference [22] This device

+ -

A B C Comm [0 x]

A [0 x]

PEBB

Figure 2.5: Power Electronic Building Block [4]

corresponds to a three phase bridge In addition to the power ports, there is

a communication bus, an analog bus and a digital bus Making only externalconnection changes, PEBB-1 demonstrated the following applications: a)DC to

AC inverter, b)AC to DC converter, c)DC to AC motor controller, d)AC to DC

boost converter and e)DC to DC boost converter.

2 PEBB-2, the second phase focuses on developing and defining PEBB form.PEBB form is defined primarily by packaging considerations such as thermal,EMI, interconnections, interfaces, communications, sensors, control, manufac-turing economics, reliability, passive devices, etc PEBB-2 will demonstratehigher-power, faster-switching devices and micro electronic integration

3 PEBB-3, will demonstrate a fully optimized PEBB prototype in form, fit, andfunction The critical technological improvements manifested in PEBB-3 arethe use of two-sided cooling, ultra-fast turn-off thyristors, distributed/integratedcontrol architecture with software configuration and control A system designer,with minimal power background, will be able to construct an power electronicsystem by using these standard-building blocks, quickly, simply, reliably

Over the past five years, the U.S.Navy has invested in an array of power electronictechnology via the PEBB program This investment is crucial to existing and futureNavy ships and is also crucial to the power electronics industry

Like the Internet, the PEBB program focuses on core issues and attempts toassure that future US Navy requirements can be fulfilled from commercial-off-the-shelf technology Ideally, this is a win-win situation The Navy wins by getting

affordable power electronics The power electronic industry wins by getting supportfor core science and technology, which would be otherwise unaffordable.

According to ref.[4], many modern paradigms have been studied for adaptation topower electronics throughout the PEBB program They are open plug and play archi-tecture, cellular design, hierarchical design, integration, and concurrent engineering

The idea of an open plug and play architecture is to build power electronics systems

in much the same way as personal computers Power modules would be plugged intotheir applications and operational setting made automatically The application knowswhat is plugged into it, who made it, and how to operate with it Each power modulemaintains its own safe operating limits Realization of this vision will require acommunity to develop standard interfaces and protocols The benefit of it is to alloweach section of the power equipment to be independent of the others

There are two motivations for plug and play architecture One is for lower costand increased application The demand for new power electronics products exceedsthe resources to supply them The next generation engineer want to design systems

on their computers and want power parts to come together like their PC components

do Open architecture multiplies the designer efforts and makes his expertise availablefor many more applications Furthermore, the partitioning allows a focusing of effortswithin the partitions and the development of high volume processes for partitioned

technologies Both the increased utilization of resources and high volume processeslead to lower cost.

“Return-on-investment” is another motivation Open plug and play architectureallows upgrades within each partition “Time-to-market” can be shortened by focus-ing on a partition rather than the whole system A new partition is inserted withother parts to make a new product This is just like upgrading a PC with a new videoboard based on a new “sub-micron” IC manufacturing process

2.3.2 Cellular Design, PEBB Partition

There would be three different levels of PEBBs according to the power range:switch cell and passive device-level PEBBs for high-power levels greater than 1MW;phase-leg PEBBs for medium power levels greater than 100KW and less than 1MW;converter-level PEBBs for low power levels less than 100KW Each of these primaryblocks are made of other basic blocks, such as: filter, power switching, and control.The power levels that define the low, medium, and high power boundaries will change

as technology changes

However, these primary blocks have electrical relationships, which transcend powerratings These simple relations lead to a cellular description or organization of powerelectronics The bridge, phase leg, and switching cell are and will be primary powerelectronic building blocks and thus “well posed” candidates for primary units of in-tegration Finally, these blocks would be snapped together to form equipment and

The task is to define the functions and interface requirements for each of thesepartitions Protocols for information transmitted across each interface need to bedefined BIOS and operating systems that apply to power equipment need to bedeveloped I/O and operating systems for power electronics must be highly reliableand capable of real time performance.

At this point, a generalized control hierarchy boils down to four controllers asfollows:

• Power switch controller

• Topology of circuit controller

• Application controller

• System controller

Each of these controllers is programmable and multi-functional

2.4 Design Issues in PEBB System Integration

The PEBB approach is not just a process of standardization; it is also a process

of integration The resulting PEBBs should have small size, light weight, high bility, and easy system-level configuration To achieve these basic requirements, thefollowing sections address the issues related to increasing the switching frequency,reducing package parasitics, improving the thermal management and reliability, andproviding flexible and intelligent system configuration [3]

The equivalent circuit of Fig.2.4 is shown as Fig.2.6 The parasitic inductance is

Vdc

Ipebb Lstray

Cdclink

Vs +

Figure 2.6: Hard Switching PEBB With Parasitics

mainly the stray inductance between the DC link and PEBB since the small internalPEBB parasitic inductance can be ignored Based on the Eq.2.1

VL(t)= Lstraydi

principle, the parasitic indectance will cause a huge voltage overshoot because of therapidly changing current at IGBT turn off The voltage spike could kill the device athigh power There are two ways to alleviate this problem: (1) slow down the currentchanging or force it to zero before switch turn off, (2) add a clamping capacitor toabsorb the rapidly changing current of the device and thereby reduce the rate ofchange of current in the parasitic inductance [19].

For hard-switching PEBB, a large, high frequency clamping capacitor is closelyadded to the PEBB module Moreover, the capacitor will cause some problems: highfrequency ringing at the PEBB terminal and some high frequency loops with theparasitic inductance and the clamping capacitors of others

Additionally, the high switching loss problem is more concern for high powerapplications, since it will limit the switching frequency and prevent reduction in thesize and cost of passive components and limit the bandwidth of control loops ForIGBTs, the turn-off loss is dominant because the turn-off current switching has adelay with respect to the junction voltage and the turn-off current is always largerthan the turn-on current

To reduce hard switching voltage overshoot, a clamping capacitor is used Toreduce hard switching loss, a snubber directly in parallel with the device is sometimesused However, the snubber makes the turn-on reverse recovery worse and then thetotal switching loss may be higher