Experimental computational studies on transition metal silicides for novel applications in advance CMOS technologies

The kinetics of silicide growth is characterized by 1 formation rate which represents the effective diffusion coefficient of the most mobile species through the silicide layer and 2 acti

1.1 Evolution of CMOS Technologies

The semiconductor revolution began in 1947 with bipolar devices fabricated

on slabs of polycrystalline Ge Single-crystalline materials were later introduced, making possible the fabrication of junction transistors 2 Development of Si-based devices was initially hindered by the easy oxidation of Si, necessitating a new generation of crystal pullers with improved environmental control to prevent SiO2

formation Later the stable Si/SiO2 system with low interface-state density eventually enabled the migration from bipolar devices to field-effect devices in 1960 3 By 1968, complementary metal-oxide-semiconductor (CMOS) devices and polysilicon gate

technology allowing self-alignment of gate to source/drain had been developed 4, 5 CMOS technology employs both n-channel (NMOS) and p-channel (PMOS) transistors to form logic elements The cross-section of a CMOS device is illustrated

in Figure 1.1 The advantage of CMOS technology is that very little current is needed

to maintain the device state and substantial current is drawn only during the state transition, resulting in significant power saving The innovations of CMOS technology permitted a significant reduction in power dissipation and device overlap capacitance, thus operation frequency was significantly improved to make them essential components in modern ICs

Figure 1.1 Cross section of modern CMOS transistor with an n-channel MOSFET

and a p-channel MOSFET

1.1.1 Scaling of CMOS Technology

In 1965, Gordon E Moore, the co-founder of Intel Corp., predicted that the number of transistors on an IC would double every eighteen months to two years, which has been acting as a guide for the IC industry ever since 6 Figure 1.2 plots

follows the Moore’s Law by Intel CPUs With increase of the number of the transistors integrated, the cost of implementing the same functions decreases While silicon-based components and platform ingredients gaining in performance, they become exponentially cheaper to produce, and therefore more plentiful, more powerful, and more seamlessly integrated into our daily lives Therefore, the driving force for each technological generation has always been the same: enhanced performance and functionality, improved reliability, increased throughput, decreased power dissipation, and reduced cost

Figure 1.2 Intel CPU processing power projection by Moore’s Law (Cited from

http://www.intel.com/technology/mooreslaw/)

CMOS devices are now being scaled to gate lengths below 50 nm and Moore’s prediction suggests that the scaling is likely to continue for at least another

decade 7 Significant challenges are unavoidable when the MOSFET gate lengths are reduced In particular, the gate oxide thickness in state-of-the-art production devices

is now below 2 nm and increases quantum mechanical tunneling of charge through the gate insulator, resulting in the off-state current increase 8 A secondary effect of the reduction of gate insulator thickness and the required high channel doping is the reduction of electron and hole mobilities in the inversion layers of CMOS transistors through interactions with the charges in the gate The degradation of the carrier mobility lowers the drain current and increases band-to-band tunneling across the junction and gate-induced drain leakage (GIDL) Moreover, statistical fluctuation of channel dopants causes increasing variation of the threshold voltage, posing difficulty

in circuit design while scaling the supply voltage Therefore enormous efforts and a number of technology solutions are being pursued to circumvent these problems

1.1.2 Advanced CMOS Technologies

Silicon is the material which has dominated the semiconductor industry for over 97% of microelectronic products over 30 years In conventional Si technology, CMOS is one of the most popular devices because of low cost, simple processing as well as high input impedance However, as a consequence of lower mobility of holes compared with electrons in Si, the p-channel devices are inferior to the n-channel ones

in terms of current drive capability and speed performance To match the current drive capability of NMOS devices, PMOS devices are designed about 2~3 times larger than NMOS, which adversely affects the level of integration and device speed

In order to improve the speed of ULSI circuits, new materials and device structures

are being proposed SiGe and Strained-Si heterostructure MOSFETs are two of the most favorable adventures 9-11

SiGe Heterostructure MOSFET:

SiGe technology has been driven to improve some of mediocre properties of silicon while retaining the current mature and cheap Si fabrication processes With the advent of the first SiGe heterojunction bipolar transistor (HBT) in 1998, the market for SiGe devices in the radio-frequency (RF) market has increased over time and is predicted to increase at 30% per annum in the future Being integrated into CMOS, SiGe devices are playing a more important role in semiconductor industry 12,

13

The first study on SiGe can be traced back to 1955 on the magnetoresistance

of silicon germanium alloys 14 In the 1950s, conceptual SiGe device was patented as

a bipolar transistor with a principle description in physics 15 Such a transistor required epitaxial growth of SiGe heterostructures, and it was only demonstrated until

1975 by Kasper and colleagues using molecular beam epitaxy (MBE) 16 Substantially the field has rapidly expanded in the era of the 1980s by developing growth technology, the 1990s by HBT devices, and the start of the 2000s by strained-

Si CMOS

Strain-induced modification of Si/SiGe films is found to have a significant impact on the band structure and carrier transport Theoretically, a lattice-mismatched layer grown on a thick substrate is pseudomorphic The lattice mismatch between Si and Ge is 4.2%, resulting in a very high misfit dislocation density 17 If a thin Si1−xGex film is grown on top of a Si1−yGey film, the top layer is compressively

strained when x > , while tensile strained when x y y < For a Si1−xGex film grown

on top of a Si substrate, the biaxial compressive strain results in the entire band offset

in the valence band while the band offset in the conduction band is very small This type of structure is favorable for hole confinement and has been exploited in several novel heterostructure devices, i.e HBTs, buried channel p-MOSFETs, and p-channel modulation-doped field effect transistors (p-MODFETs) 18

The addition of a compressively strained pseudomorphic Si1−xGex channel for PMOS can produce a buried quantum well By removing holes from a Si/SiO2

interface and placing them at a smoother heterointerface along the splitting of hole and heavy-hole bands, the reduced interface roughness scattering would increase the hole mobility However, to confine carriers in the quantum well, a large discontinuity (Ge content x 0.2) is required at the heterointerface The significant amounts of Ge in the quantum well increase alloy scattering therefore decreases the mobility of the holes 19

light-Strained-Si Heterostructure FET:

The advances in growth of strained-Si layers on relaxed Si1−xGex buffer layers have led to increased interest in Si-based heterojunction field effect transistors (HFETs) using conventional bulk Si technology

A smaller lattice constant silicon epilayer is under biaxial tension when grown

on a larger lattice constant relaxed Si1−xGex substrate For a strained-Si epilayer grown on relaxed Si1−xGex, a larger band offset is obtained in both the conduction and valence bands, relative to relaxed Si1−xGex layer 20 Since strained-Si does not suffer from alloy scattering, a significant improvement in carrier mobility can be achieved

21 It allows both electron and hole confinements in the strained-Si layer, making it useful for both n- and p-type devices for strained-Si based CMOS technology The tensile strain splits conduction band valleys with the ∆ valleys being lowered in 2energy and the ∆ valleys being increased in energy to such an extent that only the 4lower ∆ valleys have any significant population of carriers 2 22-24 It is the reduction

of inter-valley scattering which has been demonstrated to be held responsibility for the significant increases in the NMOS mobility both at room and low temperatures 25,

26 Strained-Si on insulator has also been used to enhance the mobility further by the reduction in capacitance through coupling to the substrate These mobility enhancements are at all vertical effective electric fields, demonstrating that the enhancements can be achieved in deep sub-micrometer transistors

Strained Si is more difficult to grow than strained Si1−xGex There are two major obstacles The first one is that bulk Si1−xGex substrate is currently not available yet The other reason is concentration of defects and dislocation due to large misfit Recent studies show that with the incorporation of a small amount of C atoms to develop new types of buffer layers, misfit dislocations may be reduced in the Si/SiGe material system 27 Anyway, the ability to achieve both NMOS and PMOS devices using strained Si provides a promising alternative for next-generation high-performance CMOS technology 28

1.2 Transition-Metal Silicides

No matter how the CMOS technology moving forward, as the link step between the front-end-of-line and back-end-of-line of the device manufacturing, self-

aligned silicidation (salicidation) has always been a critical process for the ULSI CMOS fabrication 29-31 Therefore, the fundamental mechanisms of their formation and stability are of great interests, and the solid-state reaction between a thin metal film and Si has been extensively and systematically analyzed 32-35

1.2.1 Formation of Silicides

In a salicidation process, silicides are simultaneously formed on the gate and source/drain areas without any additional masking After the gate and source/drain junctions are fabricated, a thin metal film is blanket deposited by physical vapor deposition (usually sputtering) on top of the whole wafer Silicide is formed with one

or two rounds of rapid thermal annealing The unreacted metal is thereafter removed

by selective wet etch which etches metal much faster than silicides The essence of the salicidation process is that only the metal in contact with the Si in source, drain, and polysilicon gate regions transforms to silicide, while the other part in contact with the SiO2 spacers remains as pure metal The metal silicide self-aligned with Si becomes an indispensable component for IC fabrication due to its low resistivity, good adhesion, and self-passivation nature It reduces the sheet, parasitic, contact, and interconnect resistance, thus shortening the RC delay time and consequently enhancing the performance speed of the device Furthermore, the self-passivating nature of silicides in oxygen-rich environment and its perfect and stable adhesion to

Si substrate make silicides the preferred materials over pure metals in CMOS processing Last but not the least, the self-aligning property helps to save more spaces for routing and eliminates misalignment at all

Fundamental mechanisms related to silicide formation involve phase formation sequence, growth kinetics and microstructures Two different mechanisms have been observed in metal/silicon reactions: diffusion-controlled and nucleation-

controlled mechanisms 36, 37 It is important to note that thin film reactions differ from those on bulk reaction Most of thin film formation involves both inter-diffusion and chemical reactions between phases at the interface 38

Diffusion-Controlled Mechanism:

For most of the metal/silicon thin film reactions, the square of formed silicide layer thickness varies linearly with time The slope of the curve gives the rate of formation and the variation with temperature gives the activation energy for growth The driving force for diffusion is the gradient of chemical potential expressed in the Nernst-Einstein equation as

and T is the temperature It was found that the growth rate and the diffusion

coefficient scale with ∆G, the free energy charge per moving atom when such an atom reacts to form a new phase The kinetics of silicide growth is characterized by (1) formation rate which represents the effective diffusion coefficient of the most mobile species through the silicide layer and (2) activation energy which is related to the silicide melting temperature The reaction kinetics of thin film is similar to that of bulk material, but the diffusivity is higher in thin film due to grain boundary diffusion enhancement 39, 40 Previous experiments showed that lattice diffusion of Ni atom is

slow with higher activation energy while grain boundary diffusion is rapid with lower activation energy in a Ni/Pt bilayer and Si diffusion couple

Nucleation-Controlled Mechanism:

When two phases are in thermal equilibrium, at either melting or evaporation points, the free energy change ∆G is equal to zero Any deviation from the equilibrium temperature can generate a driving force for the transition to another phase Reduction of volume free energy is opposed by an increase in surface energy induced by the creation of nucleus Some silicides such as NiSi2 form at relatively high temperature in an abrupt manner The formation of a new phase implies the creation of an additional interface The associated increase in the free energy is compensated by an equivalent or greater decrease of the surface energy due to the formation of the new phase

1.2.2 Popular Silicides for CMOS Technology

Self-aligned formation is the common feature of transition-metal silicides Table 1.1 lists some key properties of transition-metal silicides 41, 42

Among the silicides, the use of platinum silicide (PtSi) is mainly limited for bipolar transistors and IR detectors because of its low thermal stability and low Schottky barrier on n-Si Titanium silicides (TiSi2) is the most commonly used material till 0.25µm generation 43, 44 However, the sheet resistance of TiSi2 increases drastically with decreasing gate linewidth due to incomplete C49 TiSi2 to C54 TiSi2

transformation on narrow lines Cobalt silicide (CoSi2) is a good substitute for the generation of 0.18µm down to 65nm technologies 45 But the Si consumption of CoSi is much higher than other silicides As a result, nickel silicide (NiSi) which

shows linewidth-independent resistivity and low silicon consumption has become a promising candidate for ultra-shallow junction 46-48

Table 1.1 Important properties of common self-aligned silicides

Silicide Melting Point ( o C) Resistivity (µΩ⋅cm) Stable Temperature ( o C)

However, the desired C54 TiSi2 is formed from the nucleation and growth of the high resistivity C49 TiSi2, which gives rise to the question of scalability due to the difficulty of achieving low sheet resistance on deep sub-micron structures The key obstacle for scaling Ti silicide is the dependence of the C49 to C54 transformation on lateral dimensions, called fine-line effect in IC industry Z Ma et al examined the

C49-C54 phase transformation with in-situ transmission electron microscopy (TEM)

and found that the transformation proceeded by heterogeneous nucleation predominantly at triple C49 grain conjunctions, and grew by consumption of C49 grains 51, 52 An estimated 15% of the triple points of C49 grain boundaries are required to provide sufficient nucleation sites for C54 phase growth J A Kittl et al revealed the relation between C49 grain size and the feature linewidth with the nucleation density model and showed excellent agreements with the experimental results, which further confirmed that the nucleation sites of C54 phase located at the C49 triple grain boundaries 43

It has been shown that, when Ti thin film deposited on Si substrate (Ti/Si samples) is thermally treated by pulse laser annealing (PLA) at a very high ramp rate (~ 1010K/s) and very short duration (~ 10-8s), the TiSi2 formation mechanism changes and a new metastable hexagonal TiSi2 C40 phase is formed The C40 phase is formed via a solid-state reaction mechanism, whereas the undesirable C49 phase is formed via melting during PLA Hence C49 can be avoided with the PLA method by keeping the energy of the laser pulses sufficiently low Most importantly, the C40 phase has very similar basal planes as those of the C54 phase, where the former is constructed with an ABCABC stacking sequence while the latter has an ABAB sequence Due to

their structural similarity, C40 can act as a template whereby the technologically important C54 phase is formed on the C40 layer when the Ti/C40/Si sample is annealed using RTA The C54 formation temperature is also lowered and the C40 phase can also be transformed to C54 at a low temperature

Another significant improvement in narrow line sheet resistance is obtained with pre-amorphization implants (PAI), consisting of a shallow implant performed before Ti deposition to amorphize the top Si layer (typically ~30nm) 53 PAI induces

a smaller C49 grain size (~0.07µm) compared to conventional processes without PAI (C49 grain size ~0.22µm), enabling transformation of silicide films to the low sheet resistance phase on structures with dimensions down to 0.1µm However, PAI process still cannot go beyond 0.1µm And transient enhanced diffusion (TED) induced by PAI results in degradation of contact resistance, source–drain series resistance and drive current, and becomes more severe as junction depths are further scaled down An alternative approach to PAI is the addition of refractory metal impurities (Mo doping) close to the Ti/Si interface, leading to significant improvements in the formation of low resistivity C54 TiSi on sub-micron structures

54, 55

CoSi 2 :

Co silicide process has been successfully developed and widely adopted into 0.18µm down to 65nm generations Same as the C54 TiSi2, CoSi2 has a low resistivity of 14-20 (µΩ⋅cm), making it suitable for applications in salicide processes

In contrast to the conventional Ti silicide processes, nucleation does not limit the formation or transformation of Co silicide phases, even for lateral dimensions in the

deca–nano range As a consequence, Co silicide is not sensitive to scaling of lateral feature sizes Linewidth-independent low sheet resistance CoSi2 films are obtained down to 0.06µm dimensions 43, 56 Furthermore, a tendency of Co silicide to form thicker films at the edge of gate structures can result in a slight reverse linewidth effect with lower sheet resistance in the minimum geometry structures, which are more edge intensive

Although the line-width dependence in lateral dimension has been eliminated

by the implementation of Co silicide, there have been new issues related to vertical scaling of junction depth and poly-Si gate thickness, which may cause large diode leakage and affect gate oxide integrity (GOI) Higher temperature RTP and longer annealing time with slightly lower temperature are effective ways to suppress diode leakage, attributed to the dissolution of spikes and formation of smoother interface, because high annealing temperature promotes uniform lattice diffusion with a high activation energy and suppresses non-uniform grain boundary diffusion with a low activation energy 56, 57 Co contamination degrades gate oxide integrity due to the degradation of film and interface morphology at high temperature The high diffusivity and solubility of Co in Si also introduce rough silicide-Si interface GOI degradation can be avoided by a careful control of thermal history

Co salicide formation is sensitive to Si surface conditions and contamination prior to Co deposition Unlike Ti, Co cannot reduce native oxides on Si, therefore it

is more sensitive than Ti to residual contaminants Several methods have been developed to reduce the sensitivity of Co silicide to surface conditions, taking advantage of the reactivity of Ti and its ability to reduce native oxides, by

incorporating Ti either as a capping layer or a Co-Ti alloy at the deposition stage 56, 58

Ti or TiN capping layer that is in-situ deposited immediately following Co deposition can also effectively control the ambient contamination 59, 60

NiSi:

Scaling of gate-to-gate spacing for higher packaging density and lower source/drain series resistances requires the corresponding scaling of the gate sidewall spacer thickness, which in turn requires a more aggressive scaling of junction depths

in order to achieve adequate short channel characteristics NiSi has become one of the most promising candidates replacing TiSi2 and CoSi2 for future applications in deep sub-quarter micrometer CMOS technologies 61

Silicidation of nickel can be accomplished rapidly and uniformly within a thermal window from 400°C to 700°C, making it suitable for low-temperature processes Secondly, unlike the nucleation-controlled formation mechanism of TiSi2, formation of nickel silicides is dominated by the diffusion of Ni atoms during thermal treatment Therefore the problematic linewidth-dependence phenomenon is intrinsically eliminated in NiSi Also the silicon consumption to form NiSi is only a half of that for CoSi2 Lower silicon consumption is desirable for the formation of shallow source and drain junctions required for deep sub-micron CMOS Due to the absence of reaction between Ni and the nitrogen annealing ambient, the thickness of the deposited Ni film can be determined more accurately, leading to a better control of the consumption of the Si The last but not the least, NiSi has lower Schottky Barrier for holes at the silicide/silicon contact as compared with TiSi2 and CoSi2 This offers low constant resistance merit on the p-type diffused layer, where the resistance has

conventionally been higher than on the n-type layer Although the resistivity of NiSi

is comparable to TiSi2 and CoSi2, the thermal stability of NiSi is worse than TiSi2 and CoSi2 since NiSi is not the final product of the Ni-Si solid reaction system, as shown

in the Ni-Si binary phase diagram (Fig 1-3) The essential problems encountered for

Ni silicide include agglomeration even at temperature as low as 600°C, transformation

to the high resistivity NiSi2 phase at 750°C, and anomalously large junction leakage current due to interface roughness 62, 63

Figure 1.3 Phase diagram of Ni-Si binary phase system (Cited from SGTE alloy

databases 2004)

By alloying with a small amount of Pt on blanket wafers, the thermal stability

of NiSi can be maintained up to 900°C, which is at least 100°C higher than that of

pure NiSi 64-67 NiSi has a MnP type orthorhombic structure of the space group

Pnma or a distorted NiAs hexagonal structure of the space group P6 /3 mmc

Addition of 5 at % Pt results in a change in the c/b ratio of the orthorhombic NiSi,

thus favors the formation of a hexagonal-structured film The coexistence of these two structures may be the reason for the enhanced thermal stability of the NiSi film containing Pt 68, 69 The incorporation of nitrogen (N2+) prior to Ni deposition can also widen the salicide processing temperature window by improving the silicide thermal stability 70, 71 N2+ implantation can retard NiSi agglomeration by means of changing the grain boundary energies, the interfacial energies and/or surface diffusion Phase transformation to the high resistivity NiSi2 phase was delayed, probably due to a change in the interfacial energy These optimized properties of N2+ implanted NiSi at high temperatures were integrated into PMOS, which showed higher drive current and lower junction leakage current as compared with devices without N2+ implant

1.3 Objective and Scope

As reviewed in the previous sections, silicides have been extensively studied for a few decades both experimentally and theoretically due to their importance for CMOS ULSI technology However, most of the studies have been carried out on the conventional bulk Si substrate The silicides for the advanced CMOS technology are still not fully studied due to the lack of effective characterization tools and their formation mechanisms are still far from deep understanding For example, as the thickness of silicide in ultra-shallow junction CMOS decreases down to a few atomic layers, electrical property and thermal stability will be different to thick silicide films due to quantum effects At the same time, new materials are being introduced into

advanced CMOS technologies, such as SiGe and strained-Si, the chemical composition and strain/stress state of the substrates will also influence the solid-state reaction process in silicidation Strain can significantly affect the atomic structure of

Si, therefore its band structure as well The impact will further propagate to silicide

on top through Si/silicide interface In SiGe system, the silicide thin film becomes ternary compounds, whose formation energy and thermal stability are affected by the concentration of Ge Therefore, the ternary compounds need to be studied thoroughly for successful implementation of SiGe in advanced IC circuits This work is carried out with aim to fill in these technical gaps

The thesis is devoted to studies on formation mechanisms and interface properties of transition-metal silicides through both experimental and theoretical approaches The shrinkage in lateral dimensions increases the demands to form ultra-thin silicide films to avoid excessive consumption of silicon, imposing substantial difficulties on silicidation processes In the first part of the thesis, the formation and stability of ultra-thin silicide films have been systematically studied Chapter 3 discusses stabilities of ultra-thin nickel silicide films in terms of electrical property, phase transition, and thermal stability Chapter 4 demonstrates a new technique, micro-Raman imaging, to be an effective technique for determining the morphology

of interfaces between metal or silicide thin films and silicon substrate, and evaluating the interface roughness

In the theoretical part, formation of silicides on different substrates has been simulated and the corresponding properties have been explored In Chapter 5, the reported interface structures are reproduced and a new interface structure is proposed

The new structure is stable from the energetics point of view and able to clarify the ambiguity in literatures The strain effects on the interfacial properties of different structures in MSi2/Si(001) heterojunction are discussed in details in Chapter 6, including atomic configuration, interface energy, electronic properties and Schottky barrier height And Chapter 7 presents bulk properties of germanosilicides with different compositions, which are the ternary compounds when silicide forms on Si1-

xGex substrates

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Chapter 2

Experimental and Computational Methodologies

Thin films play very important roles in CMOS fabrication starting from the very first pad oxide and nitride to the final passivation layer deposition A great number of techniques have been developed to form uniform thin films and to

characterize the quality of the films On the other hand, first-principles (ab initio)

calculation by solving the Schrödinger equation with only specifications of the present ions in any system has become one of the most outstanding methodologies of quantum mechanics The most important advantage of the first-principles calculation

is to predict new materials and explore material properties under extreme conditions that experimental techniques have difficulties to approach In this chapter, thin film growth and characterization methodologies and the basic concepts adopted in the first-principles calculation used in our studies will be introduced respectively

2.1 Thin Film Growth

An integrated circuit (IC) is largely composed of thin layers of either conducting or insulating films deposited over the semiconductor wafer surface Dielectric films, such as silicon dioxide and silicon nitride, are used as the isolation, mask, and passivation layers Polysilicon film can be used as conducting layer, semiconductor, or resistor by proper doping with different impurities And metal thin films basically act as local connection and interconnection from the basic constituent

devices, i.e transistors, up to the top layer of the whole circuit In brief, thin film technologies have been widely applied to the whole process of CMOS ICs The reliability of the ICs critically depends on the choice of materials in terms of adhesion, chemical stability, and thermal stability And the deposition methods and conditions affect the properties of the thin films substantially

Thin film growth methodologies can be generally categorized as Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) Chemical Vapor Deposition is a process that transforms gaseous molecules into a solid material in the form of thin film or powder on the surface of a substrate through chemical reactions

It is a material synthesis process whereby the constituents of the vapor phases react chemically near or on a substrate surface to form a solid product While the essence

of Physical Vapor Deposition is a process which involves vapor generation, transportation, and condensation to form a thin film by physical means rather than chemical reactions

2.1.1 RF Sputtering

The most common forms of PVD are evaporation, e-beam evaporation, plasma spray deposition, and sputtering Today, in ULSI fabrication, the most widely-used method to accomplish PVD of thin films is sputtering Sputtering is a process in which atoms on the surface of a target (cathode) are knocked off and condensed into a thin layer of the extracted material on a substrate (anode), through high-energy particle bombardment by either reactive or non-reactive ions 1, 2 The prevalence of sputtering is because of (1) the high deposition rate afforded by modern cathode and target design, (2) the capability of depositing and maintaining complex alloy

compositions, (3) the capability of depositing high-melting-temperature metals (like refractory metals), (4) the capability of maintaining well-controlled, uniform deposition on large (200mm and 300mm diameters) wafers, and (5) the capability of cleaning the substrate surface before depositing metal in multi-chamber systems

Figure 2.1 Schematic illustration of a RF sputtering chamber

Figure 2.1 is a schematic illustration of a RF (radio frequency) sputtering chamber The substrate is placed in a low-pressure chamber between a cathode and

an anode Both the electrodes are driven by a RF power source, which ionizes the gas (e.g., argon) and generates plasma in between A DC potential is used to drive the ions towards the surface of the target causing atoms to be knocked off and condensed

on the substrate surface The use of a RF generator is essential to maintain the

Matching Network

RF Generator

Sample Stage

& Heater

Target Magnet

Vacuum Chamber

discharge and to avoid charge build-up when sputtering insulating materials such as PZT The presence of a matching network between the RF generator and the target is necessary in order to optimize the power dissipation in the discharge Magnets are implemented to enhance the sputtering rate, by increasing the ionizing effect of electrons magnetically trapped in the vicinity of the target (magnetron sputtering) Using magnets can trap not only electrons, but also charged species at the target, so that the unwanted species cannot reach the substrate and the film quality is improved Sputtering has become a prevailing technique for depositing various metallic films on wafers because of its unparalleled characteristics mentioned before No other deposition technique can offer all these advantages Sputtering is and will continue to

be the technique of choice to deposit aluminum, aluminum alloys, platinum, gold, TiW, and transition metals (Pt, Ti, Co, Ni, etc.)

2.1.2 Rapid Thermal Annealing

Rapid thermal processing (RTP) has been widely applied in ULSI fabrication process, including epitaxial and selective growth of Si, generation of abrupt doping profiles, deposition of oxide or polycrystalline Si, junction formation and defect removal, oxidation, and metallization 3, 4 Rapid thermal annealing (RTA) has been found to be superior to conventional furnace techniques on metal silicide formation on source/drain and gate structures because the limited thermal stability of many silicide materials and their extreme sensitivity to trace impurities in the annealing ambient limit the application of furnace In contrast, RTA is a fast and single wafer process, minimizing the chance of particle contamination and deterioration of the properties of silicides

With RTP, a single wafer is heated in an extremely short period of time under atmospheric conditions or at low pressure under isothermal conditions Figure 2.2 shows a basic RTP system schematically The processing chamber is made of quartz, silicon carbide, stainless steel, or aluminum, and has quartz windows through which the optical radiation passes to illuminate the wafer inside The wafer holder is normally made of quartz and contacts the wafer in a minimum number of spots A thermocouple or IR pyrometer is placed in a control loop to monitor and control wafer temperature The RTP system is interfaced with a gas-handling system to adjust the annealing ambient and a computer to control the system operation

Figure 2.2 Schematic diagram of a rapid thermal processing system

The basic thermophysics in RTP follows Stefan-Boltzmann law, which

5

Lamp Cooling Water Quartz Window Wafer

Vacuum Thermocouple

Purge Gas

Pyrometer

( ) 4

where T is the absolute surface temperature, ε is the emissivity, and σ the

Stefan-Boltzmann radiation constant Since lamps and reflectors in the system are placed some distance from the wafer and an intervening quartz optical window is added in place, it is necessary to produce a high level of radiative heat flow, in another word, the temperature of the source should be very high The wavelength of the maximum intensity of the radiation source obeys Wien’s displacement law

3 max T 2.89783 10

where λmax is in units of meters Typical lamps in practical RTP systems have theoretical blackbody color temperature between 6000K (arc lamp) and 2900K (tungsten filament) 4 However, the color temperature of the heated wafer is much lower, at 900 to 1400K As a result, the absorption and emission spectra of the Si wafer never overlap in the optical-heating reactor, which creates temperature nonuniformity compared to conventional furnaces with the blackbody color temperature of 1450K Therefore the RTA parameters should be carefully tuned to minimize the deleterious effect

2.2 Thin Film Characterization Techniques

Thin film characterization is a wide field with numerous methodologies Here only the techniques used in this study will be introduced, including Raman Microscopy for phase identification, four-point probe (FFP) for sheet resistance measurement, Rutherford Back-scattering Spectrometry (RBS) for stoichiometric

identification, and atomic force microscopy (AFM) for surface morphology evaluation

2.2.1 Raman Microscopy

In 1928, Chandrasekhara Venkata Raman discovered that when monochromatic light passes through a transparent substance and the scattered light is examined spectroscopically, new weak lines of different frequencies appear in the spectrum in addition to the excitation frequency, which is called Raman effect 6, 7 It was soon realized that the newly discovered effect constitutes an excellent tool to study excitations of molecules and molecular structures, as well as single crystals 8 However, experiments were difficult and limited due to small scattering cross sections

In the mid-1960s, the advent of lasers, which provide strong, coherent monochromatic light in a wide range of wavelength, revolutionized Raman spectroscopy 9 Since then, Raman spectroscopy has been used as an important analytical technique for the identification of any material 10

Consider a light wave of frequency ν0 with electric field strength E , it can be

expressed as

0cos 2 0

where E is the amplitude and t the time Dipole moment P of a molecule induced 0

by the light can be given by

0cos 2 0

where α is the polarizability of the molecule If the molecule vibrates with a frequency νm , the nuclear displacement q can be written as

0cos 2 m

where q is the vibrational amplitude For a small amplitude of vibration, 0 α is

expanded as Taylor series of q ,

0

0

q q

Combining Eqs 2.4-2.6 and neglecting the terms higher than first order, the

dipole moment P has the expression as

(Stokes), shown in Figure 2.3 If (∂ ∂α q)0 is zero, the vibration is not Raman-active Namely, to be Raman-active, the rate of change of polarizability α with the vibration must be nonzero

Figure 2.3 Energy level diagram of Raman scattering

2.2.2 Four Point Probe

When the Ni/Si samples are heated up, Ni atoms diffuse into Si substrate to form different phases of Ni silicides at different temperatures Different phases have different resistance and thin film morphology, which influence directly the application

of the films Therefore, sheet resistance is the key parameter among all the properties

of silicide thin films for CMOS devices Consider a rectangular block of the material with length L , width W , and thickness t , the resistance of the sample is

= is defined as the sheet resistance of a layer of the material The unit of

the sheet resistance R is the same as the resistance R , which is Ohm To reflect the

Virtual Energy States

Vibrational Energy States

Rayleigh Scattering Stokes Scattering Anti-Stokes Scattering

IR Absorbance

characteristic of a layer rather than a bulk, the sheet resistance R is normally given as s

Ohm per square (Ohm/sq)

Figure 2.4 Schematic diagram of a four-point probe

The sheet resistance can be easily measured by four-point probe as illustrated

in Figure 2.4 Through two outer probes, a constant current is carried over the sample and the voltage drop is measured across the remaining two probes The sheet resistance therefore is given by

s

V R

I

α

where V is the measured DC voltage across the two voltage probes, I is the DC

current passing through the two current probes, and α is a geometry correction factor,

1, 4 - Current Probes

2, 3 - Voltage Probes

which accounts for the sample size, shape and probe spacing When the sample size

is over hundred-times of the probe spacing, the factor saturates to a constant of 4.53

2.2.3 Rutherford Back-Scattering Spectrometry

Two popular techniques, Rutherford Back-scattering Spectrometry (RBS) and atomic force microscopy (AFM), have been used to study the thermal stability of the ultra-thin silicide films in our experiments

Backscattering was discovered in 1911 during an experiment suggested by Lord Rutherford In this experiment, alpha particles were directed onto a thin foil where they were scattered by the atomic nuclei in the foil Today the analytical technique which bears his name as Rutherford Back-scattering is very similar to the first experiment As illustrated in Figure 2.5, an ion with mass M is accelerated with 1

energy E (typically on the order of several million electronvolts) and then irradiated 0

to a solid consisting of an atom with mass M The ion ricochets off the atoms at the 2

surface via elastic scattering The energy E of this ion is given by 1

backscattered from carbon is several orders of magnitude less than those backscattered from an element like gold This implies that RBS is a very sensitive tool for detecting high atomic number elements like tungsten The mass resolution, or the ability to distinguish between elements, is very low for high atomic number elements, while for light elements the resolution is quite good Also, RBS is often used to measure the stoichiometry of thin films, which is the ratio of one element to the other in the film

Figure 2.5 Principle of Rutherford Back-scattering Spectrometry

2.2.4 Atomic Force Microscopy

Atomic force microscopy (AFM), introduced about 20 years ago, has become

an essential imaging technique in virtually all branches of science and engineering due to its capability of conveying 3-D images with nanometer resolution in ambient

environment or even in liquid 12 In an AFM, a super sharp probe, mounted on a thin cantilever, runs a raster scan across the sample surface During the scan, the probe moves up and down relative to the sample to maintain a constant force or distance between the probe and the sample surface The vertical movement is recorded against

XY position and used to construct 3-D images

Figure 2.6 Schematic diagram of an atomic force microscope (cited from Vecco

application notes)

Usually, optical method is used to sense the force or distance, where a focusing laser beam is directed to the end of the cantilever and then reflected to a position sensitive detector (PSD), as shown in Figure 2.6 The output from the PSD, which is proportional to the bending of the cantilever and thus is a measure of the

force between the probe and the sample, is fed into a proportional-integral-differential (PID) controller, which moves the probe up or down accordingly to maintain a constant PSD output This method is usually referred as contact mode The other commonly used method is tapping mode, in which the cantilever is driven at or slightly below its resonant frequency by a piezo actuator When the probe approaches the sample surface, oscillating amplitude of the cantilever decreases due to the interaction between them The amplitude is measured by the root mean square (RMS)

of the PSD output through lock-in technique and based on which the controller moves the probe up or down to keep the distance constant

2.3 First-Principles Calculation

There is no doubt that formulation and development of quantum theory has led

to a revolution in various scientific realms – physics, chemistry and biology In quantum mechanics, any system can be interpreted by solving the Schrödinger equation of a complete many-electron-system Among quantum methodologies, first-principles calculation, also known as ab initio calculation, is unique to study material

properties based on fundamental physical laws and nonadjustable parameters only Furthermore, total-energy techniques have been successfully used to predict equilibrium lattice constants, bulk modulus, phonons, piezoelectric constants, and phase transition pressure and temperature with great accuracy, since most physical properties are related to total energies or to the difference between total energies For example, the equilibrium lattice constant of a crystal is the one that minimizes the total energy; and surfaces or defects of solids are the structures that minimize their corresponding total energies

In principle, prediction of geometric and electronic structures of a new material requires the calculation of quantum-mechanical total energy of the system and subsequently minimization of the total energy with respect to electronic and nuclear coordinates However, it is impossible to solve the time-independent Schrödinger equation without any assumption Born-Oppenheimer approximation is the very first step to treat nuclei adiabatic, which reduces the many-body problem to a solution of dynamics of the electrons in some frozen-in configurations of the nuclei Even with this simplification, the many-body problem remains formidable Further approximations are necessary to allow total-energy calculations to be performed accurately and efficiently Hatree-Fork approximation and density-functional theory (DFT) are the two most practicable simplifications to simulate the electron-electron interactions Density-functional theory provides a simple method to describe the exchange and correlation of electron gas and has become a popular state-of-the-art methodology In this work, we use density-functional theory with local density and generalized gradient approximation to study the structural and electronic properties of silicide bulk and the interface between silicide and silicon 13 Besides DFT, pseudopotential theory is introduced to model the electron-ion interactions, supercell scheme is used to model systems with aperiodic geometries, and iterative minimization techniques are adopted to relax electronic coordinates, respectively

2.3.1 Born-Oppenheimer and Hartree-Fork Approximations

In quantum mechanics, any system with N nuclei and n electrons can be described using the following time-independent Schrödinger equation

H r RK K Ψ r RK K = ΨE r RK K (2.11)

where H r Rˆ( )K, K is the Hamiltonian of the system, Ψ( )r RK, K is the wave function of the

dynamic variables of all particles, rK is the position vector of electrons, RK is the

position vector of nuclei, and E is the eigenstate energy of the system

Using a nonrelativistic approximation that takes into account only the pairwise interparticle interactions, the Hamiltonian in Eq (2.11) has the following coordinate representation 14, 15

where Mα is the nuclei mass, m is the electron mass, rKi is the position vector of the

i th electron, RKα is the position vector of the α -th nucleus, and zα is the atomic number By separating the motion of nuclei and electrons, the Hamiltonian H r Rˆ ( )K,K

can be represented by three portions,

2 2

α β α

ˆ

e n

i i

z e H

Because of the large difference between electrons and nuclei masses, the electrons respond instantaneously to the motion of the nuclei Thus the nuclei can be treated adiabatically, leading to a separation of electronic and nuclear coordinates in the many-body wave function, which is called the Born-Oppenheimer approximation

As a result, the Hˆn term can be dissociated from others in the Hamiltonian and negligible Based on this approximation, the Hamiltonian of the electronic subsystem

where the first term is the many-body kinetic energy operator, the second one describes the interactions of electrons with each other, and the final term represents the interaction of the electrons with the bare nuclei at fixed positions in the solid

However, even with the Born-Oppenheimer approximation, solving the Schrödinger equation still faces unaffordable mathematical difficulties The major difficulty lies in the electron-electron interaction, which introduces another many-body system rather than a sum of one-particle systems Electrons repel each other through Coulomb interaction between their charges The Coulomb energy of electrons can be reduced by keeping the electrons spatially separated by balancing against the kinetic energy of the electron wave function deformation

The wave functions of a many-electron system have to be anti-symmetric under the exchange of any two electrons since electrons are fermions The anti-symmetry of the wave functions produces a spatial separation between electrons with same spin, and thus reduces the Coulomb energy of the electronic system The