Application of titanium silicide as an interconnect in deep submicron integrated chip manufacturing

2.1 Titanium Silicide in Integrated Chip manufacturing 5 2.3 Area-Dependency of C49-to-C54 TiSi2 Phase Transformation 7 2.4 Pre-Amorphization Implant and Implant Through Metal 8... Titan

Founded 1905

APPLICATION OF TITANIUM SILICIDE AS AN INTERCONNECT IN DEEP SUBMICRON INTEGRATED

CHIP MANUFACTURING

TAN CHENG CHEH, DENNIS

(B.Eng (Hons.), NUS)

A THESIS SUBMITTED FOR THE DEGREE OF PH.D

DEPARTMENT OF MECHANICAL ENGINEERING

THE NATIONAL UNIVERSITY OF SINGAPORE

2004

I would like to express my heartfelt gratitude to a number of individuals who have assisted in making the project possible and successful Firstly, I would like to express my utmost appreciation to my supervisor Assoc Prof Lu Li, my mentors from Chartered Semiconductor Manufacturing Pte Ltd Dr Alex See and Dr Lap Chan for providing me with the opportunity for postgraduate study, but most crucially, for their invaluable supervision, advice and guidance throughout my candidature It is both my privilege and honor to work with them I would also like to acknowledge the National University of Singapore, Chartered Semiconductor Manufacturing Pte Ltd, and the National Science and Technology Board for providing me with the scholarship and financial assistance

Special thanks and appreciation to the staff and students of Materials Science Laboratory at the Department of Mechanical Engineering of the National University of Singapore for their technical expertise and enjoyable comradeship; namely, Mr Thomas Tan Bah Chee, Mdm Zhong Xiang Li, Mr Ng Hong Wei, Mr Maung Aye Thein , Mr Chua Beng Wah, Mr Gary Wong and Ms Sharon Nai

Special thanks and appreciation also to the staff from Chartered Semiconductor Manufacturing for their technical expertise; namely, Dr Ho Chaw Sing, Dr Randall Cha, Mr Lim Eng Wah, Mr Yap Kuan Pei, Mr Tee Kheng Chok, Dr Chen Shao Yin,

Mr Lai Chung Who, Dr Soo Choi Pheng, Ms Ko Lian Hoon and Mr Pang Chong Hau

for their unvarying support and encouragement Lastly, I would like to express my gratitude to my most beloved wife, Ms Teresa Soh, for her untiring patience and understanding

2.1 Titanium Silicide in Integrated Chip manufacturing 5

2.3 Area-Dependency of C49-to-C54 TiSi2 Phase Transformation 7

2.4 Pre-Amorphization Implant and Implant Through Metal 8

2.9 Differential Scanning Calorimeter 13

CHAPTER 4 EFFECT OF SILICON SUBSTRATE

AMORPHIZATION ON THE KINETICS

OF THE REACTION BETWEEN THE TITANIUM THIN FILM AND SILICON 36

4.3.3 Crystallite Size Evaluation from XRD Spectra 44 4.3.4 Activation Energy Calculations for C49-TiSi2 Formation 46 4.3.5 Activation Energy Calculations for C49-TiSi2 Precursor

CHAPTER 5 STUDY OF TITANIUM SILICIDE FORMATION

CHAPTER 7 FUTURE RECOMMENDATIONS 91

Titanium silicide (TiSi2) has been the choice interconnect for MOS Oxide-Semiconductor) devices due to its low electrical resistivity, good thermal stability and low silicon consumption Other than these advantages, most importantly titanium silicide can be integrated into a self-aligned silicide process (SAlicide) This

(Metal-is a process that does not require additional lithography while it selectively forms titanium silicide on areas where it is required: exposed silicon surfaces on the MOS device This can be easily achieved because titanium when in contact with silicon forms titanium silicide when heated

Although titanium silicide is thermally stable at high temperatures in a face centred orthorhombic structure (C54-TiSi2), there exists a meta-stable phase at lower temperatures with a base centred orthorhombic structure (C49-TiSi2) which first forms The final C54 phase is desired over the C49 phase titanium silicide not only because it

is thermally stable, but also more importantly it has a low electrical resistivity which is essential to the performance of the MOS device Demand for faster electronics led to higher circuit density in MOS devices and smaller feature sizes It was then discovered that the phase transformation of titanium silicide from C49 phase to C54 phase is area-dependent

The current challenge is to understand the obstacles inhibiting this phase change, to understand some of the common techniques used to overcome these obstacles while exploring new methods with existing manufacturing tools

The kinetics of the phase transformation and properties of the resulting titanium silicide from different processing techniques are hence studied in the present investigation Both new and improved processing techniques based on current

process, while newer novel techniques are explored and investigated

Figure 2-1 Schematic diagram of a typical Ti-salicide process 6

Figure 2-2 Schematic diagram of the differential scanning calorimeter 14 Figure 2-3 Schematic of a laser-Raman spectroscopy system 16

Figure 3-1(a) Sheet resistance of silicided undoped poly Si lines of varying line

Figure 3-1(b) Sheet resistance of silicided undoped poly Si lines of varying line

Figure 3-2(a) Micro-Raman spectra for TiSi2 on undoped 0.35 µm poly Si lines

line width 30 Figure 3-3(e) Gate-to-source/drain leakage current for specimens at 0.25 µm

Figure 4-1 The temperature profile taken during sample preparation for

Figure 4-2 DSC measurements of thin film PVD TiN/Ti deposited on

silicon (100) substrates with varying pre-amorphization implant dose: (A) without implant, (B) 1x1014 cm-2, (C) 5x1014 cm-2, (D) 8x1014 cm-2, (E) 1x1015 cm-2, (F) 45 nm amorphous silicon deposition, (G) 45 nm amorphous silicon deposition without

Figure 4-3 X-ray diffraction scans of specimen A after different thermal

anneal treatments at θ = 2° All except 850 °C were prepared

Figure 4-4 X-ray diffraction scans of specimen F after different thermal

anneal treatments at θ = 2° All except 850 °C were prepared

Figures 4-5 DSC curves measured from specimens with various degrees of Si

substrate amorphization: (a) specimen A: no Si implant, (b) specimen B: 1x1014 cm-2 Si implant, (c) specimen C:

5x1014 cm-2 Si implant, (d) specimen D: 8x1014 cm-2 Si implant, (e) specimen E: 1x1015 cm-2 Si implant & (f) specimen F: 45nm

different heating rates 48

Figure 4-7 Kissinger plots for C49-TiSi2 formation on different specimens:

(a) specimen A: no Si implant, (b) specimen B: 1x1014 cm-2 Si implant, (c) specimen C: 5x1014 cm-2 Si implant, (d) specimen D:

8x1014 cm-2 Si implant, (e) specimen E: 1x1015 cm-2 Si implant

& (f) specimen F: 45nm amorphous Si deposition 50 Figure 4-8 Kissinger plots for C49 TiSi2 pre-cursor phases formation on

different specimens: (a) specimen D: 8x1014 cm-2 Si implant, (b) specimen E: 1x1015 cm-2 Si implant, (c) specimen F: 45nm

Figure 4-9 θ-2θ x-ray diffraction scans of specimen A after different thermal

Figure 4-10 Ellingham plot of Ti-Si reactions Change in Gibbs free energy for

per mole of Si reactant Crystalline Si in a tetrahedral structure is used for the calculations Reaction r5 cannot take place since

Figure 4-11 Ellingham plot of Ti5Si4 formation from Ti reacting with Si of

different structures; r1: with as-implanted (77K) a-Si(1); r2: with relaxed (at 500 °C) a-Si(2); r3: Ti with crystalline (tetrahedral) Si

Excess Gibbs free energy normalized to per mole of Si reactant 61 Figure 4-12 Schematic diagram on the formation of pre-cursor phases for

specimens A and F Initial Gibbs free energy of specimens A

specimen F leading to a drop in Gibbs free energy from G1 to G2 66 Figure 5-1(a) Comparing sheet resistance after etchback for specimens with

different spike temperatures plus a fixed soak time at a lower

Figure 5-1(b) Comparing sheet resistance after RTA2 for specimens with

different spike temperatures plus a fixed soak time at a lower

Figure 5-2(a) Comparing sheet resistance after etchback for specimens with

a fixed spike temperature plus different soak times at a lower

Figure 5-2(b) Comparing sheet resistance after the RTA2 treatment for

specimens with a fixed spike temperature plus different soak

Figure 5-3(a) Comparing sheet resistance after etchback for specimens with

different spike temperatures without any soak time during RTA1 75 Figure 5-3(b) Comparing sheet resistance after the RTA2 treatment for

specimens with different spike temperatures without any soak

Figure 5-4(a) Gate-to-source/drain leakage current versus applied voltage on

line width equals 0.25 µm taken from specimen A after RTA2

Figure 5-4(b) Gate-to-source/drain leakage current versus applied voltage on

line width equals 0.25 µm taken from specimen D after RTA2

specimens at line width equals 0.25 µm 79 Figure 5-6 Cross section TEM picture of 0.25 µm serpentine comb structure

sample B (35 Ks-1 ramp-up with 30s soak) respectively 93 Figure 7-2 Schematic of a Silicon wafer deposited with titanium being

annealed with induced Eddy currents generated by induction coils 94

Table 2-1 Reported activation energies for C49-TiSi2 formation and the

Table 2-2 Summary of silicides suitable for salicide process 12

Table 4-1 Descriptions of the silicon substrate conditions prior to

45nm/15nm Ti/TiN stack deposition (except for specimen G)

For all pre-amorphization implants, Si species was used with an

Table 4-2 Comparison on peak broadening of C49 TiSi2 (131) XRD peak,

Table 4-3 Activation energy for C49-TiSi2 on Si substrates with different

Table 4-4 Activation energies for C49-TiSi2 pre-cursor phases on Si

substrates with different degrees of amorphization 53 Table 4-5 Parameters used in the free-energy calculations of Figure 4-11 60

Table 5-2 Sheet resistance after etchback for varying spike anneal

DSC Differential Scanning Calorimetry

Chapter 1 Introduction

1.1 Background

Since the invention of the integrated circuit (IC) by Kilby & Noyce in 1959, investigation of the materials and their integration into the manufacturing processes has been an integral part of the development for faster and more powerful integrated circuit chips This is because performance of the integrated circuit is very much affected by material selection and its successful integration into existing manufacturing processes Study on metal silicides forms a large part of this investigation because they can make low resistance and reliable contacts to shallow p-n junctions However many

of these metal silicides contain secondary and metastable phases, hence in-depth studies of their properties are needed before any metal silicide can successfully be integrated into the IC chip

Titanium silicide has been widely used as an interconnect in the Semiconductor (MOS) device for many technological generations due to its low resistivity and good thermal stability However, the application of titanium silicide in deep sub-micron electronic features is limited due to the incomplete formation of the face centred orthorhombic structured titanium silicide (C54-TiSi2) Instead a metastable, body centred orthorhombic structured titanium silicide (C49-TiSi2) is formed, which is undesirable as its electrical resistivity is higher than that of the C54 phase To overcome this problem, IC chip manufacturers either introduce new processing techniques or turn to other metal silicides altogether With new processing techniques, the use of titanium silicide as an interconnect can be extended to nano-sized structures

Metal-Oxide-1.2 Objectives

The objectives of this research project are to study the obstacles inhibiting the formation of the C54 phase on sub-micron electronic structures, to investigate the successes of current methods employed by IC manufacturers to overcome these obstacles, and finally to demonstrate new methods or techniques that enhance the formation of the C54 phase on sub-micron structures

1.3 Scope

The incomplete phase transformation of C49-to-C54 is studied on electronic device structures down to 0.25 micrometers manufactured using 0.35-micron technology The phases present on minute structures are characterized using micro-Raman spectroscopy The effect of different ramp-up rates on the formation of the titanium salicide is also studied

The process employed in 0.25-micron technology for the formation of C54 phase titanium silicide is studied To understand the kinetics of the phase transformation of titanium silicide, differential scanning calorimetry and X-ray diffraction are used Based on these observations, a hypothesis will be proposed to explain the success of this technique

The use of a spike anneal on the formation of titanium silicide on electronic structures down to 0.275 micrometers is studied The integration of this technique into the existing manufacturing process of integrated chips was investigated

Last but not least, the feasibility of other new novel techniques will be investigated

1.4 Organization of Thesis

The remaining parts of the thesis are organized as follows:

Chapter Two provides background information on titanium silicide and some

of the experimental techniques used in this research including the formation of titanium silicide on designated areas of the chip, comparison with other metal silicides and current techniques to overcome the area-dependency of the C49-to-C54 titanium silicide phase transformation

Chapter Three presents a study of effects of ramp-up rates on the salicide process It describes the experimental procedures carried out The results presented include electrical resistance, gate-to-source/drain leakage current, and micro-Raman spectroscopy spectra A discussion of the results is presented before conclusions on the effects of ramp-up rates on the salicide process

Chapter Four presents the effects of silicon substrate amorphization on the kinetics of the reaction between titanium thin film and silicon The results presented include thermal graphs obtained from a differential scanning calorimeter and X-ray diffraction A detailed discussion, including the determination of activation energies, is presented An explanation is also offered on the success of current manufacturing techniques that overcomes the area-dependency of the C49-to-C54 titanium silicide phase transformation, followed by conclusions

Chapter Five presents a study of titanium silicide formation using spike anneals It describes the experimental procedures carried out followed by results

obtained, these include electrical resistance and gate-to-source/drain leakage current Discussion of the successes of employing a spike anneal is presented before ending with conclusions

Chapter Six concludes the major findings from this research work

Finally, Chapter Seven suggests three recommendations for feasible future studies

Chapter 2 Literature Survey

2.1 Titanium Silicide in Integrated Chip manufacturing

The usefulness of a metal silicide for an integrated chip depends, not only on the desired low resistivity, but also on the ease with which the silicide can be formed Other criteria also include the amount of Si substrate consumed and the main diffusing species during formation Titanium silicide is widely used as an interconnect to the gate and source/drain regions due to its low resistivity and good thermal stability [1] Titanium silicide first forms as the metastable C49 phase, a body centred orthorhombic structured crystal (a = 3.62 Å, b = 13.76 Å, c = 3.605 Å), which is of a high resistivity

of 60 - 90 µΩcm, in the temperature range of 500 to 650 °C At the higher temperature range of 700 to 850 °C, titanium silicide undergoes a phase transformation from C49 phase (base-centered orthorhombic) to the desired C54 phase, a face-centered orthorhombic structured crystal with a = 8.24 Å, b = 4.78 Å, c = 8.54 Å, which has a lower resistivity of 12-20 µΩcm [2]

2.2 Titanium Salicide Process

Titanium salicide or the self-aligned silicide process manufactures a film of titanium silicide selectively on the gate and source/drain regions of the MOSFET Since only areas where the silicon surface is exposed can react with the titanium film, the process is achieved without the use of an additional masking step, thus, the phrase: Self-Aligned Figure 2-1 shows the 4 basic steps in the titanium salicide process

step 3: RTA1

C54-TiSi2

step 4: Ti etchback + RTA2

Figure 2-1 Schematic diagram of a typical Ti-Salicide Process

Step 1, pre-titanium clean, is a preparation step that removes any native oxide (SiO2) on the exposed Si surface The chemical used is dilute HF solution Step 2 is titanium deposition, which is usually done using Physical Vapour Deposition A time-lag between steps 1 and 2 of not more than 8 hours prevents any excessive SiO2 from reforming before titanium is deposited In order to avoid contamination of the titanium film, a layer of titanium nitride can sometimes be deposited onto the titanium film as seen in Figure 2-1 Step 3 is the first Rapid Thermal Anneal (RTA) step, known commonly as RTA1 The temperatures for RTA1 are usually between 600 and 750 °C The process window for RTA1 is determined such that the temperature should be high enough to allow titanium to completely react with the silicon surface to form C49-

TiSi2, but be low enough to prevent either a reaction between titanium and spacers, or excessive diffusion of silicon over spacers After RTA1, SC1, H2O:H2O2:NH4OH (6:1:1), used to remove the titanium nitride and any unreacted titanium Finally, a second RTA step, called RTA2 is applied at a higher temperature range from 800°C to 850°C to convert the C49-TiSi2 to C54-TiSi2 This conversion is necessary as C54-TiSi2 has a resistivity of 12-20 µΩcm, which is much lower than the resistivity of C49-TiSi2 at 60-90 µΩcm The process window for RTA2 is set such that the temperature should be high enough to achieve the phase conversion, but be low enough to prevent agglomeration of the C54-TiSi2 film

2.3 Area-Dependency of C49-to-C54 TiSi 2 Phase Transformation

The difficulty of using titanium silicide as a metal silicide begins to show at deep sub-micron device features The sheet resistance of titanium silicide after RTA2 increases as the linewidth decreases below 0.35 µm, and at 0.25 µm the sheet resistance was close to that of C49-TiSi2 Studies revealed that the increase in sheet resistance was due to the incomplete C49-to-C54 TiSi2 phase transformation A high percentage of C49-TiSi2 was present even after RTA2 [28]

Ma and Allen [3] discovered that C54-TiSi2 nucleates along the grain boundaries of a thicker C49-TiSi2 film (550 Å and 1000 Å of Ti deposited) and it nucleates at the grain edges or triple-grain boundary junctions of the thin C49-TiSi2film (250 Å of Ti deposited) With each technology node, the feature size is scaled downwards proportionally With a smaller line width, the junction depth decreases as with silicide thickness Therefore for a deep sub-micrometer line width, the C49-to-C54 TiSi2 phase transformation takes place on the triple grain boundary junctions

Previous studies showed that grain size of thin film C49-TiSi2 is in the micrometer range [4] Hence, with smaller line widths the availability of C49-TiSi2triple grain boundary junctions reduces Without these triple-grain boundary junctions, C54-TiSi2 cannot nucleate without risking agglomeration at higher temperatures

sub-To overcome this limitation of TiSi2, methods were devised to extend the use

of TiSi2 into the deep sub-micrometer regime Among the methods, Amorphization Implant (PAI) and Implant though Metal (ITM) have been widely used

Pre-in Pre-integrated chip manufacturPre-ing

2.4 Pre-Amorphization Implant and Implant Through Metal

In order to reduce the area-dependency of the C49-to-C54 TiSi2 phase transformation, an extra procedure is included into the typical Ti salicide process Before step 1 of Figure 2-1, the wafer is subjected to an ion-implantation, typically using silicon as an implant species The aim of the ion-implantation is to amorphize the silicon substrate It has been demonstrated that PAI reduces the area-dependency of the C49-to-C54 TiSi2 phase transformation and the sheet resistance of TiSi2 after RTA2 for smaller line widths [5-8]

Although it reduces the area-dependency of the C49-to-C54 TiSi2 phase transformation, amorphizing the silicon substrate can degrade the electrical properties

of the IC chips The degradation is believed to be attributed to the implantation and silicidation-induced generation of vacancies and interstitials, resulting in the de-activation and subsequent re-distribution of dopants around the transistor lightly doped drain (LDD) and source/drain regions [9-11]

Similar to that of PAI, Implant Through Metal (ITM) amorphizes the Si substrate through ion-implantation, but only after the metal has been deposited: thus Implant Through Metal It has also been shown that ITM reduces the area-dependency

of the C49-to-C54 TiSi2 phase transformation [5-8] However, like PAI, it also introduces lattice defects into the substrate and thus degrades the electrical device

2.5 Kinetics of Thin Film TiSi 2 Formation

Various researchers have reported the activation energy for the thin film TiSi2 formation to be 1.26~3.1 eV [12-17] Reported findings mostly used the low resistivity of C49-TiSi2 as a means to indicate the amount of C49-TiSi2 present Murarka and Fraser [12] used the change in electrical resistivity to track the amount of C49-TiSi2 formed from 1000 Å Ti deposited on to 4300 Å poly Si and reported the activation energy to be 1.8 eV Using backscattering spectroscopy, Hung and co-workers[13] reported 1.8 eV from 900 Å Ti deposited on 2500 Å of amorphous Si Thompson and co-workers [14] employed electrical resistivity, they reported 1.47 eV for 800 Å of co-evaporated TiSi2 on a Si substrate and 1.26 eV on a SiO2 substrate

C49-Clevenger and co-workers used the maximum rate of change of resistivity (dR/dt = 0)

as an indication for maximum reaction rate, and reported 2.6 eV for 575 Å of Ti deposited on poly Si [15] Ma and co-workers [16] employed differential scanning calorimetry to track 10 multilayers of Ti/a-Si (19.2:10.8 nm) films deposited onto photoresist-coated glass slides, and reported 3.1 eV More recently, Stark and co-workers [17] used backscattering spectroscopy measurements on 80 nm of Ti sputtered onto Si wafers annealed to different temperatures and obtained an activation energy of 2.3 eV Table 2-1 summarises the results for C49-TiSi2

Table 2-1 Reported activation energies for C49-TiSi 2 formation and the methodology adopted

2.6 Comparison with other metal silicides

Since the scalability of TiSi2 into the deep sub-micrometer regime is in question, two other metal silicides have since emerged as possible substitutes to TiSi2, namely: CoSi2 and NiSi

CoSi2 is currently a popular choice for 0.25 µm and sub-0.25 µm technology generations However, there are problems inherent to Co-silicidation Unlike Ti, Co cannot reduce SiO2 therefore it is sensitive to cleaning and ambient contamination It has been demonstrated that these drawbacks can be solved using a Ti-capped Co-silicidation process The Co/Ti cap process has an excellent scalability and a large process window in terms of silicidation temperature and ambient However, the major problem with CoSi2 is its relatively higher Si consumption With continuously decreasing junction depth, CoSi2 is being scaled down to lower the silicon consumption at the expense of higher sheet resistance

NiSi is potentially another suitable silicide due to its low resistivity, lower consumption of Si, and ability to maintain low resistivity even for line widths down to 0.1 µm or less [18] However, NiSi has a relatively low thermal stability and problems with transformation of NiSi into the highly resistivity NiSi2, and agglomeration of NiSi

at elevated process temperatures In addition to the thermal stability of NiSi, another concern for NiSi is the effect of the silicidation process on the electrical properties of the silicon substrate as well as device performance, due to the formation of any silicide spikes and silicidation-induced defects, which mainly arise since the diffusivity and

solubility of Ni in Si are relatively high at the processing temperatures Ni has been reported to induce defects and precipitates in Si

Table 2-2 gives a summary of the silicides discussed

Table 2-2 Summary of silicides suitable for salicide process

Silicide Resistivity

[µΩcm]

Si consumption for 1 unit thickness of silicide

Limitations

approx 0.35 µm, incomplete C49-to- C54 TiSi2 phase transformation

cleaning and ambient contamination

Transformation to high resistivity NiSi2 Agglomeration of NiSi [20,21]

2.7 Rapid Thermal Annealing

Rapid Thermal Annealing (RTA) or Processing (RTP) differs from the conventional furnace treatment in many ways In a conventional furnace, wafers are treated in batches of up to 200 wafers depending on the size of the furnace Although the whole process is somewhat longer for the furnace, its throughput is much faster due to batch processing In an RTA system, wafers are processed individually at a reduced thermal budget By increasing the temperature of the wafer at a very fast rate through powerful lamps, the RTA can reduce the amount of thermal budget usually associated with furnace treatments This is essential to integrated chip manufacturing since the extra thermal budget will lead to undesired dopant diffusion Another advantage in RTA is its ambient control Since it is a single wafer processing system,

the RTA chamber is much smaller compared to a conventional furnace, which makes it possible for the RTA chamber to have a tighter ambient control This is important for Ti-silicidation because slight amounts of O2 can cause oxidation at the Ti-Si interface and cause an increase in the resistivity

2.8 Thermal Budget

Quantitative analysis of RTA usually employs the concept of “thermal budget,” which is commonly defined as the area under the time-temperature curve characterizing the processing sequence Efforts focus on minimizing the thermal budget in an attempt to reduce unwanted solid-phase diffusion or interface degradation

The idea of the thermal budget appears to have originated in conjunction with modeling thermal diffusion of dopants in p-n junction fabrication Budget then referred

to the inverse functional relationship between the isothermal processing temperature and the time required to establish a particular junction depth More precisely, in non-isothermal operation, thermal budget denotes the area under a time-temperature curve [22]

2.9 Differential Scanning Calorimeter

A Differential Scanning Calorimeter (DSC) is an instrument that measures the amount of heat released or absorbed during a reaction It achieves this by having two pans, one with the specimen leaving the other empty as reference, showing the heat up

at a rate predetermined The amount of energy which has to be supplied to or withdrawn from the sample to maintain zero temperature differential between the specimen and the reference is then measured and recorded during the temperature ramp up The specimen and reference are placed in identical environments (usually an inert gas like Argon or Nitrogen) on individual bases which contain a thermocouple and a heater The temperatures of the two thermocouples are compared periodically, and the electrical power supplied to each heater adjusted so as to minimise the difference between them while maintaining the predetermined temperature ramp up Figure 2-2 shows a schematic representation of a differential scanning calorimeter

Figure 2-2 Schematic diagram of a differential scanning calorimeter

The difference in power supplied, which is also the rate of energy absorption

by the sample, is then proportional to the specific heat of the sample since the specific heat at any temperature determines the amount of thermal energy necessary to change the sample temperature by a given amount Any transition accompanied by a change in specific heat produces a discontinuity in the power signal, and exothermic or

endothermic enthalpy changes give peaks whose areas are proportional to the total

enthalpy change

2.10 Kissinger’s Analysis

Kissinger proposed a method to calculate the kinetic constants for a reaction

generally described by equation 2-1 [23]:

RT

E n

a e x Z dt

−

where dx/dt is the rate of a reaction, x is the fraction reacted, n is the empirical order of

the reaction, and T is the temperature in Kelvin In a thermal analysis, the peak temperature occurs when the rate of reaction is at a maximum, i.e d(dx/dt)/dt is zero,

as stated by equation 2-2:

0)

a e x Z dt

d dt

dx dt

d

(2-2)

If the temperature rises at a constant rate φ, then dT/dt is φ, and equation 2-2

can be reduced to equation 2-3:

)/()

/

m a

m Z E kT

where φ is the heating rate, k is Boltzmann’s constant, Ea is the activation free energy

barrier, Z is the pre-exponential constant, and T m is the peak temperature in Kelvin

where the reaction rate is at its maximum By measuring the peak temperatures for a

number of heating rates, φ, a Kissinger plot of ln(φ/T m 2 ) against 1/T m can then be used

to find E a

2.11 Raman Spectroscopy

Laser

ScanningmonochrometerCRT

D

PA

L2

M2

M1S

Figure 2-3 Schematic of a laser-Raman spectroscopy system

Figure 2-3 shows a schematic diagram of a typical set up for a Raman spectroscopy system for optically transparent samples [24]

The appearance of additional lines in the spectrum of monochromatic light that has been scattered by a transparent material medium is termed the Raman effect and was discovered by C V Raman in 1928 The energy and thus the frequency or

wavelength of the scattered light changes as the light either imparts rotational or vibrational energy to the scattering molecules or takes energy away Quantum mechanics requires that only certain well-defined frequencies and atomic displacements are allowed These are known as the normal modes of vibration of the molecule A linear molecule with N atoms has 3N - 5 normal modes, and a non-linear molecule has 3N - 6 normal modes of vibration There are several types of motion that contribute to the normal modes Some examples are:

• stretching motion between two bonded atoms;

• bending motion between three atoms connected by two bonds;

• out-of-plane deformation modes that change an otherwise planar structure into

a non-planar one

The Raman effect states that the line spectrum of the scattered light will have one prominent line corresponding to the original wavelength of the incident radiation, plus additional lines to each side of it corresponding to the shorter or longer wavelengths of the altered portion of the light This Raman spectrum is characteristic

of the transmitting substance Raman spectrometry is a useful technique in physical and chemical research, particularly for the characterization of materials

2.12 X-Ray Diffraction

Diffraction occurs when wave motion encounters a set of regularly spaced scattering objects provided that the wavelength of the wave motion is of the same order of magnitude as the repeat distance between the scattering centers The German

physicist von Laue reasoned that if crystals were composed of regularly spaced atoms, which might act as scattering centers for x-rays, and if x-rays were electromagnetic waves with a wavelength about equal to the interatomic distance in crystals, then it should be possible to diffract x-rays by means of crystals A difference in the path length of various rays arises when a crystal diffracts x-rays

A diffracted beam may be defined as a beam composed of a large number of scattered rays mutually reinforcing one another Diffraction is, therefore, essentially a scattering phenomenon Figure 2-4 shows a section of a crystal, its atoms arranged on

a set of parallel planes A, B, C spaced distance d apart A beam of perfectly parallel,

perfectly monochromatic x-rays of wavelength λ incident at an angle θ, called the Bragg angle, where θ is measured between the incident beam and the crystal planes

under consideration For incident rays 1 and 2, scattered by atoms K and L, the path difference for rays 1K1’ and 2L2’ is:

θ

d LN

Scattered rays 1’ and 2’ will be completely in phase if this path difference is equal to a whole number n of wavelengths, or if:

When the size of the individual crystals is less than about 0.1 µm, broadening

of the Debye rings results The extend of the broadening is given by Scherrer’s equation below [25]:

θ

λβ

cos

9.0

t

where β = broadening of a diffraction line measured at half its maximum intensity (radians) and t = diameter of an individual crystal All diffraction lines have a measurable breadth, even when the crystal size exceeds 0.1 µm, due to such causes as divergence of the incident beam and size of the sample (in Debye cameras) and width

of the x-ray source (in diffractometers) The breath β in equation 2-6 refers, however

to the extra breadth, or broadening, due to the crystal-size effects alone In other words, β is essentially zero when the particle size exceeds about 0.1 µm

The main problem in determining crystal size from line breadths is to determine β from the measured breadth βm of the diffraction line Of the many

methods proposed, Warren’s is the simplest The unknown is mixed with a standard which has a particle size greater than 0.1 µm, and which produces a diffraction line near the line from the unknown which is to be used in the determination A diffraction pattern is then made of the mixture in either a Debye camera or, preferably, a diffractometer This pattern will contain sharp lines from the standard and broad lines from the unknown Let βs be the measured breadth, at half-maximum intensity, of the line from the standard Then β is given, not simply by the difference between βm and

βs, but by the equation:

2 2 2

s

m ββ

The maximum size measurable by line broadening was formerly placed at 0.1

µm, chiefly as a result of the use of camera techniques With a diffractometer however, the upper limit has been pushed to almost 0.2 µm Attempts have been made to apply Scherrer’s equation to the broadened diffraction lines from very fine-grained metal specimens and so determine the size of the individual grains Such determinations are never very reliable, however, because the individual grains of such a material are often non-uniformly strained, and strain can also add to the broadening of the diffraction lines

Chapter 3 Effects of Ramp Up Rates on the Formation of Titanium Silicide

3.1 Introduction

An increase in sheet resistance of TiSi2 with decreasing line width is attributed

to an incomplete transformation from the high resistance C49-TiSi2 phase to the desired low resistance C54-TiSi2 phase In this chapter, the effects of the ramp up rate

of RTA1 in the salicide process are investigated Electrical resistance measurements and micro-Raman spectroscopy characterization were carried out to investigate the C49-to-C54 phase transformation on poly lines with different line widths Samples were annealed with 3 different ramp-up rates in RTA1 From micro-Raman spectra, it was observed that the increased ramp-up rate during RTA1 resulted in more C54-TiSi2formed on poly Si lines with a smaller line width during the second rapid thermal anneal (RTA2) It was also shown that higher ramp-up rates resulted in lower sheet resistance for deep sub-micrometer poly lines [26]

3.2 Experimental Procedures

Experiments were performed on 8” (200mm) wafers from 0.35 µm CMOS logic technology A 450/150 Å Ti/TiN stack was first deposited using PVD on patterned poly Si lines with SiO2 spacers These undoped poly Si lines are on field SiO2 The deposition was carried out within 4 hours after a brief dip in a diluted HF solution that removed any native SiO2 Ti silicide was then formed in two RTA steps Four RTA1 schemes (with different ramp rates and soak times) were then applied on

6 separate wafers Table 3-1 shows the details of the 4 RTA1 schemes All RTA treatments were done in a N2 gas ambient

Table 3-1: Details of RTA1

Specimen A 2 wafers 35 Ks-1 ramp-up to 720 °C, 30 s soak at 720 °C

Specimen B 1 wafer 85 Ks-1 ramp-up to 720 °C, 30 s soak at 720 °C

Specimen C 2 wafers 150 Ks-1 ramp-up to 720 °C, 30 s soak at 720 °C

Specimen D 1 wafer 150 Ks-1 ramp-up to 720 °C, 20 s soak at 720 °C

After RTA1, selective etching of unreacted Ti and TiN (etchback) was carried out using SC1 (NH 4 OH:H 2 O 2 :H 2 O at 1:1:10) The sheet resistance of silicided poly-Si lines of varying line width was measured on 2 wafers, one each from specimen A and C This was done by measuring the Kelvin structure of various line widths In RTA2, a 30 s soak at 850 °C, 35 Ks-1 ramp-up rate was then performed on the remaining 4 wafers The sheet resistance of silicided poly-Si lines was also extracted from the same Kelvin structures These Kelvin structures had line widths ranging from 0.275 to 1 µm Large silicided pads connected to the Kelvin structures made it possible to measure the silicide sheet resistance without having to process metal lines on the wafers For each wafer specimen, all sheet resistance results were collected from 17 dies distributed on the wafer Micro-Raman spectroscopy studies were then performed on Serpentine Comb structures of silicided poly-Si with various line widths using a Raman system fitted with single grating spectorgraph The 782-nm near infrared excitation laser has a focus spot diameter of about 1-2 µm The Serpentine Comb structures were used as they provided sufficient TiSi 2 for the Raman scattering experiments On the other hand, the Kelvin structures contained only a single silicided poly Si line, which is insufficient to provide enough Raman scattering signals from the TiSi 2

Finally, the gate to source/drain leakage current was extracted on the Serpentine Comb structures to check for bridging across the spacers as a result of

increased ramp-up rate during RTA1 The leakage current was measured while sweeping the applied voltage from –5V to +5V between the poly Si line and source/drain

to 720 °C, 30 s soak at 720 °C) shows a delay in the increase of sheet resistance as the

line width decreases The sheet resistances of specimen A, B and D start to increase when poly lines are narrower than 0.33 µm whereas the sheet resistance of specimen C starts to increase only when poly lines are narrower than 0.30 µm Even so, the sheet resistance of specimen C remains lower than that of specimens A, B and D

A: RTA1 35C/s ramp to 720C + 30s soak at 720C

C: RTA1 150 amp to 720C + 30s soak at 720C

C This suggests that the TiSi2 formed on specimen A is thicker than that on specimen

C

It is noted from Figure 3-1(a) that, although the ramp rate for specimen D is the same as that for specimen C, the poly sheet resistance of specimen D behaves more like that of specimen A which received a much slower ramp rate during RTA1 This is