Application of PEEC modeling for the development of a novel multi gigahertz test interface with fine pitch wafer level package

APPLICATION OF PEEC MODELING FOR THE DEVELOPMENT OF A NOVEL MULTI-GIGAHERTZ TEST INTERFACE WITH FINE PITCH WAFER LEVEL PACKAGE JAYASANKER JAYABALAN DEPARTMENT OF ELECTRICAL AND COMPUT

APPLICATION OF PEEC MODELING FOR THE

DEVELOPMENT OF A NOVEL MULTI-GIGAHERTZ TEST

INTERFACE WITH FINE PITCH WAFER LEVEL PACKAGE

JAYASANKER JAYABALAN

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

APPLICATION OF PEEC MODELING FOR THE

DEVELOPMENT OF A NOVEL MULTI-GIGAHERTZ TEST

INTERFACE WITH FINE PITCH WAFER LEVEL PACKAGE

BY

JAYASANKER JAYABALAN

M.Sc.(Engg), National University of Singapore

A THESIS SUBMITTED FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

ACKNOWLEDGMENTS

I like to thank my research supervisors, Professor Leong Mook Seng, Dr Ooi Ban Leong and Dr Mahadevan Krishna Iyer for the invaluable advice and guidance throughout the course of this research Their emphasis on independent and multi-disciplinary research has given me opportunities to explore many aspects of electromagnetic modeling, measurements and electronic packaging

The National University of Singapore and Institute of Microelectronics provided many facilities without which this work would not have materialized In particular, the readily available literature and computing resources in NUS and the assembly, measurement and analysis equipment facilities in IME have greatly helped

me in completing this work successfully I am also honored to be awarded the Wafer Level Packaging Program research fellowship provided by Singapore’s Agency for Science, Technology and Research during my candidature

Nano-My appreciation to Dr Mihai of IME for his help on microwave modeling and measurements; Dr Albert Ruehli of IBM for clarifications on PEEC modeling via email; Prof M S Nakhla of Carleton University for clarifications on circuit solvers for delay differential equations when he visited the Institute for Mathematical Sciences; Prof Andrew Tay and my NUS laboratory colleagues Dr Xu, Ms Guo Lin,

Mr Wu Bin, Mr Song and Mr Sing for the numerous discussions and help which have contributed to this work; my IME colleagues Mr Sivakumar and Mr Ranjan for help in test sample preparations

I am grateful to my wife Padmalatha, my parents and in-laws for their kind

TABLE OF CONTENTS

ACKNOWLEDGMENT……… i

TABLE OF CONTENTS……….…ii

ABSTRACT………vii

LIST OF FIGURES………ix

LIST OF TABLES………xiv

LIST OF SYMBOLS……….….……xv

CHAPTER 1……… 1

INTRODUCTION………1

1.1 Background and Motivation.……….….……….1

1.2 Partial Element Equivalent Circuit Modeling….……… ……… … 3

1.3 Solving Delay Differential Equation Systems……….… ……… … 4

1.3.1 DDE Example with Two Nodes ……… ……… …… 4

1.3.2 Time Stepping Algorithm for Solving Delay Differential Equation Systems …… ……6

1.4 Scattering Parameter Analysis of Circuits ……… ……… … 8

1.5 Scope and Organization of This Thesis…… ……… ……… … 10

1.6 Original Contributions……… ……… … 13

1.6.1 Journals.……… ……… ……… …… 14

1.6.2 Journal Submissions under Review……… ……… …… 15

1.6.3 Conferences ………… ……… ……… …… 15

1.6.4 Patents ……… ……… ……… …… 16

CHAPTER 2……… ………….17 MODELING OF HOMOGENEOUS LOSSLESS MEDIA BY PEEC

2.2 Deriving the PEEC Model in Homogeneous Media… …….… ……… ……… 18

2.3 Baker-Campbell-Hausdorff-Dynkin Series Expression… ……… 22

2.4 Scaling the System Matrix……… ……… 24

2.5 Numerical Example……… ……… 27

2.6 Results and Discussions ………… … ………… ……… 29

CHAPTER 3……… ………….38

PEEC AND LUMPED CIRCUIT MODELING OF HOMOGENEOUS LOSSY MEDIA ……….….……….38

3.1 Introduction……… ……….38

3.2 PEEC Model Extension to Lossy Substrates……… 38

3.3 Lumped Circuit Model in Lossy Substrates……….……… 40

3.3.1 Equivalent Circuit Description……… ……… …… 41

3.3.2 Modeling Methodology … ……… ……… …… 42

3.3.3 Minimizing the Residual Trace Function ……… ……… …… 44

3.4 Results and Discussions……… ………….……… 45

CHAPTER 4……… ………….49

PEEC MODELING OF MULTICONDUCTOR SYSTEM WITH DIELECTRIC MESH……… … ……….49

4.1 Introduction……… ……….49

4.2 Probing Considerations for WLP Test: Relevance of Dielectric Mesh……… 50

4.3 PEEC Modeling for Elastomer Dielectric Mesh….……… 53

4.4 Numerical Example and Discussions… ………… ……… 57

CHAPTER 5……… ………….65

5.2.1 Example A: Inductive Open Wire Loop……….…… ……… …… 72

5.2.2 Example B: Insulated Capacitive Spheres……… 73

5.3 Two Layer System: Microstrip Capacitance……… 75

5.4 Extension to PEEC Model……… ……… 77

5.5 Multilayer PEEC Example: Coupled Microstrip Line Filter……… 83

5.5.1 Three Layer Geometry ……… ……… …… 83

5.2.2 Four Layer Geometry.…… ……… 86

5.6 Discussion……… ……… ……… ……… 88

CHAPTER 6……… 89

DEVELOPMENT OF A NOVEL MULTIGIGAHERTZ TEST INTERFACE FOR FINE PITCH WAFER LEVEL PACKAGES : AN APPLCATION OF PEEC MODELING……… ….89

6.1 Introduction……… … ……… 89

6.1.1 Significance of Wafer Level Packaging……… ……… ….… 89

6.1.2 WLP Test Concept.…… ……… 90

6.1.3 Limitations of Conventional Test Approaches for WLPs……….……… …… 91

6.1.4 Test Solution……….……… 92

6.2 Structure of Prototype and Fabrication……….……….… 93

6.2.1 Test Fixture……….……… ……… …… 93

6.2.2 Device under Test ….… ……….… 99

6.3 Model of Prototype Components……….… ……….……….101

6.3.1 WLP…… ……….……… ……… …….101

6.3.2 WLP Off-chip Interconnect……… ……….101

6.3.3 Elastomer Mesh… …….……… ……… …….103

6.3.4 Multilayer Substrate ….….……… ……….105

6.3.5 System Level Model… ……… ……… …….108

6.5.2 High Speed Signal Generation and Detection for Functional Test of Fine Pitch

and Large Pin Count WLP Devices……… 120

6.5.3 Eye Diagrams……… ……….… 122

6.6 Discussions……….…….…… ……….124

CHAPTER 7……….126

CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORKS….……… 126

7.1 Concluding Remarks……… ……….126

7.2 Suggestions for Future Works… ……… … 129

7.2.1 Modeling Intermediate and Far Field Effects ……… … 130

7.2.2 Modeling Nano-Scale Size Effects……… … 131

REFERENCES……… ….133

APPENDIX A……… 144

DELAY DIFFERENTIAL EQUATION CODING EXAMPLE FOR PEEC WITH 2 NODES…… 144

APPENDIX B ……… ……….149

COMPUTATION OF GREEN’S FUNCTION INTEGRALS…… …… … 149

B.1 Numerical Evaluation……… …… ……….149

B.2 Analytical Evaluation……… ……….152

B.2.1 Approximate Forms for Removing Singularity……… ……… … 152

APPENDIX C…… ……… ……….155

THE METHOD OF IMAGES IN MULTILAYERS……… … … 155

C.1 On the Use of Image Method in Representing Multilayers……….155

C.2 Multilayer Problem as a Multi-body Problem……… … ……….156

C.3 Silvester’s Image Model of Spatial Green’s Function……….158

APPENDIX D ……… ……….164

MODEL CONSIDERATIONS AS CIRCUIT SIZES APPROACH NANO-SCALE……… ……… ……… … …164

D.1 Introduction……… …… ……….164

D.2 Modeling……… …… ……….166

D.3 Results and Discussion……… ……… …… ……….169

APPENDIX E……… ……….172

SPICE EXAMPLE CODE FOR PEEC IMPLEMENTATION………… … 172

APPENDIX F……… ……….182

OPTIMIZATION: MINIMUM, CONVERGENCE AND NOISE SENSITIVITY……… 182

ABSTRACT

This thesis derives efficient partial element equivalent circuit (PEEC) models

in homogeneous media, dielectric mesh media, inhomogeneous media with multilayered composites and applies the models for the development of a novel test interface for wafer level packages (WLP) operating at multi-gigahertz frequencies given the tight geometrical constraints of fine pitch (of the order of 100 micron) off-chip interconnects and large device pin counts (of the order of thousands)

PEEC scaling technique incorporating Baker-Campbell-Hausdorff-Dynkin series for the analysis of fine pitch geometries has been proposed An improved PEEC model is derived for homogeneous media through the scaling of circuit elements The model is verified with a stripline geometry Relatively good agreements between the Method of Moments simulation data and the results generated from the scaled circuit model are obtained PEEC modeling is then extended to lossy silicon substrates using the theory of complex images The model is verified with a measurement based lumped circuit model The model is found to agree with measured data over a wide frequency range for coplanar waveguides fabricated on a high resistivity silicon substrate

For wafer level package test application, there is a need for using elastomer mesh probes due to vertical and lateral compliance requirements A novel circuit model is developed for treating the dielectric-metal composite mixture that the probe

is built with The local interaction between the dielectric and metal is factored into the

PEEC model of multilayer dielectric geometry is next developed to address the signal redistribution in WLP test hardware To do this, the concept of mutual interactions between circuit elements is extended to an interface function Isolation of the self and mutual components lends itself to separate treatment of the interface from the bulk substrate This formulation was first tested in a quasi-static capacitance problem in a micro-strip The per unit length capacitance was evaluated for different geometries and material properties Then, transmission characteristics of a multilayered coupled micro-strip filter were analyzed The treatment of the dielectric interface in terms of the convolution of the interface function and source function in pulse basis is found to give satisfactory results compared to other independent studies

This thesis combines the modeling techniques derived above for developing a prototype test interface comprising of a compliant elastomer mesh for probing fine pitch wafer level packaged devices The prototype has been built to handle multi-gigahertz signal propagation using 100 micron pitch GSG mesh-coplanar probes The components of the prototype namely multilayer PCB with connectors, elastomer mesh probe, WLP interconnect and coplanar transmission lines have all been modeled A complete system level model has been developed The validity of the modeling as well as the efficacy of the prototype system for WLP test is demonstrated with model simulation and measurement results

LIST OF FIGURES

Fig 1.1: DDE network with two nodes……… … ………… ……… 4

Fig 1.2: Simulation setup for S11 and S 21……… … ………… ……….……… 8

Fig 1.3: Simulation setup for S22 and S 12 ……… ………… ……… ……… ……….8

Fig 2.1: PEEC model……….……… … 18

Fig 2.2: Sectioning the object geometry into inductance partitions……… ….……… 21

Fig 2.3: Sectioning the object geometry into capacitive partitions……… …… 21

Fig 2.4: Cross-section of strip transmission line ……… … …….……… …… 28

Fig 2.5: S21 magnitude (linear) versus frequency ……….……… …….……… …… 30

Fig 2.6: S21 phase (Degrees) versus frequency ………… ………….…… ….……… …… 31

Fig 2.7: S21 magnitude and phase error versus frequency….………… ……….……… 31

Fig 2.8: S11 magnitude and phase error versus frequency…….……… ……….……… 32

Fig 2.9: S11 phase (Degrees) versus frequency ………… ……….…….……… …… 33

Fig 2.10: S11 magnitude and phase error versus frequency….……….……… …… 34

Fig 2.11: Scaling coefficient versus solution error….………….……….……… …… 35

Fig 2.12: Scling coefficient versus sensitivity….……….……… …… 36

Fig 3.1: Image ground plane for a coplanar transmission line on a lossy silicon substrate………… 39

Fig 3.2: PEEC model of transmission line on lossy substrate ……… 40

Fig 3.3: (a) Equivalent circuit and (b) flowchart showing the lump model approach……… 43

Fig 3.4: Measurement setup… …… ……….……… ……… 46

Fig 3.5: Re( S21 ) measurement versus simulation… ……… ……….….……… …….…… 46

Fig 3.6: Im( S21 ) measurement versus simulation… ……….…….……… ………… 47

Fig 3.7: Re( S11 ) measurement versus simulation… ……….……….……… …… … 47

Fig 3.8: Im( S11 ) measurement versus simulation… ………….………….……… … ….… 48

Fig 4.1: Elastomer dielectric mesh without metallization……… ………… ….……… …… 52

Fig 4.4: Elastomer coplanar probe layout M+D represents the mixture of metal and polymer mesh

material D represents the polymer mesh alone GSG represents air coplanar probe used for VNA

measurements.……….……… …… 58

Fig 4.5: Physical test sample of Elastomer probe (a) Top view (b) Cross-section ………… ……… 59

Fig 4.6: PEEC for Elastomer mesh coplanar line… ……… ….……….… 59

Fig 4.7: Insertion Loss (S21 ) measurement versus PEEC model…… ….… … ……… 60

Fig 4.8: Return Loss (S11 ) measurement versus PEEC model……….………… … ……… …… 61

Fig 5.1: Interface between two dielectrics ……… 67

Fig 5.2: Interfaces within multilayer dielectrics ……… 71

Fig 5.3: Open wire loop of two conducting bars in series ….……… 72

Fig 5.4: System of two insulated spheres……… ……… 73

Fig 5.5: Microstrip geometry……… 76

Fig 5.6: Effective permittivity versus w/h……….……… 76

Fig 5.7: Cell structure for finite conductor including (a) multilayer dielectrics (a) with multilayer split into two bulk layers and an interface layer……… 77

Fig 5.8: PEEC model at metal and dielectric interface……… …… 80

Fig 5.9: PEEC model at dielectric interior………… ……… 82

Fig 5.10: Coupled microstrip filter geometry (a) Top metal layer (b) Intermediate metal layer (c) Multilayer cross section backed by ground plane (hashed segment represents coupled line; solid segments represent single transmission line / metal patch) ……… 84

Fig 5.11: Equivalent circuit for a coupled microstrip………….… ……….… 85

Fig 5.12: Equivalent circuit at the interface layer nodes……… ……… 85

Fig 5.13: S21 magnitude response of three layer coupled line filter……… …… ……… 86

Fig.5.14: Four layer coupled microstrip filter geometry (a) Top metal layer, (b) Second metal layer, (c) Third metal layer and (d) Multilayer cross section backed by ground plane (hashed segment represents coupled line; solid segments represent single transmission line / metal patch) ……… 87

Fig 5.15: S11 magnitude response of four layer coupled line filter….……… ……… 87

Fig 6.3: PCB top layer with SMA connector footprints Elastomer mesh is the square sheet in the

centre ……… 94

Fig 6.4: PCB (a) Signal layer and (b) Cross-Section ……….… 95

Fig 6.5: Elastomer mesh Sheet shown with a magnified probe (a) Physical structure and (b) Full wave model… ……… 96

Fig 6.6: Elastomer mesh with device under test…… ……… ……… 97

Fig 6.7: Fabricated prototype test fixture……… ……… ……… 97

Fig 6.8: Prototype test fixture components (mesh exposed) ……… ……… ……… 98

Fig 6.9: X-Ray image of the DUT coplanar structure (top view) ……… …… 99

Fig 6.10: SEM image of a fabricated copper column interconnect……… ……… 100

Fig 6.11: Equivalent circuit of the WLP transmission and pads………… ……… 101

Fig 6.12: Copper column interconnect geometry…… ……….103

Fig 6.13: Equivalent circuit of WLP interconnect Copper column………… ……… 103

Fig 6.14: Equivalent circuit model of Elastomer mesh plane……… ……… ……… 104

Fig 6.15: Equivalent circuit for Elastomer mesh plane with metallization …… …… ………… 105

Fig 6.16: Equivalent circuit for the mesh probe……… …… ……… 105

Fig 6.17: Multilayer substrate geometry (a) Cross-section and (b) Full wave model …… … … 107

Fig 6.18: Equivalent circuit for the PCB ground plane……… ……… … 107

Fig 6.19: Equivalent circuit at the multilayer interface………… ……… 108

Fig 6.20: Equivalent circuit for the PCB and coaxial via……… ……… 108

Fig 6.21: System level (a) PEEC model and (b) Full wave model ……… …… 111

Fig 6.22: Insertion loss measurement of WLP with single copper column…… ……… 113

Fig 6.25: (a) Insertion loss and (b) return loss measurement of WLP with multiple copper

column……… 116

Fig 6.26: Solder bump schematic ……….……… ……… 116

Fig 6.27: (a) Insertion loss and (b) return loss measurement of WLP with solder bump………… 117

Fig 6.28: SEM image of copper column interconnect: Before probing……….……… 118

Fig 6.29: SEM image of copper column interconnect: After probing…… ……… 118

Fig 6.30: Test hardware for VNA measurement (with dashed lines indicating signal path…….… 120

Fig 6.31: Functional test hardware (with dashed lines indicating signal path) … ……… 121

Fig 6.32: Wafer probe setup with functional test hardware……… 121

Fig 6.33: Eye diagram at 2.5 Gbps ……….……… 123

Fig 6.34: Eye diagram at 5 Gbps ………….……… 123

Fig 6.35: Eye diagram at 8 Gbps ………….……… 124

Fig A.1: Response of a two node DDE system to a Gaussian excitation…….……… 148

Fig B.1: Segmentation of source and field surface elements……… 149

Fig B.2: Circular approximation of a square patch for self term evaluation……… 152

Fig C.1: Equipotential spherical surface P due to point charges at A and B……… 155

Fig C.2: Equipotential flux lines associated with a line charge near a semi-infinite dielectric half- space……… 158

Fig C.3: Flux lines due to a line charge near a dielectric slab ……… 160

Fig C.4: Green’s function for the dielectric slab at the field distance of x=5 m, y= 7m and source distance of x’=75m, y’=0m ……….…… 161

Fig C.5: Relative difference in Green’s function for the dielectric slab at the field distance of x=5 m, y= 7m and source distance of x’=75m, y’=0m ……… 161

x=5m, y= 7m, source distance of y’=0m and slab width of 2m ……… ……… 162

Fig D.1: Fermi energy versus width of copper nanowire ……….……… 169

Fig D.2: Work function versus size of copper nanowire ……… ……… 170

Fig D.3: Ionization potential versus size of copper nanowire ……… 171

LIST OF TABLES

Table 2.1: S11 Magnitude error (percentage) and Phase error(degrees) ………….……… 32

Table 2.2: S11 Magnitude error (percentage) and Phase error(degrees) ………….……… …33

Table 2.3: Number of terms versus convergence error of BCHD series … …….……… …36

Table 4.1: Insertion loss Model versus Measurement relative error……….………….………….62

Table 4.2: Return loss Model versus Measurement relative error ……… …… …63

Table 4.3: Comparison of different probing technologies……… …64

Table 6.1::Test Fixture Part Details……….……….……… 94

Table 6.2: S21 Measurement and Model Data……… ………114

LIST OF SYMBOLS

A Magnetic vector potential

B Magnetic displacement vector

D Electric displacement vector

E Electric field vector

G(r,r’) Green’s function for the field at r due to source at r’

H Magnetic field vector

J Electric current density

ρ Electric charge density

CHAPTER 1

INTRODUCTION

1.1 Background and Motivation

In conventional integrated circuit (IC) packaging, test and burn-in are done after the IC is packaged using package formats such as Quad Flat Package (QFP), Ball Grid Array (BGA), or Chip Scale Package (CSP) But this singulated device test and burn-in at the packaged IC level is very expensive

Wafer Level Packaging (WLP) is a new paradigm in microelectronic packaging which provides solution, to arrest cost escalation, through miniaturization [1] WLP offers batch processing capability at the wafer level Since test and burn-in can be performed in one go with many devices in parallel, test productivity is multiplied while test cost is significantly reduced But the need to make electrical contacts to the large number of I/O pins with fine pitches of the order of 100 microns presents new problems

to the conventional wafer level test system Furthermore, the bandwidth requirements present difficulties in the selection of materials as well as integration and fabrication methods necessitating efficient modeling of test system interface to avoid costs of multiple prototyping cycles

Fine pitch WLPs with large number of input / output pins pose tremendous test

need to be compliant in the lateral direction to accommodate thermal expansion and contraction At the same time, they should offer good electrical contact for efficient signal transmission and integrity over several gigahertz frequency ranges

There are many test probes available currently that meets some but not all of the test needs of WLP semiconductor devices Coaxial probes and air-coplanar probes, for instance, provide high frequency operation but they are too bulky and so they are suited for low pin count device testing only The cantilever beam probes have been used traditionally in the industry for testing chips with pin counts of the order of hundreds but they are very bad for high frequency testing due to huge inductance of long lead length There are Cobra probes, membrane and DoD (die-on-die) probes from various sources but their problem is that they are not providing reliable contacts and are not scalable to very high pin counts (beyond a thousand or two) Thus the motivation behind this thesis

is to provide a new solution to testing WLPs using a novel elastomer mesh material based probe geometry with a fine pitch of 100 micron and a multilayer PCB for multi-gigahertz signal distribution The partial element equivalent circuit (PEEC) method [2] is used for modeling and physical realization of such a test interface The content of this thesis is, therefore, (a) the derivation of efficient PEEC model in homogeneous media from the Green’s function [3] and from the scattering parameter measurements, (b) derivation of efficient PEEC model in inhomogeneous media with dielectric mesh [4], (c) derivation of efficient PEEC model in inhomogeneous media with multilayered composites and (d) application of the PEEC models for the development and analysis of test interface for

device pin counts (of the order of thousands) In the following section, a review of the literature on PEEC method which has been developed over the past decades for modeling multi-conductor systems in homogeneous dielectric media is given

1.2 Partial Element Equivalent Circuit Modeling

In typical device applications, we are not interested in knowing the field values at every point in the domain of the problem We are only interested in the terminal or nodal voltages and currents There is the possibility to condense the field information into the circuit information that is good enough for most VLSI applications PEEC modeling suits the purpose due to the popularity and efficiency of circuit solvers like SPICE among VLSI design community for many decades The challenges are not only the complexity

of the 3D structures, but also an ever growing number of interconnects that must be modeled accurately PEEC provides an efficient option to handle the VLSI circuit complexity through its ability to reduce the problem order by condensing the field information at innumerable points into circuit element information over a more manageable number of area and volume elements PEEC method is similar to the moment method with pulse function used for weight as well as basis The interaction between capacitive displacement currents and the inductive conductor currents are to be considered for getting accurate results

The PEEC method is applicable in both time and frequency domain [5]-[6] Fast implementations of the method have been shown using fast multipoles and wavelets [7]-

improvements Model order reduction has been addressed by Antonini, Cullum and Cangellaris [17]-[24] Numerous applications of PEEC has been demonstrated for the case of interconnects, vias, power-ground planes, LTCC circuits, spiral inductors, accurate treatment of crosstalk, skin effect and dielectric loss [19]-[55]

The availability of better CAD tools for the extraction of inductances and capacitances makes the PEEC models attractive PEECs are equivalent to Maxwell’s equations in the limit of an infinite lattice of partial elements and when retardation field is neglected PEECs can be combined with other models, like transistors, for a circuit simulator like SPICE

Unlike differential equation RLC lump model, PEEC includes cross-coupling terms The mutual components are represented by delayed interaction The circuit equation thus obtained, which is actually a delay differential circuit equation (DDE), is solved by an implicit time stepping algorithm [56] The time domain solution of DDEs by time stepping algorithms is discussed in the next section The method for frequency domain solution of DDE system in circuit solver is detailed in section 1.4

1.3 Solving Delay Differential Equation (DDE) Systems

1.3.1 DDE Example with Two Nodes

Let φ1 and φ2 be the potentials of a network shown in Fig 1.1, with two nodes, which

is typical of the PEEC topology The nodes are separated by the partial inductance

11

p

L and partial resistance R The excitation and the load currents are I and S I L

respectively The partial coefficients of potentials (reciprocal capacitances)

corresponding to the two nodes are p and 11 p with the conductance component22 G Let

τ be the interaction time delay between the two capacitances Then, the MNA (modified

nodal analysis) equations of the equivalent circuit can be written as

The time factor t is implicit for all the state variables and is suppressed for brevity except

where delays are involved In matrix operator form, the MNA equations are,

'1

0

S S L

p

p G

1 11

t p

p

p

I t L

of the DDE system is illustrated with Matlab codes in Appendix A

1.3.2 Time Stepping Algorithm for Solving Delay Differential Equation Systems

Both explicit [57] and implicit [58] schemes are available in the literature to solve the delay differential equations Since implicit scheme is known to be stable, we use backward Euler method for the time domain solution [56]

Let A be the system matrix, and x’ be the state variables and w the input stimuli Then the

system is represented as

Time domain solutions have sometimes been found to diverge after a sufficient number of time steps, because of the accumulation of numerical noise The source of the noise could be numerical round-off errors or from the analytical and numerical approximations made in developing the circuit model The approximation errors are said

to introduce low-amplitude, right-half-plane, nonphysical poles into the model

Many techniques for solving late-time instabilities have been reported [59] Tijhuis [60] investigated using an improved time-interpolation scheme to increase the accuracy of

time derivatives Rao et al [61] used a conjugate gradient technique to control error

accumulation over time Smith [62] describes a procedure that considers the fact that time instabilities, generally being of a high-frequency nature relative to the correct response, can be filtered from the solution by averaging techniques

late-1.4 Scattering Parameter Analysis of Circuits

First each port is represented by a resistor in series with a voltage source The value of resistance is set to the reference resistance of the port, typically 50 Ohms The magnitude

of the source voltage is initially set to zero at all the ports

Fig 1.3: Simulation setup for S12 and S22

The scattering parameters are related by

12

where V1−, V2− are the reflected waves and V1+, V2+ are the transmitted waves at the ports

1 and 2 respectively Also, in Fig 1.1 V is the sum of the transmitted and reflected 11

waves at port 1 and V is the sum of the transmitted and reflected waves at port 2 Thus, 21

11 1 1

V =V++V−, (1.12a)

21 2 2

V =V++V−, (1.12b) and

1 1 1 11

V =V+−V−+V (1.13) Using equation (1.12a), equation (1.13) becomes

1 2 1

V = V+. (1.14) Using equations (1.10), (1.12a) and (1.14), S is given by 11

Fig 1.2 shows the circuit arrangement for the computations For computing S and 11 S , 21

the magnitude of the voltage source on the first port is set to 2Volts and the alternating current (AC) analysis [63] is run over the frequency range of interest For automatically performing subtraction, a 1Volt source is installed to obtainS 11

Similarly, as shown in Fig 1.3, S and 22 S are obtained from 12

22 22 1

S =V − , (1.17)

12 12

S =V (1.18) For convenience, the model simulation results are presented in the thesis in the form of scattering parameter (S parameter) data since it is easier to compare with the results of full-wave EM solvers without having to do FFT Example SPICE codes for S parameter analysis are given in Appendix E

1.5 Scope and Organization of this Thesis

This thesis presents the derivation and application of PEEC modeling for the development of a multi-gigahertz test interface for fine pitch wafer level packages First, efficient PEEC models for homogeneous media are derived from a new scaling technique based on Baker-Campbell-Hausdorff-Dynkin series [64] This technique leads to an order

of improvement in relative accuracy for predicting small quantities such as return loss Secondly, the PEEC models are extended to lossy silicon substrates and compared with lumped circuit model derived, by mapping the physical geometry to circuit elements and

due to material inhomogeneity and geometric discontinuity Thirdly, PEEC models for inhomogeneous media with dielectric mesh are derived The dielectric mesh substrate with metallization suits the need for test probes for wafer level packages Fourthly, PEEC model for multi-layer geometry is developed by considering additional interaction terms arising from multilayer interfaces Current generation of high speed devices and the hardware used for testing such devices are built with multi-layer substrates and boards to redistribute power and signal lines Hence, multilayer PEEC has practical significance in the design and test of devices operating at RF and microwave frequencies Finally, PEEC models derived above are combined and applied towards development of a complete test interface for fine pitch wafer level package for multi-gigahertz operation at probe pitch of the order of 100 micron

Chapter 2 derives a novel PEEC model based on a perturbation technique for scaling of circuit elements in homogeneous media Baker-Campbell-Hausdorff-Dynkin series [64] is used to scale the circuit derived from the geometry Circuit scaling is shown

to provide an order of magnitude of accuracy improvement in the prediction of return loss from PEEC models A strip line geometry is taken as a test case The results of the circuit model simulation are compared with that from Method of Moments (MoM) Relatively good agreements between the scaled circuit model simulation data and the MoM are obtained

PEEC modeling derived in Chapter 2 is extended to lossy substrates using the theory of images The extended model is compared with a measurement based lumped

ABCD matrix structure are used to derive the optimization algorithm A sample device having coplanar waveguide structure fabricated on high resistivity silicon substrate (2 kilo-ohm cm) is used as a test case The models and measurements are well matched over

100 MHz to 20 GHz range

For wafer level package test applications, there is a need to use elastomer mesh substrate based probes due to vertical and lateral compliance requirements A novel PEEC model is developed in Chapter 4 for treating the dielectric-metal composite mixture that the probe is built with The local interaction between the dielectric and metal

is factored into the electric field integral equation for accurate representation of the circuit elements The model is verified with measurements in a coplanar GSG (Ground Signal Ground) probe structure

In Chapter 5, PEEC method for multilayer dielectric geometry is presented To do this, the concept of mutual interactions between circuit elements is extended to an interface function Isolation of the self and mutual components lends itself to separate treatment of the interface from the bulk substrate This formulation is first tested in a quasi-static capacitance problem in a micro-strip The per unit length capacitance is evaluated for different geometries and material properties Then transmission characteristics of a multilayered coupled micro-strip filter are analyzed The treatment of the dielectric interface in terms of the convolution of the interface function with source function in pulse basis in the time domain is found to give satisfactory results compared

to other studies based on the method of moments

compliant elastomer mesh, a multilayer printed circuit board substrate with coplanar transmission lines and coaxial connectors are presented The test hardware is built to handle multi-gigahertz signal propagation using 100 micron pitch GSG mesh-coplanar probes The components of the test hardware such as the SMA connectors, coplanar transmission lines on the PCB, off-chip and on-chip interconnect of the WLP and elastomer mesh probe have all been modeled Two cases of system level model containing the above sub-systems, one based on PEEC and the other from full-wave solver, has been developed and compared The numerical results of scattering parameters from both modeling and the measurements on the prototype are found to be in good agreement over the frequency range from DC to 5 GHz

PEEC model is extended to lossy substrates and verified with a measurement based lumped circuit modeling methodology The lumped circuit modeling method is valuable where Green’s function approach fares poorly due to its singular behaviour and due to the

symmetry of the model and the consequent simplicity of the ABCD matrices are used to develop this method

PEEC method for modeling dielectric mesh medium including metallization is derived The mesh has novel electrical and mechanical properties that make it attractive for applications such as wafer level package test

Interface function coefficients based on the method of images is derived This method takes into account the effect of multiple stacks of dielectrics, which are common in current CMOS, LTCC and other integrated circuit and package fabrication technologies Multilayer PEEC modeling method is derived using the interface function This method makes it possible to represent multilayer objects in terms of circuit elements without the need to rely on full-wave field solvers

A test methodology is demonstrated for fine pitch (of the order of 100 micron), high pin count (of the order of thousands) wafer level packages at high frequencies (of the order of gigahertz) using elastomer mesh probes

The contributions made in this research are reported in the following publications:

1.6.1 Journals

1 J Jayabalan, B.L Ooi, M.S Leong and M.K Iyer, “A scaling technique for partial

element equivalent circuit analysis using SPICE,” Microwave and Wireless Components

Letters, IEEE ,Vol 14 , Issue: 5 , pp 216 – 218, March 2004

2 J Jayabalan, W Bin, D X Xu, B.L Ooi, M S Leong and M K Iyer, “A

measurements,” Microwave and Optical Technology Letters, Vol.45, Issue 2, pp

115-118, Wiley Interscience, April 2005

3 J Jayabalan, B.L Ooi, M.K Iyer and M.S Leong, “Modeling and application of

elastomer mesh for microwave probing,” IEE proceedings on Microwaves, Antennas and

Propagation, Vol.153, No 1, pp.83-88, Feb 2006

4 J Jayabalan, R Jayaganthan, A.A.O Andrew Tay and B.L Ooi., “Energetics of

Copper Nanowires,” International Journal of NanoScience, World Scientific, Singapore,

Vol 4, No 4, pp 717-724, Aug 2005

5 J Jayabalan, B.L Ooi, M.S Leong and M.K Iyer, “Novel Circuit Model for

Three-Dimensional Geometries with Multilayer Dielectrics,” IEEE Transactions on Microwave

Theory and Techniques, Vol 54, Issue 4, Part 1, pp 1331 – 1339, Jun 2006

1.6.2 Journal Submissions under Review

6 J Jayabalan, M.K.Iyer, M.D Rotaru, V.S Rao V Kripesh, B.L Ooi and M.S Leong,

“A novel test strategy for fine pitch wafer level packaged devices,” to appear in IEEE

CPMT Transactions on Advanced Packaging

2 J Jayabalan, C.K Goh, B.L Ooi, M.S Leong, M.K Iyer and A.A.O Tay, “PLL based

high speed functional testing, “IEEE Proceedings Asian Test Symposium, pp 116 – 119,

ATS 2003

3 J Jayabalan, W Bin, D X Xu, B.L Ooi, M S Leong and M K Iyer,” Pad modeling

from S-Parameter measurements,” in Progress in electromagnetic research symposium

proceedings, Nanjing, China, PIERS, Aug 2004

4 J.Jayabalan, M.D.Rotaru, Jimmy PH Tan, M.K.Iyer, B.L.Ooi and M.S Leong, “Test

Bench modeling and characterization for fine pitch wafer level packaged devices, IEEE

Electronics Packaging Technology Conference Proceedings, pp 502 – 505, Dec 2004

5 J Jayabalan, B.L Ooi, and M S Leong, “PEEC Model for Multiconductor Systems

Including Dielectric Mesh,” Asia Pacific Microwave Conference proceedings,Suzhou,

China, Vol 2, Dec 2005

6 J Jayabalan and M.D Rotaru, “High Frequency Characterizaion of 100 micron pitch

wafer level package interconnects,” to appear in IEEE Electronics Packaging Technology

Conference Proceedings, Vol 1, pp 171-174, Dec 2005

1.6.4 Patents

1 J Jayabalan, M.D Rotaru, M.K Iyer, and A.A.O Tay, “Compliant Probes and Test Methodology for Fine Pitch Wafer Level Devices and Interconnects,” filed in US Patents and Trademarks Office, No 11/207336, August, 2005

In PEEC modeling of micron size multi-conductor geometries, the resistance values are quite small, while the reactance values are relatively large at GHz frequencies This huge spread in the network component values leads to poor results or ill-conditioned matrices in circuit simulation using SPICE For example, in a microstrip structure, the

transmission parameter values (S ) from circuit simulation are accurate to within 5% of 21

since this does not improve the matrix condition A scaling technique based on the approximation of BCHD series [65]-[66] is applied to alleviate this problem

2.2 Deriving the PEEC Model in Homogeneous Media

The PEEC model in Fig 2.1 comes from mapping the field problem into a circuit problem The Maxwell equations are represented in the form of an Electric Field Integral Equation (EFIE) in terms of scalar and vector potentials

↑

Fig 2.1: PEEC model

Starting with the Maxwell equation,

E is a vector whose curl is zero This means that the vector is equivalent to the

gradient of a scalar called the scalar potential That is

E E E contains both incident ( E ) and i

scattered (E ) components For representing the scattered term, E=0 for a conservative s

Integrating the above equation over the volume, we arrive at the macroscopic Kirchoff’s voltage equation Since the voltage around the closed loop is zero, we have

half a cell away from each other This partitioning is clearly depicted in Figs 2.2-2.3 for the case of two dimensional object such as a thin conducting microstrip

Fig 2.2: Sectioning the object geometry into inductance partitions

Fig 2.3 Sectioning the object geometry into capacitive partitions

The integral of quasi-static free space Green’s function kernel which represents the circuit components is evaluated by numerical quadrature or using approximate analytical and closed form expressions [19], [67]-[69] for quick evaluation of component values The evaluation of the Green’s function kernel leads to the PEEC model with self- and

2.3 Baker-Campbell-Hausdorff-Dynkin Series Expression

Given two n n× matrices namely x and y, the objective is to find a power series

n

x e

n

∞

=

=∑ , (2.16)

holds The solution of the matrix problem could be obtained by treating x and y as

variable elements that obey certain non-commutative algebra rules It is assumed that the

matrices x and y are close to zero matrices to ensure the convergence of the series

To proceed with the derivation, a Hausdorff derivative operator is defined as

explicitly, a deformation of x and y in terms of a special series with variables u and v

gives

e e =e +αϕ u x + ⋅⋅⋅ −αψ v y + ⋅⋅⋅ e (2.20)