Detection and resolution enhancement of laser induced fault localization techniques 1

TABLE OF CONTENTS Page ABSTRACT ix LIST OF ABBREVIATIONS xi LIST OF SYMBOLS xiii LIST OF TABLES xvi LIST OF FIGURES xvii Chapter 1: Failure Analysis and Fault Localization Challe

DETECTION AND RESOLUTION ENHANCEMENT OF

LASER INDUCED FAULT LOCALIZATION

ACKNOWLEDGEMENTS

I would like to thank my supervisor, Prof Jacob Phang for his guidance for the last 6 years, beginning from my undergraduate final year In spite of his busy schedule, he never fails to allocate time every week to review my progress and gives valuable academic advice It is also under his supervision that I am given the opportunities to collaborate with local and overseas industry partners I am also thankful for his great efforts for getting grants or even out of his sponsorship for me to attend overseas conference whenever a paper is accepted He has trained me to be an independent and confident researcher

Another person whom I wish to express my heartfelt gratitude is the CEO of SEMICAPS, Mr Chua Choon Meng He has been a great industrial mentor to me throughout my graduate years He never fails to engage me in valuable technical discussions and to enlighten me with the needs of the industry He and his company have given me great equipment and facilities support in the course of our collaboration For these, I would like to take this opportunity to thank SEMICAPS and the staff

In addition, I would like to thank Dr Lap Chan and Dr Ng Chee Mang from GLOBALFOUNDRIES, Singapore for including me into the company postgraduate special project team They have provided me with invaluable training related to semiconductor wafer fabrication and the company has given additional top-up to my research scholarship This program has also given me great opportunities to interact and learn from other postgraduate students in the team who are researching on other semiconductor fields, from process, materials, reliability to novel transistor devices

I would also like to thank Mrs Ho Chiow Mooi, the principal laboratory officer and the staff of the Centre for Integrated Circuit Failure Analysis (CICFAR) for having provided excellent administration and logistics support throughout my PhD

candidature

Finally, I would like to thank my fellow peers who are in the same research team under the supervision of Prof Phang They have been a continual source of encouragement, moral support and of course fun in the midst of my postgraduate years Part of this work has also resulted from the collaboration with this team

Not forgetting my wife, Jeanette who has been my greatest source of love and one who never fails to lift me up when the going gets tough Thank you

TABLE OF CONTENTS

Page

ABSTRACT ix LIST OF ABBREVIATIONS xi

LIST OF SYMBOLS xiii

LIST OF TABLES xvi

LIST OF FIGURES xvii

Chapter 1: Failure Analysis and Fault Localization Challenges 1 1.1 Failure Analysis 1

1.2 Failure Analysis Challenges 2 1.3 Active and Passive Fault Localization Techniques 3 1.3.1 Photon Emission Microscopy 4 1.3.2 Laser Induced Techniques 5 1.3.3 Frontside and Backside Failure Analysis 6 1.4 Fault Localization Challenges 7

1.5 Project Motivation 11 Chapter 2: Physics & Literature Review of Laser Induced Detection Systems 14 2.1 Physics of Laser Induced Phenomena 14 2.1.1 Light Transmittance in Doped Silicon Substrate 14

2.1.2.2 Effect on Metal Interconnects and Silicon 17

2.3.2.3 Development of Dynamic Laser Stimulation Techniques 38

2.5 Resolution Enhancement with Solid Immersion Lens Technology 43

Chapter 3: AC-Coupled Laser Induced Techniques 49 3.1 Circuit Modeling of AC-Coupled Detection Systems 49

Chapter 4: DC-Coupled Laser Induced Technique 68

4.2 Differential Resistance Measurement Detection System 69 4.3 AC-Coupled and DC-Coupled Detection Systems Comparison 70

4.5 DReM Sensitivity Optimization 89

4.7 Sensitivity Comparison of AC-Coupled and DC-Coupled

Chapter 5: Pulsed Laser with Lock-In Detection 99

5.1.1 DC-Coupled Pulsed Laser Induced Signal Response 100 5.1.2 AC-Coupled Pulsed Laser Induced Signal Response 105

5.3.1.3 Lock-In Time Constant 128

5.3.1.5 Detection Sensitivity Variation with Pulsing Frequency 131

Chapter 6: Application of Pulsed Laser Induced Technique for

Localization of Cu/low-k Interconnect Reliability

Chapter 7: Effect of Refractive Solid Immersion Lens Parameters on the Enhancement of Laser Induced Fault Localization

7.3 TIVA Enhancements from RSIL 168

7.6 Effect of RSIL Parameters on Imaging and TIVA Enhancement 174 7.7 Combining RSIL and Pulsed Laser Induced Techniques for Effective Defect

Chapter 9: Recommendation for Future Work 193 9.1 Detection Sensitivity Enhancement with Double Lock-In Detection 193 9.2 Beyond Fault Localization to Defect Characterization 195

Abstract

Failure analysis is an integral step for the development and manufacturing of semiconductor integrated circuits Fault localization is the most crucial step in failure analysis as successful or unsuccessful fault localization determines the success or failure of the entire FA cycle The 2 key limiting factors for the application of laser induced fault localization detection systems on advanced technology node below 65

nm are detection sensitivity and resolution

The objective of this work is to develop techniques and enhancements to improve both the detection sensitivity and localization precision of existing laser beam techniques This would extend the applicability of the techniques and allow them to remain compatible for optical fault isolation for 65 nm technology node and beyond

To achieve this objective, a comprehensive theoretical and experimental study was firstly carried out to evaluate the sensitivity of existing fault localization detection systems Following then, a new dc-coupled laser induced fault localization detection system called Differential Resistance Measurement was developed for accurate measurement of laser induced phenomena It enhances sensitivity by eliminating the artifacts inherent in existing ac-coupled detection systems and allows precise localization of the resistive sites without artifacts, within a single scan

Next, a systematic approach was taken to assess and optimize the detection sensitivity

of pulsed laser with narrowband and wideband lock-in detection on both ac-coupled and dc-coupled detection systems By developing an analytical model based on heat transport mechanism to describe the pulsed laser induced phenomena of a biased

metal line structure, the sensitivity of pulsed laser with narrowband and wideband lock-in detection, and its dependence on pulsing frequency and sample thermal time constant were understood The key parameters for narrowband lock -in detection were optimized and this has resulted in achieving a detection sensitivity enhancement factor between 15 - 20 times at a frequency between 200 Hz - 1 kHz To overcome the long scan time and complex setup for narrowband lock -in, a software algorithm compatible for ac-coupled and dc-coupled detection systems was developed for implementing wideband lock-in detection within a single pulse period without a lock-

in amplifier In the same frequency range, sensitivity enhancement factor between 3 -

8 times has been achieved The significant sensitivity enhancement with the lock-in

detection was demonstrated on the localization of Cu/Low-k interconnect reliability

defects which were otherwise not detectable with conventional laser induced techniques

Refractive Solid Immersion Lens (RSIL) was adopted for backside failure analysis to improve localization precision The performance of RSIL on laser induced response was investigated at different focal planes and the conditions to optimize RSIL performances for both laser imaging and laser induced applications have been established Spatial resolution down to 300 nm and laser induced signal enhancement

of approximately 15 times have been achieved Combining lock-in detection with RSIL, the significant enhancement in detection sensitivity and localization precision was demonstrated on 65 nm microprocessor devices

LIST OF ABBREVIATIONS

AOI Area Of Interest

BEOL Back-End Of Line

Ercf Complementary Error Function

CMRR Common Mode Rejection Ratio

DVM Dynamic Laser Delay Variation Mapping

DReM Differential Resistance Measurement

DSIL Diffractive Solid Immersion Lens

DUT Device Under Test

EDFA Electronic Device Failure Analysis

FA Failure Analysis

FEOL Front-End Of Line

FET Field Effect Transistor

FWHM Full Width at Half Maximum

HPF High Pass Filter

IC Integrated Circuits

IPFA International Symposium of Physical & Failure Analysis of Integrated

Circuits

ISTFA International Symposium for Testing & Failure Analysis

ITRS International Technology Roadmap for Semiconductors

LADA Laser Assisted Device Alteration

LIA-SDL Lock-In Assisted Soft Defect Localization

LIVA Light Induced Voltage Alteration

LIA Lock-In Amplifier

MF-TLS Mixed Frequency Detection of Thermal Laser Stimulation

NA Numerical Aperture

OBIRCH Optical Beam Induced Resistance Change

OBIC Optical Beam Induced Current

PD Pupil Diameter

PEM Photon Emission Microscopy

PICA Picosecond Imaging Circuit Analysis

PSD Phase Sensitive Detection

RIL Resistive Interconnection Localization

R.M.S root mean square

RSIL Refractive Solid Immersion Lens

SA Spherical Aberrations

SCOBIC Single Contact Optical Beam Induced Current

SDL Soft Defect Localization

SEI Seebeck Effect Imaging

SIL Solid Immersion Lens

SNR Signal-to-Noise Ratio

SOM Scanning Optical Microscope

SOI Silicon-On-Insulator

SRM Series Resistance Measurement

TBIP Thermal Beam Induced Phenomena

TCR Temperature Coefficient of Resistance

TIVA Thermal Induced Voltage Alteration

XIVA Externally Induced Voltage Alteration

 Amplified pulsed laser induced voltage change for dc-coupled detection

system in time domain )

(

 pulsed

ac

v Amplified pulsed laser induced voltage change for dc-coupled detection

system in frequency domain

( z r

G 2-Dimensional carrier generation rate

LIST OF TABLES

Table 1.1 Key Parameters Relevant to Failure Analysis Extracted from

International Technology Roadmap for Semiconductors

8

Table 2.1 Advantages and disadvantages of OBIRCH and TIVA 29 Table 2.2 Seebeck coefficients for different materials 32 Table 3.1 Experimental parameters of TIVA, OBIRCH and TBIP for SNR

comparison

64 Table 4.1 Summary of the advantages and disadvantages of ac-coupled and

dc-coupled detection systems

85

Table 4.2 Experimental parameters for sensitivity comparison of ac-coupled

and dc-coupled detection systems

95

Table 5.1 Experimental settings for pulsed-TIVA and pulsed-DReM with

narrowband lock-in detection

132 Table 5.2 Experimental settings of TIVA and DReM with pulsing and

NB/WB lock-in detection and without pulsing

145

LIST OF FIGURES

Fig 1.1 Relative rates of increase in calculated defect power density versus

chip standby power density (normalized to 2001) for a typical internode short-circuit defect (shown in inset) Derived from fundamental ITRS data

10

Fig 2.1 Light transmittance of (a) 500 µm p-Si with different doping

concentrations and (b) p-Si at 1019 cm-3 with different thicknesses

15

Fig 2.2 Light transmittance of (a) 1064 nm laser and (b) 1340 nm laser

with varying doping concentrations and Si substrate thickness

16

Fig 2.3 Electrical characteristic of a forward biased silicon diode at an

increased temperature

19 Fig 2.4 Variation of reverse bias saturation current of a silicon photodiode

at an increasing temperature

20 Fig 2.5 Heat diffusion paths and dominant light to heat converters for (a)

frontside and (b) backside thermal stimulation on a field effect transistor

21

Fig 2.6 Critical photocurrent sources in CMOS with illumination from the

backside

22 Fig 2.7 (a) SEMICAPS SOM 1005 system block diagram and (b)

photograph of SEMICAPS SOM 1005

24

Fig 2.10 Frontside (a) reflected, (b) laser induced and (c) reflected-laser

induced overlay images for fault localization

26 Fig 2.11 Categorization of Laser Induced Techniques 27

Fig 2.13 Comparison of the voltage decrease at constant current biasing and

the current increase at constant voltage biasing under the same laser stimulus on a CMOS ACIC

30

Fig 2.15 Resistive defects localized with power alteration techniques 34

Fig 2.17 Backside reflected-SDL overlay image of an advanced

microprocessor with “fail-to-pass” sites denoted in white and the

“pass-to-fail” sites denoted in black

36

Fig 2.18 Shmoo plot with gray colour representing normal device

functionality

37 Fig 2.19 (a) FIB cross-section at defective site localized by RIL showing a

failing via and (b) the signal waveform across failing via

37 Fig 2.20 High magnification SDL overlay image of an ASIC sample 38

Fig 2.22 (a) OBIC and (b) SCOBIC images of transistor junctions 41 Fig 2.23 (a)LIVA logic map of cell rows, (b) LIVA difference image

between two states and (c) frontside reflected image of the scan area of a microprocessor

42

Fig 2.24 (a)Refractive solid immersion lens and (b) diffractive solid 44

Fig 3.4 (a) Test sample reflected-TIVA overlay image, (b) TIVA signal

image and (c) line profile across AA‟ showing signal mean s, noise mean n and noise standard deviation n

57

Fig 3.5 SRM voltage sensitivity measured across the DUT, v d, and the

supply voltage, v s, using the SRM setup described in Fig 3.2

pulsed laser of 47.6 mW laser power, A of 10 kV/V, v V of d

30.8mV and r d of 100 mΩ

62

Fig 3.9 Overlay of TBIP transient response with 4.7 mH inductor, R of L

17Ω and SRM response with R of 17Ω s

62

Fig 3.10 Signal images of TIVA, SRM and TBIP at various operating

conditions

64 Fig 3.11 (a) SNR , (b) voltage sensitivity and noise standard deviation

comparison for TIVA, SRM and TBIP

ac-coupled amplification at 200 V/V gain and 0.03 Hz – 10 kHz band pass filter

73

Fig 4.5 Laser induced signal across a metal line measured from ac-coupled

and dc-coupled detection systems with A v 1V /V , v d 1V ,

ms

t a 5 , 1 2.2msand 2 10ms

74

Fig 4.6 Frontside image of an NMOS transistor (W/L: 40 µm/0.4 µm) with

DReM signal overlaid in pseudo colour

75

Fig 4.7 Horizontal line scan signal profiles of (a) ac-coupled detection

systems taken from TIVA signal micrograph and (b) dc-coupled detection systems from DReM signal micrograph showing the signal mean ( s ), noise mean ( N ), and noise standard deviation(N)

76

Fig 4.8 Laser induced response on a signal location with laser “on” at time

= 0

77

μs/pixel, (b) 1 ms/pixel and (c) 2 ms/pixel

Fig 4.10 4.10 DReM signal micrographs and the corresponding line profiles

across DReM signal of the transistor at scan speed of (a) 100 μs/pixel, (b) 1 ms/pixel and (c) 2 ms/pixel

79

Fig 4.11 TIVA and DReM signal images at different point sample averaging

rate with laser scan speed of 10 µs/pixel

81 Fig 4.12 TIVA and DReM signal images at different amplifier band pass

filter settings

82

Fig 4.13 (a) Frontside reflected image, (b) DReM image of 105 Ω Al

serpentine test structure and (c) DReM image when DUT is vertically displaced

Fig 4.16 a (i) DReM reflected-overlay image, a (ii) TIVA image and a (iii)

DReM image when the laser scan is perpendicular to the 1.7 kΩ resistor structure; b (i) DReM reflected-overlay image, b (ii) TIVA image and b (iii) DReM image when the laser scan is parallel to the resistor structure

Fig 4.19 DReM (a) detection sensitivity, (b) voltage sensitivity and noise

standard deviation F 1 with varying R and 1 R 2

91

Fig 4.20 (a) DReM detection sensitivity, (b) voltage sensitivity and noise

variation at varying arm ratio

92 Fig 4.21 DReM resistance change measurement of a 15.3 Ω Al line

structure biased at 15.4 mV at varying arm ratio under 26.7 mW laser irradiation

94

Fig 4.22 (a) SNR, (b) voltage sensitivities and (c) noise standard deviation

comparison of ac-coupled and dc-coupled detection systems

96

Fig 5.1 Cross-section view of a metal line with 2 μm width and 0.5 μm

thickness

100 Fig 5.2 DC-Coupled laser induced voltage change at (a) 500 Hz and (b) 5

kHz with v d A v 1V and DUT 30s 103

Fig 5.3 Laser induced voltage change for ac-coupled and dc-coupled

detection systems at varying pulsing frequencies with v d A v 1V ,

s

 30 , 1 2.2msand 1 10ms

106

Fig 5.4 Control signal and pulsed-DReM signal with DUT biased at 30.8

mV, 26.4 mW laser power, voltage gain of 10 kV/V and bandpass settings DC-10 kHz

107

Fig 5.5 (a) DC-coupled pulsed-DReM and (b) ac-coupled pulsed-TIVA

signal response at varying pulsing frequency overlaid with simulated dc-coupled and ac-coupled response

110

Fig 5.7 Narrowband a(i) in-phase and a(ii) quadrature-phase correlation

functions and wideband b(i) in-phase and b(ii) quadrature-phase

113

correlation functions

Fig 5.8 Narrowband lock-in detection output for dc-coupled detection

systems with v d A v 1V and DUT 30s

116

Fig 5.9 (a) Narrowband lock-in detection output for ac-coupled detection

systems withv d A v 1V , DUT 30s, 1 2.2msand 2 10ms

(b) Narrowband lock-in magnitude output for dc-coupled and

ac-coupled detection systems

118

Fig 5.10 Wideband lock-in detection output for dc-coupled detection

systems withv d A v 1V andDUT 30s 120

Fig 5.11 Wideband lock-in detection output for ac-coupled detection

systems withv d A v 1V , DUT 30s, 1 2.2msand 2 10ms

122

Fig 5.12 Narrowband and wideband lock-in detection magnitude output for

dc-coupled and ac-coupled detection systems withv d A v 1V ,10sDUT 30s, 1 2.2msand 2 10ms

122

Fig 5.13 Pulsed-TIVA with narrowband lock-in detection experimental

setup

125

Fig 5.14 Frontside reflected- pulsed-TIVA overlay and pulsed-TIVA images

with dwell time of (a) 1.5 ms/pix and (b) 250 μs/pix at

kHz

f o 2 and LIA 500s

126

Fig 5.15 (a) Pulsed-TIVA with NB lock-in detection with normalized scan

speed, LIA/ pix at 200 Hz pulsing frequency with LIA = 5 ms and

2 kHz pulsing frequency with LIA = 500 μs

127

Fig 5.16 Line profiles across AA‟ of pulsed-TIVA images at (a) 2 kHz

withLIAof 500 μs and (b) 200 Hz withLIAof 5 ms at same laser power, pre-amplifier settings and biasing condition

127

Fig 5.17 (a) Detection sensitivity, dwell time, (b) voltage sensitivity and

noise standard deviation of pulsed-TIVA with normalized lock-in time constant, LIA T o at 500 Hz pulsing frequency

128

Fig 5.18 Frontside(a) reflected- pulsed-TIVA overlay and (b) pulsed-TIVA

images at f o 50Hz with LIA 500s ( LIA 0.025T o ) and

pix

ms /

5

narrowband lock-in detection at varying pulsing frequencies

134

Fig 5.22 Experimental setups of (a) pulsed-DReM and (b) pulsed-TIVA

with digital wideband lock-in algorithm

137 Fig 5.23 Waveforms describing the principles of software digital wideband

lock-in algorithm

137 Fig 5.24 Noise standard deviation of pulsed-TIVA with wideband lock-in

with averaging over N pulses at 1.8 kHz and 142 Hz pulsing

139

frequency with t d 0 and t d 45s , using v d A v 1V ,

s

 30 , 1 2.2msand 2 10ms

Fig 5.26 Sensitivity comparison of pulsed-TIVA and pulsed-DReM with

WB lock-in detection at varying pulsing frequencies

142

Fig 5.27 Sensitivity comparison between TIVA and DReM with and

without lock-in detection for ac-coupled and dc-coupled detection systems

147

Fig 5.28 Narrowband and wideband lock-in detection magnitude output for

dc-coupled and ac-coupled detection systems withv d A v 1V ,1sDUT 30s, 1 2.2msand 2 10ms

149

Fig 6.1 (a) Cu/low-k dielectric comb structure with line width/space of

0.18 μm/0.18 μm and total test area of 10-3

cm2 (b) Cross-section TEM image of the comb structure

153

Fig 6.2 (a) Frontside TIVA image of comb sample A at 66mW laser power

(b) Pulsed-TIVA signal image at 66mW laser power and pulsing frequency of 500Hz (c) Reflected and pulsed-TIVA overlay image

of comb sample A (d) TIVA and pulsed-TIVA vertical line profiles across defect site

155

Fig 6.3 (a) Frontside TIVA image of comb sample B at 66mW laser power

(b) Pulsed-TIVA image at 66mW laser power and pulsing frequency of 500Hz (c) Reflected – pulsed-TIVA overlay image of comb sample B.(d) TIVA and pulsed-TIVA horizontal line profiles across defect site

156

Fig 6.4 Frontside reflected and pulsed-TIVA overlay image of comb

sample A indicating the cross-sectioned sites

158

Fig 6.5 (a) SEM cross-section image at AA‟ displaying dielectric crack

paths from Cu top corners and (b) at BB‟ illustrating Cu extrusion through the crack paths

158

Fig 6.6 (a) SEM and (b) TEM cross-section image at CC‟ illustrating

dielectric breakdown of the dielectric cap and low-k dielectric (c) STEM-EDX line profile taken along the dotted line illustrating random Cu traces in the dielectric region

159

Fig 6.7 TEM cross-section of another failing comb sample displaying a

combination of dielectric stack burn and dielectric cracking through the Cu top corners

160

Fig 6.8 (a) & (b) Pulsed-TIVA overlay images of comb sample C with

three distinct defective spots

161 Fig 6.9 SEM cross-sections images of defect at spot 2 161 Fig 6.10 a(i) SEM and a(ii) TEM cross-section images of spot 1 b(i) SEM

and b(ii) TEM cross-section images of spot 3 showing metal

Fig 7.3 TIVA image (a) and reflected-TIVA overlay image (b) from a

polysilicon structure using Mitutoyo 20X objective

168 Fig 7.4 TIVA image (a) and reflected-TIVA overlay image (b) from a

polysilicon structure using Mitutoyo 20x objective and RSIL application

169

Fig 7.5 (a) Location of AA‟, (b)line profile of AA‟ and (c) normalized

signal intensity plot across TIVA signal spot

169

sFig 7.6 (a) Line profiles and (b) normalized intensity plot across TIVA

signal spot at varying focal planes with 20X objective and constant laser power of 26.4 mW

171

Fig 7.8 NA requirement and collection angle at various focal depths 173 Fig 7.9 Laser beam geometrical cone, within (a) mechanical aperture and

(b) larger than mechanical aperture

173 Fig 7.10 Change in TIVA signal enhancements with varying laser focusing

planes and objective NA

with 20X backing objective (NA: 0.24) and RSIL (b) SEM

cross-section image along AA‟

180

Fig 7.14 (a) Reflected-TIVA overlay image and (b) reflected–Pulsed-TIVA

overlay image of Microprocessor Device B with 20X objective(NA: 0.24)

181

Fig 7.15 (a) Reflected–TIVA overlay image and (b) reflected –

pulsed-TIVA overlay image at Region A of Microprocessor Device B with RSIL and 20X objective(NA: 0.24)

182

Fig 7.16 (a) Reflected-TIVA overlay image with 100X objective and (b)

reflected-pulsed TIVA overlay image of Region B of Microprocessor Device B with RSIL and 20X objective (NA: 0.24)

at 8.5 mW laser power

182

Fig 7.17 (a) Reflected - pulsed-TIVA overlay with 20X objective(NA: 0.24)

and RSIL at 1.5 mW laser power, (b) GDS layout of the RSIL field

of view and (c) SEM cross-section along BB‟ revealing defect in the active layer

183

Fig 7.18 (a) Reflected-Pulsed-TIVA overlay image with 100X objective

(NA:0.5), (b)reflected-pulsed-TIVA overlay image with RSIL and 50X objective (NA:0.42), (c) GDS layout and (d) TEM cross-

section along CC‟ of Microprocessor Device C

Chapter 1: Failure Analysis and Fault Localization

Challenges

1.1 Failure Analysis

Failure analysis (FA) is an integral step for the development and manufacturing of semiconductor integrated circuits (IC) It occurs at all stages of the manufacturing process from design and wafer fabrication to IC packaging and applications It involves electrical and physical measurements on circuits and materials to understand the failure mechanism and to find the root cause of failure This serves as a feedback

to improve the design or the manufacturing steps for greater yield and better device reliability However, since FA is a reactive step, it suffers from a lack in focus and funding The development of new FA tools and techniques to improve analytical capability also lags mainstream activities of design, manufacturing and test [1]

Failure analysis is usually a sequential process involving 5 main steps, namely: failure validation, fault localization, sample preparation and defect tracing, defect characterization and root cause determination [2] Failure validation involves verification of the fail units received from the automated test environment in a laboratory environment using hardware tools, like bench testers, parametric analyzers and logic analyzers The failed units are then categorized based on common failing characteristics to reduce the quantity of units for in-depth FA Packages related or die related failures can usually be identified after this step Fault localization is then carried out using localization techniques to isolate the defective areas on the failed units Units with isolated defect sites are prepared for deprocessing steps involving

delayering, polishing, etching or cross-sectioning to access the defects The defect characterization step involves imaging and analyzing the physical properties of the defects using common tools, such as Scanning Electron Microscope and Transmission Electron Microscope for high resolution imaging, Energy Dispersive X-Ray and Auger Electron Spectroscopy for elemental mapping and depth profiling The objective is to determine the root cause of the failure Finally, corrective measures are taken for design related or process related failures to improve the manufacturing yield

or reliability of the devices Among these 5 steps, fault localization is the most critical step in failure analysis since it reduces the area required for the analysis dramatically [3] and determines the success or failure of the analysis

1.2 Failure Analysis Challenges

The challenges for failure analysis are dictated by the scaling and development of integrated circuits according to the International Technology Roadmap for Semiconductors (ITRS) [4] The roadmaps and needs for FA are also addressed by the International SEMATECH IC Failure Analysis Council and Packaging and Interconnect Failure Analysis Council [5,6] which are summarized in various reviews and publications [1,7-9]

The technical challenges for failure analysis are mainly in fault localization and defect characterization [9] where the former faces the greatest challenge driven by advancing

IC technology [1] Device scaling drives the need for fault localization tools and techniques with greater sensitivity and resolution in order to precisely relate an

circuits are incorporated in some logic devices, their isolation capabilities are rather limited and such functions are not available for analog and mixed signal devices Thus,

IC fault localization is dependent on instrumentation that images the physical manifestations of the defects, like photon emission, magnetic field strength, thermal distribution, or images the response of the defects due to a stimulating source, e.g., laser, sound wave or x-ray These instruments have limited sensitivity and resolution which would become less effective as the ICs become increasingly complex and circuit accessibility is reduced [1]

The advancement of IC technology also brings about an exponential increase in new materials incorporated in fully assembled ICs [1] These materials bring about new challenges in materials deprocessing and sample preparation, new failure mechanisms and material interactions with existing tools The introduction of new packages also requires new recipes for decapsulation

1.3 Active and Passive Fault Localization Techniques

In general, faults may occur at the package level or die level of a failed IC device Package level fault localization involves techniques for localizing package related issues like delamination, faulty or missing bond wires These techniques include Scanning Acoustic Microscopy and X-Ray Microscopy Die level fault localization, however, requires techniques which can accurately isolate the defect hidden among millions of transistors or buried among a multi-layer metallization stack This is the key bottleneck in the FA process As integrated circuits drive towards higher complexity with reduced transistor dimensions and increased metallization stacks,

different fault localization methodologies are required to provide adequate information on the physical location of the defects

1.3.1 Photon Emission Microscopy

Currently, there are two main categories of optical fault localization techniques for failure analysis, namely passive and active techniques Photon Emission Microscopy (PEM), based on electroluminescence, is the most common of the passive techniques With the sample biased in normal operating mode, failure sites that emit photons are localized from the frontside or backside of the sample using photon detectors [10, 11] The sources of emission come from inter-band electron-hole pair recombination or intra-band transitions [12]

Different PEM focal plane array detectors, namely silicon CCDs with a wavelength range of 0.3 μm – 1.1 μm, InGaAs with a wavelength range of 0.8 μm – 1.6 μm or HgCdTe with a wavelength range of 0.8 μm – 2.5 μm are used for photon detection The overall performance of a PEM system can be quantified by its detectivity [13].Examples of weaknesses that could emit photons include leaky junctions, contact spiking, oxide leakages, silicon mechanical damages, hot-electron effects, polysilicon filaments and CMOS latch-up [14] The origins of these emissions are from forward

or reverse-biased diodes, oxide breakdown resulting in undesired biased-diode or saturated transistors Metallization failures, however, do not emit photons because there is no electron and hole pair recombination It should be noted that a photon emission site may not necessarily correlate to a physical defect because photon

sometimes be due to the design or test conditions of the device The application of photon emission microscopy in FA has also been extended beyond fault localization

to defect characterization using the spectroscopic mode where the failure mechanism could potentially be characterized by its emission spectrum [15, 16] Time resolved photon emission has been developed to monitor the switching activities of transistors with picosecond timing resolution and the technique is known as Picosecond Imaging Circuit Analysis (PICA) [17]

1.3.2 Laser Induced Techniques

Active fault localization techniques involve the use of a scanned near-infrared laser beam in a scanning optical microscope (SOM) system to stimulate failures which are sensitive to thermal or carrier stimulation [18] The type of stimulation depends on the wavelength of the laser source and the bandgap energy of the device materials For example, a 1340 nm laser with 0.93 eV energy acts as a thermal stimulating source for

Si with a bandgap energy of 1.17 eV but inject carriers on Ge substrate with a lower bandgap energy of 0.66 eV With the device biased in its failure mode, the interaction

of the laser with the defects results in a significant electrical power change which could be amplified and mapped into an image to precisely identify the temperature sensitive sites or carrier active regions Based on these principles, a series of power alteration and test-based techniques have been developed over the decade to localize resistive defects, like metal shorts, damaged junctions resulting in hard failures and subtle soft defects giving rise to functional failures [18]

While PEM is able to capture the symptoms of existing leakage defects, laser induced techniques can precisely localize temperature sensitive latent defects Furthermore, laser induced techniques are effective in localizing ohmic shorts and shorted-metal interconnects whose thermal emissions (typically > 5μm wavelength) are not detectable by photon detectors Thus, these techniques complement each other and are often used together for more effective and accurate fault isolation [19-23]

1.3.3 Frontside and Backside Failure Analysis

Both PEM and laser induced techniques are compatible for frontside and backside failure analysis For PEM, the success of frontside analysis depends on the unobstructed detection of photons emitted from the defect location and backside analysis is limited to photon detection with wavelength in the near infra -red region due to silicon‟s 1000 nm absorption edge Laser induced detection depends on laser coupling efficiency through the multi-metallization layers for frontside analysis and laser absorption through possibly highly doped substrate for backside analysis For silicon based devices, 1064 nm laser is used for carrier injection while 1340 nm laser

is commonly chosen for thermal stimulation The wavelengths are chosen close to Si bandgap for highest transmittance through the backside and are also compatible for frontside analysis [24]

As IC technology advances, frontside analysis faces severe limitations due to the use

of increasing metallization layers This prevents emitted photons from the defects from reaching the photon detectors and obstructs effective laser stimulation at

metal layers and the spreading of heat from indirect laser heating degrades spatial resolution of the techniques [25] Moreover, the increasing use of flip-chip packages [26] to accommodate array I/O pads across the chip surface for high speed devices

makes frontside analysis unavailable

1.4 Fault Localization Challenges

The challenges in the application of laser induced techniques for fault localization in microelectronic failure analysis can be derived from the International Technology Roadmap for Semiconductors (ITRS 2005) which forecasts CMOS technology in near-term years through 2013 [4] The key parameters relevant to failure analysis are presented in Table 1.1 The roadmap indicates continual dimensional scaling in accordance with Moore‟s Law for the semiconductor industry The critical defect size follows the technology node and is specified at half of the half pitch value

Passive and active fault localization techniques are implemented in far-field optical systems where the resolution of fault localization is limited due to diffraction effects For backside analysis, the relevant wavelength range is from 1050 nm to 1600 nm At this range, the spatial resolution is generally limited to about 1 μm for a 0.7 numerical aperture (NA) objective lens This is 29 times larger than the critical defect size for the 65 nm technology node and corresponds to 20 DRAM cells or 3 transistors in the microprocessor unit To illustrate, for a defect in a 65 nm via chain which is localized

to a 1.5 μm signal spot size, 10 FIB cuts and SEM observations would be required in subsequent steps to image the physical defect [27] Since localization precision is

severely compromised, there is a need to enhance spatial resolution of these techniques for them to remain effective for 65 nm technology nodes and beyond

Table 1.1 Key Parameters Relevant to Failure Analysis Extracted from

International Technology Roadmap for Semiconductors [4]

Dimensional Scaling

MPU Metal 1 Half Pitch (nm) 90 68 45 32

Equiv Gate Oxide Thickness (Physical) (nm)

Extended Planar Bulk (High Performance)

1.2 1.1 0.65 NA Critical Defect Size (nm) 45 34 22.5 16

Complexity

Total Chip Area for MPU (mm2) 111 140 140 140

Total Chip Area for DRAM (mm2) 88 110 93 93

No of transistors per µm2 at production

(including on-chip SRAM) for MPU1

1.74 2.78 5.52 11.04

No of Cells per µm2 for DRAM1 12.2 19.5 46.1 92.4 Number of Metal Levels for MPU 11 11 12 13 MPU Total Interconnect Length (m/cm2) 1019 1439 2222 3125 Number of Metal Levels for DRAM 4 4 4 4

Electrical Performance

Power Supply Voltage for MPU (V dd ) (V) 0.9 -1.1 0.8 -1.1 0.7-1.0 0.6 -0.9 Allowable Maximum Power for MPU (W) 200 300 300 300 On-chip Clock Frequency (MHz) 5,204 9,285 15,079 22,980 Sub-threshold Leakage (I sd,leak ) (µA/µm)

Extended Planar Bulk (High Performance)

0.06 0.2 0.28 NA MPU = Microprocessor Unit

DRAM = Dynamic Random Access Memory

1

Derived from ITRS Data

Another main challenge following device scaling is the effectiveness of existing laser induced techniques due to reduced detection sensitivity on advanced nodes The key success factor of laser induced techniques for fault localization is detection sensitivity, which depends on the following factors:

i laser power at the defect location ;

ii generation efficiency of the laser induced signal ;

iii detection efficiency of the laser induced signal ;

iv noise in the system

The detection sensitivity depends on the coupling efficiency of the laser interacting with the defect that is buried in the active or within the multi-metallization layers and how much of the induced signal is detectable by the detection systems Although sensitivity can be increased by increasing laser power or biasing electrical power, there is a limit to the maximum laser power that can be used to avoid laser induced damages Increasing biasing power is also usually not favored as it risks aggravating the defect condition or over-stress Table 1.1 shows that ICs scale physically with the reduction of gate oxide thickness by about 50% This will drive to the point where the applicable dosage of laser power has to be reduced before it adversely affects the

oxide properties Recent developments in low-k and high-k dielectrics exhibit easier

contact and silicide breakdowns which require lower laser power resulting in a weaker induced signal for detection [28] While the number of metallization levels remains almost the same, the density of interconnects increases by 1.4 times, indicating higher chances of defects being obstructed by higher level metal layers, reducing laser coupling efficiency

The on-chip frequency is expected to increase from 5 GHz to 23 GHz by 2013 This indicates tighter device “on-off‟ margins and an expected increase in defects without physical signature arising from the effect of parasitic resistance or capacitance on functional operating range [3] In addition, failure analysis involving real-time speed tests will have to be tester-docked since cable and other adaptive solutions would result in significant speed degradation between tester and the device under test (DUT) Although the operating voltage decreases gradually, the transistor leakage shows an exponential rise Higher standby currents show up as thermal or electrical noise, and denser interconnect increases inter- and intra-metal levels „cross-talk‟ This

is well illustrated in Fig 1.1 showing that the signal-to-noise ratio (SNR) for laser beam techniques in CMOS is threatened by noise, which is dependent on standby power density It shows that noise is increasing at a faster rate than signal, which depends on defect power density

Fig 1.1 Relative rates of increase in calculated defect power density versus chip standby power density (normalized to 2001) for a typical internode short-circuit

defect (shown in inset) Derived from fundamental ITRS data [8]

Current technology nodes involve integrating new materials and more process steps into the manufacturing line This includes changing of backend metallization from aluminum to copper, the gradual move towards low-k inter-metal layer dielectric and high-k gate dielectric, the change from cobalt silicide to nickel silicide for better contact resistance and adopting metal gate for CMOS transistor All these may trigger new failure mechanisms resulting in critical defect sizes that are comparable to the device dimensions In summary, current laser induced techniques are becoming less effective for optical fault isolation in the 65 nm technology node and beyond

1.5 Project Motivation

The objective of this project is to develop techniques and enhancement methods to improve both detection sensitivity and localization precision of existing laser beam techniques This would extend the applicability of the techniques and allow them to remain compatible for optical fault isolation for 65 nm technology node and beyond

To achieve this objective, a comprehensive theoretical and experimental study is first carried out to evaluate the sensitivity of existing fault localization techniques A new dc-coupled laser induced fault localization technique for accurate measurement of laser induced phenomena is developed This technique eliminates artifacts which are inherent in existing ac-coupled techniques and is compatible for isolating gross and fine defects Pulsed laser with lock-in detection is then applied to improve detection sensitivity A software digital lock-in algorithm is also developed for easy implementation of lock-in detection without a lock-in amplifier Although some research groups have also reported successful detection sensitivity enhancement with lock-in detection, the key parameters affecting sensitivity remain uncertain A theoretical model based on heat transport mechanism is developed to understand the voltage sensitivity of pulsed laser with lock-in detection To date, a signal to noise enhancement of more than 20 times with lock-in measurement has been achieved The significant sensitivity enhancement with lock-in detection is demonstrated on the localization of Cu/Low-k interconnect reliability defects which are otherwise not detectable with conventional laser induced techniques

An effective approach to improve resolution is to use Solid Immersion Lens (SIL) technology Refractive Solid Immersion Lens (RSIL) involves placing a truncated Si

spherical lens on the surface of the Si substrate light to cause light refractions at the spherical surface In this work, RSIL is adopted for backside failure analysis to improve localization precision The performance of RSIL on laser induced response was investigated at different focal planes From this study, the conditions to optimize RSIL performances for both laser imaging and laser induced applications have been established Spatial resolution down to 300 nm and laser induced signal enhancement

of approximately 15 times have been achieved with its increased power density Combining lock-in detection with RSIL, the significant enhancement in detection sensitivity and localization precision is demonstrated on 65 nm microprocessor devices

This project involves collaborative work with several institutional and industrial partners, including Nanyang Technological University of Singapore, SEMICAPS Singapore Pte Ltd, Chartered Semiconductor Manufacturing (currently know as GLOBALFOUNDARIES Singapore Pte Ltd) and Advanced Micro Devices, Singapore Ltd

This report is organized and presented as follows:

Chapter 2 presents the fundamental theory behind laser induced applications and covers the reviews of the work done by other research groups

Chapter 3 develops the circuit models for existing ac-coupled detection systems to evaluate the signal sensitivity of these techniques It proposes a figure of merit for measuring the detection sensitivity of laser induced techniques by calculating the

signal to noise ratio from the laser induced signal image This method is then used to assess and compare the detection sensitivity of the techniques

Chapter 4 presents the development of a new dc-coupled detection system for detecting laser induced phenomena Optimization of the detection sensitivity of the detection system is discussed

Chapter 5 presents a systematic approach to assess and optimize the detection sensitivity of pulsed laser with lock-in detection on both ac-coupled and dc-coupled detection systems A theoretical framework for pulsed laser with lock-in detection is developed with experimental validation

Chapter 6 demonstrates the applications of pulsing with lock-in detection

configuration for effective localization of Cu/low-k interconnects reliability defects

which are not detectable by the limited detection sensitivity of existing techniques

Chapter 7 presents an in-depth experimental study to understand the performance of RSIL with laser induced detection systems for fault localization at different focusing planes and under different objective NA Combining RSIL with pulsing and lock-in detection on laser induced detection systems, a significant improvement in resolution and detection sensitivity is demonstrated on backside failure analysis of 65 nm microprocessor devices

Chapter 8 concludes the thesis and summarizes the key contributions of this research project and Chapter 9 proposes several recommendations for future work

Chapter 2: Physics & Literature Review of Laser Induced

Detection Systems

This chapter gives an overview on the physics involving laser interaction with devices This is followed by a description of the scanning optical microscope hardware system and the major signal pathways during localization A literature review on the development of laser induced techniques over the past decade for fault localization and defect characterization in microelectronic failure analysis is also presented

2.1 Physics of Laser Induced Phenomena

The physics of laser induced phenomena lies in the interaction between the focused laser beam and the DUT which is biased in its failure mode There are generally two types of stimulation namely thermal and carrier stimulation Laser photon energies which are greater than the device bandgap energy generate electron-hole pairs resulting in localized carrier injection while lower photon energies induce localized heating effects

2.1.1 Light Transmittance in Doped Silicon Substrate

Fig 2.1 shows the transmittance of light for different silicon thicknesses and different doping concentrations The figure is plotted based on the empirical model developed

by Aw et al [24] and Falk RA [29] to establish the reflectivity and optical absorption

coefficient of doped silicon

Fig 2.1 Light transmittance of (a) 500 µm p-Si with different doping concentrations and

(b) p-Si at 1019 cm-3 with different thicknesses [24,29]

It is evident that the steepest slope is at 1000 nm The absorption edge of Si at 1000

nm results in the absorption of virtually all light with wavelength lower than 1000 nm This absorption effect is due to phonon assisted absorption where the transition of an electron from the valence band to the conduction band occurs in the presence of phonon for an indirect bandgap material like Si Phonon assisted absorption decreases sharply with increasing wavelength and becomes negligible at 1.2 μm [24] At longer wavelengths, free carrier absorption effects become the dominant absorption mechanism and the absorption strength increases with wavelength and carrier concentration Therefore, Fig 2.1(a) shows that light transmittance decreases with increasing doping concentration Fig 2.1(b) shows that for a heavily doped Si substrate, light transmittance also decreases significantly with increasing silicon thickness

From these results, 1064 nm and 1340 nm semiconductor lasers are commonly used for laser induced applications on Si based devices 1064 nm laser is used for carrier stimulation and 1340 nm laser is used for thermal stimulation These lasers are chosen with wavelengths close to Si absorption edge to provide highest transmittance through

(a) (b) Fig 2.2 Light transmittance of (a) 1064 nm laser and (b) 1340 nm laser with varying doping

concentrations and Si substrate thickness [24, 29]

Based on the same model, Fig 2.1 is re-plotted in Fig 2.2 to illustrate light

transmittance of 1064 nm laser and 1340 nm laser against silicon thickness at

different doping concentrations for laser based applications It shows that the

absorption effect on 1064 nm laser is stronger than 1340 nm This is due to significant

phonon assisted absorption on 1064 nm laser which is on the other hand negligible on

1340 nm laser Since the absorption effect increases with doping concentration and Si

thickness, Si substrates are often required to be thinned for reasonable laser

transmittance for backside analysis This is especially so for highly doped substrate

(>1E18 cm-3) where substrates are thinned down to around 100 – 200 μm thickness

for laser based applications To further improve laser transmittance, an anti-reflection

coating can be applied at the Si surface to reduce light reflectance at the Si-air

interface [30, 31]

2.1.2 Thermal Stimulation

For silicon devices, the 1340 nm laser is used for thermal stimulation Since the

generated The effect of thermal stimulation on temperature change, materials and device parameters are described in the following section

2.1.2.1 Temperature Change

The temperature change due to 1340nm laser heating is an important parameter for the understanding of laser induced effects As the focused laser scans across an integrated circuit, the effective temperature change is a function of the power density, heat absorption capabilities of the materials and also the dimensions of the materials relative to the laser spot size The results of separate thermal modeling studies have shown temperature change of 1oC/mW on Si substrate [32] and 0.55oC/mW on 1 μm width metallic line embedded in SiO2 [33] A temperature change of 4.4oC/mW has also been measured using the threshold voltage shift in 0.13 μm transistors fabricated

on Silicon-On-Insulator (SOI) process [34] Although a convenient way to increase sensitivity is to increase laser power, this is usually undesirable due to the risk of laser induced damages cause by excessive localized heating [34, 35]

2.1.2.2 Effect on Metal Interconnects and Silicon

When a 1340 nm laser beam rasters across a biased device, the change in resistivity,

where0 is the resistivity before heating, TCRdenotes the temperature coefficient of

resistance (TCR) of the material and T is the change of temperature due to thermal