sử dụng giao thức rsvp (resource reservation protôcl) để ứng dụng trong mạng bị nghẽn

To reduce totalsystem cost, S3C2400 also provides the following: separate 16KB Instruction and 16KB Data Cache, MMU to handlevirtual memory management, LCD controller STN & TFT, 2-channe

INTRODUCTION

SAMSUNG's S3C2400 16/32-bit RISC microprocessor is designed to provide a cost-effective, low power, small diesize and high performance micro-controller solution for hand-held devices and general applications To reduce totalsystem cost, S3C2400 also provides the following: separate 16KB Instruction and 16KB Data Cache, MMU to handlevirtual memory management, LCD controller (STN & TFT), 2-channel UART with handshake, 4-channel DMA,

System Manager (chip select logic, EDO/SDRAM controller), 4-channel Timers with PWM, I/O Ports, RTC, channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, USB Host, USB Device, Multi-Media Card Interface, SPIand PLL for clock generation

8-The S3C2400 was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier Itslow-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitiveapplications Also S3C2400 adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture)

An outstanding feature of the S3C2400 is its CPU core, a 16/32-bit ARM920T RISC processor designed by AdvancedRISC Machines, Ltd The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate16KB instruction and 16KB data caches, each with a 8-word line length

By providing complete set of common system peripherals, the S3C2400 minimizes overall system costs and

eliminates the need to configure additional components The integrated on-chip functions that are described in thisdocument include:

• 1.8V internal, 3.3V external (I/O boundary) microprocessor with 16KB I-Cache, 16KB D-Cache, and MMU

• External memory controller (EDO/SDRAM Control, Chip Select logic)

• LCD controller (up to 4K color STN and 64K color TFT) with 1-ch LCD-dedicated DMA

• 4-ch DMAs with external request pins

• 2-ch UART with handshake (IrDA1.0, 16-byte FIFO)/1-ch SPI

• 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller

• MMC interface (ver 2.11)

• 2-port USB Host /1- port USB Device (ver 1.1)

• 4-ch PWM timers & 1-ch internal timer

• Watch Dog Timer

• 90-bit general purpose I/O ports/8-ch external interrupt source

• Power control: Normal, Slow, Idle, Stop and SL_IDLE mode

• 8-ch 10-bit ADC

• RTC with calendar function

• On-chip clock generator with PLL

Architecture

• Integrated system for hand-held devices and

general embedded applications

• 16/32-Bit RISC architecture and powerful

instruction set with ARM920T CPU core

• Enhanced ARM architecture MMU to support

WinCE, EPOC 32 and Linux

• Instruction cache, data cache, write buffer and

Physical address TAG RAM to reduce the effect

of main memory bandwidth and latency on

performance

• ARM920T CPU core supports the ARM debug

architecture and has a Tracking ICE mode

• Internal AMBA(Advanced Microcontroller Bus

Architecture) (AMBA2.0, AHB/APB)

System Manager

• Little/Big Endian support

• Address space: 32M bytes for each bank

(Total 256Mbyte)

• Supports programmable 8/16/32-bit data bus

width for each bank

• Fixed bank start address and programmable bank

size for 7 banks

• Programmable bank start address and bank size

for one bank

• 8 memory banks

— 6 memory banks for ROM, SRAM etc

— 2 memory banks for ROM/SRAM/DRAM(EDO

MPLL makes the clock for operating MCU atmaximum 150Mhz @ 1.8V

• Clock can be fed selectively to each functionblock by software

• Power mode: Normal, Slow, Idle, Stop mode andSL_IDLE mode

Normal mode: Normal operating mode

Slow mode: Low frequency clock without PLL.Idle mode: Stop the clock for only CPU

Stop mode: All clocks are stopped

SL_IDLE mode: All clocks except LCD arestopped

• Wake up by EINT[7:0] or RTC alarm interrupt fromStop mode

Interrupt Controller

• 32 Interrupt sources(Watch dog timer, 5Timer, 6UART, 8Externalinterrupts, 4 DMA, 2 RTC, 1 ADC, 1 IIC, 1 SPI, 1MMC, 2 USB)

• Level/Edge mode on external interrupt source

• Programmable polarity of edge and level

• Supports FIQ (Fast Interrupt request) for veryurgent interrupt request

• Dead-zone generation

• Supports external clock source

RTC (Real Time Clock)

• Full clock feature: msec, sec, min, hour, day,

week, month, year

• 32.768 KHz operation

• Alarm interrupt

• Time tick interrupt

General Purpose Input/Output Ports

• 8 external interrupt ports

• 90 multiplexed input/output ports

• Loop back mode for testing

• Each channel has internal 16-byte Tx FIFO and

• Supports the monochrome, 4 gray levels, 16graylevels, 256 color and 4096 colors for STN LCD

• Supports multiple screen size

— Typical actual screen size: 640x480,320x240, 160x160 (pixels)

— Maximum virtual screen size (color mode): 4096x1024, 2048x2048, 1024x4096 etc

• Supports power saving mode(Enhanced SL_IDLEmode.)

TFT (Thin Film Transistor) color displays Feature

• Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palettecolor displays for color TFT

• Supports 16 bpp non-palette true-color displaysfor color TFT

• Supports maximum 32K (64K using intensity)color TFT at 16 bpp mode

• Supports multiple screen size

— Typical actual screen size:

• 16-bit Watchdog Timer

• Interrupt request or system reset at time-out

IIC-BUS Interface

• 1-ch Multi-Master IIC-Bus

• Serial, 8-bit oriented and bi-directional data

transfers can be made at up to 100 Kbit/s in the

standard mode or up to 400 Kbit/s in the fast

mode

IIS-BUS Interface

• 1-ch IIS-bus for audio interface with DMA-based

operation

• Serial, 8/16bit per channel data transfers

• Supports IIS format and MSB-justified data

format

USB Host

• 2-port USB Host

• Complies with OHCI Rev 1.0

• Compatible with the USB Specification

version 1.1

USB Device

• 1-port USB Device

• 5 Endpoints for USB Device

• Compatible with the USB Specification

version 1.1

MMC Interface

• Multi-Media Card Protocol version 2.11compatible

• 2x16 Bytes FIFO for receive/transmit

• DMA-based or interrupt-based operation

SPI Interface

• Serial Peripheral Interface Protocol version 2.11compatible

• 2x8 bits Shift register for receive/transmit

• DMA-based or interrupt-based operation

Operating Voltage Range

ARM9TDMI Processor core (Internal Embedded ICE)

DD[31:0]

WriteBack

PA Tag RAM

Data MMU

AMBA Bus I/F JTAG

Data CACHE (16KB)

WBPA[31:0]

DPA[31:0]

Bridge & DMA(4Ch)

Clock Generator (MPLL)

A H B B U S

Interrupt CONT.

USB Host CONT.

ExtMaster

LCD DMA

LCD CONT.

A P B B U S

I2C

GPIO I2S

Watchdog Timer BUS CONT.

65 63 61

68 66

74 73 71 69

76 78 80

75

86 84 82

88 90 92

87

41 43 45 47 49 51 VDDi I2SSCLK/GPG1 I2SSDO/GPG3/I2SSDI MMCCLK/GPG4/I2SSDI SPIMISO/GPG7/IICSDA VDDIO

VSSIO LEND/GPD4 VLINE/GPD2 VM/GPD1 VSSi VFRAME/GPD0 VD0/GPC0

VD4/GPC4 VSSIO VD3/GPC3 VD5/GPC5 VD7/GPC7 VD9/GPC9 VD10/GPC10 VSSi VDDi VD11/GPC11 VD13/GPC13 VDDIO VD14/GPC14

169 171 173 175 177 179

157 159 161 163 165 167

OM1 VSSIO VSSA_ADC Avref AIN0 AIN2

98 96 94

100 101 103

Table 1-1 208-Pin LQFP Pin Assignment Pin

Number

Pin Name

Default Function

65 VSSIO VSSIO – – P vss3op

Table 1-1 208-Pin LQFP Pin Assignment (Continued) Pin

Number

Pin Name

Default Function

1-13

Table 1-1 208-Pin LQFP Pin Assignment (Continued) Pin

Number

Pin Name

Default Function

NOTES:

The @STOP shows the pin states when S3C2400 is in STOP mode

3 Hi-z or Pre means Hi-z or Previous state and which is determined by the setting of MISCCR register

4 AI/AO means analog input/output

5 P, I, and O mean power, input and output respectively

6 The I/O state @nRESET shows the pin status in the below @nRESET duration

nRESET

FCLK

@nRESET4FCLK

7 The below table shows the I/O types and descriptions.

vdd1ih, vss3I 1.8V Vdd/Vss for internal logic

vdd1ih_core, vss3I 1.8V Vdd/Vss for internal logic without input driver

vdd3op, vss3op 3.3V Vdd/Vss for external logic

vdd3t_abb, vss3t_abb 3.3V Vdd/Vss for analog circuitry

phot12sm output pad, tri-state, medium slew rate, Io=12mA

phsoscm26 Oscillator cell with enable and feedback resistor

phbsu50ct8sm bi-directional pad, LVCMOS schmit-trigger, 50Kohm pull-up resistor with control,

tri-state, Io=8mAphbsu50ct12sm bi-directional pad, LVCMOS schmit-trigger, 50Kohm pull-up resistor with control,

tri-state, Io=12mAphbsu50cdct8sm bi-directional pad, LVCMOS schmit-trigger, 50Kohm pull-up resistor with control,

tri-state, selectable output pad(open-drain or tri-state), Io=8mA

Table 1-2 208-Pin FBGA Pin Assignment (Continued) Pin

Number

Pin Name

Pin Number

Pin Name

Table 1-2 208-Pin FBGA Pin Assignment (Continued) Pin

Number

Pin Name

Pin Number

Pin Name

OM[1:0] I OM[1:0] sets S3C2400 in the TEST mode, which is used only at fabrication Also, it

determines the bus width of nGCS0 The logic level is determined by the pull-up/downresistor during the RESET cycle

ADDR[24:0] O ADDR[24:0] (Address Bus) outputs the memory address of the corresponding bank DATA[31:0] IO DATA[31:0] (Data Bus) inputs data during memory read and outputs data during

memory write The bus width is programmable among 8/16/32-bit

nGCS[7:0] O nGCS[7:0] (General Chip Select) are activated when the address of a memory is within

the address region of each bank The number of access cycles and the bank size can

be programmed

nWE O nWE (Write Enable) indicates that the current bus cycle is a write cycle

nBE[3:0] O Upper Byte/Lower Byte Enable(In case of SRAM)

nOE O nOE (Output Enable) indicates that the current bus cycle is a read cycle

nXBREQ I nXBREQ (Bus Hold Request) allows another bus master to request control of the local

bus BACK active indicates that bus control has been granted

nXBACK O nXBACK (Bus Hold Acknowledge) indicates that the S3C2400 has surrendered control

of the local bus to another bus master

nWAIT I nWAIT requests to prolong a current bus cycle As long as nWAIT is L, the current

bus cycle cannot be completed

DRAM/SDRAM/SRAM

Table 1-3 S3C2400 Signal Descriptions (Continued)

LCD CONTROL UNIT

VM O STN: VM alternates the polarity of the row and column voltage

INTERRUPT CONTROL UNIT

EINT[7:0] I External Interrupt request

DMA

UART

nCTS[1:0] I UART clear to send input signal

nRTS[1:0] O UART request to send output signal

IIC-BUS

IIS-BUS

USB HOST

USB DEVICE

SPI

SPIMISO IO SPIMISO is the master data input line, when SPI is configured as a master

When SPI is configured as a slave, this pin reverse its role

SPIMOSI IO SPIMOSI is the master data output line, when SPI is configured as a master

When SPI is configured as a slave, this pin reverse its role

When SPI is configured as a master and ENMUL is set, nSS is a slave select

When SPI is configured as a slave, nSS is also a slave select

Table 1-3 S3C2400 Signal Descriptions (Continued)

JTAG TEST LOGIC

nTRST I nTRST(TAP Controller Reset) resets the TAP controller at start

If debugger is used, A 10K pull-up resistor has to be connected

If debugger(black ICE) is not used, nTRST pin must be at L or low active pulse

TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's

states A 10K pull-up resistor has to be connected to TMS pin

TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic

A 10K pull-up resistor must be connected to TCK pin

TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and data

A 10K pull-up resistor must be connected to TDI pin

TDO O TDO (TAP Controller Data Output) is the serial output for test instructions and data

RESET & CLOCK & POWER

nRESET ST nRESET suspends any operation in progress and places S3C2400 into a known reset

state For a reset, nRESET must be held to L level for at least 4 FCLK after theprocessor power has been stabilized

OM[3:2] I OM[3:2] determines how the clock is made

OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source

OM[3:2] = 01b, Crystal is used for MPLL CLK source and EXTCLK is used for UPLL CLK source

OM[3:2] = 10b, EXTCLK is used for MPLL CLK source and Crystal is used for UPLL CLK source

OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source

When OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.When OM[3:2] = 10b, EXTCLK is used for MPLL CLK source only

When OM[3:2] = 01b, EXTCLK is used for UPLL CLK source only

If it isn't used, it has to be H (3.3V)

XTIpll AI Crystal Input for internal osc circuit

When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source.When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only

When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only

If it isn't used, XTIpll has to be H (3.3V)

XTOpll AO Crystal Output for internal osc circuit

When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source.When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only

When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only

If it isn't used, it has to be a floating pin

NOTES:

2 AI/AO means analog input/output

3 ST means schmitt-trigger

CLKOUT O Clock output signal The CLKSEL of MISCCR register configures the clock output

mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK

POWER

VDDi_MPLL P S3C2400 MPLL analog and digital VDD (1.8 V)

Address (L Endian)

Table 1-4 S3C2400 Special Registers (Continued) Register

Name

Address (B Endian)

Address (L Endian)

LCD CONTROLLER

Table 1-4 S3C2400 Special Registers (Continued) Register

Name

Address (B Endian)

Address (L Endian)

1-31

Table 1-4 S3C2400 Special Registers (Continued)

(B Endian)

Address (L Endian)

Acc.

Unit

Read/W rite

Function USB DEVICE

IIC

IIS

Table 1-4 S3C2400 Special Registers (Continued) Register

Name

Address (B Endian)

Address (L Endian)

SPI

Table 1-4 S3C2400 Special Registers (Continued)

(B Endian)

Address (L Endian)

little/big endian

4 It is very important that the ADC registers, RTC registers and UART registers be read/written by the specified access unit and the specified address Moreover, one must carefully consider which endian mode is used

5 W: 32-bit register, which must be accessed by LDR/STR or int type pointer(int *)

HW: 16-bit register, which must be accessed by LDRH/STRH or short int type pointer(short int *)

B: 8-bit register, which must be accessed by LDRB/STRB or char type pointer(char int *)

2 PROGRAMMER'S MODEL

OVERVIEW

S3C2400X01 has been developed using the advanced ARM920T core, which has been designed by Advanced RISCMachines, Ltd

PROCESSOR OPERATING STATES

From the programmer's point of view, the ARM920T can be in one of two states:

• ARM state which executes 32-bit, word-aligned ARM instructions

• THUMB state which can execute 16-bit, halfword-aligned THUMB instructions In this state, the PC uses bit 1 to

select between alternate halfwords

NOTE

Transition between these two states does not affect the processor mode or the contents of the registers

SWITCHING STATE

Entering THUMB State

Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operandregister

Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT,SWI etc.), if the exception was entered with the processor in THUMB state

Entering ARM State

Entry into ARM state happens:

• On execution of the BX instruction with the state bit clear in the operand register

• On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.) In this case, the PC isplaced in the exception mode's link register, and execution commences at the exception's vector address

MEMORY FORMATS

ARM920T views memory as a linear collection of bytes numbered upwards from zero Bytes 0 to 3 hold the firststored word, bytes 4 to 7 the second and so on ARM920T can treat words in memory as being stored either in Big-Endian or Little-Endian format

31840

23951

1062

1173

408Higher Address

Lower Address

Word Address

Most significant byte is at lowest address

Word is addressed by byte address of most significant byte

408Higher Address

Lower Address

Word Address

Least significant byte is at lowest address

Word is addressed by byte address of least significant byte

840

951

1062

1173

Figure 2-2 Little-Endian Addresses of Bytes whthin Words

OPERATING MODES

ARM920T supports seven modes of operation:

• User (usr): The normal ARM program execution state

• FIQ (fiq): Designed to support a data transfer or channel process

• IRQ (irq): Used for general-purpose interrupt handling

• Supervisor (svc): Protected mode for the operating system

• Abort mode (abt): Entered after a data or instruction prefetch abort

• System (sys): A privileged user mode for the operating system

• Undefined (und): Entered when an undefined instruction is executed

Mode changes may be made under software control, or may be brought about by external interrupts or exceptionprocessing Most application programs will execute in User mode The non-user modes' known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources

REGISTERS

ARM920T has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannotall be seen at once The processor state and operating mode dictate which registers are available to the programmer

The ARM State Register Set

In ARM state, 16 general registers and one or two status registers are visible at any one time In privileged User) modes, mode-specific banked registers are switched in Figure 2-3 shows which registers are available in eachmode: the banked registers are marked with a shaded triangle

(non-The ARM state register set contains 16 directly accessible registers: R0 to R15 All of these except R15 are purpose, and may be used to hold either data or address values In addition to these, there is a seventeenth registerused to store status information

general-Register 14 is used as the subroutine link register This receives a copy of R15 when a Branch and

Link (BL) instruction is executed At all other times it may be treated as a purpose register The corresponding banked registers R14_svc, R14_irq, R14_fiq,R14_abt and R14_und are similarly used to hold the return values of R15 wheninterrupts and exceptions arise, or when Branch and Link instructions are executedwithin interrupt or exception routines

general-Register 15 holds the Program Counter (PC) In ARM state, bits [1:0] of R15 are zero and bits

[31:2] contain the PC In THUMB state, bit [0] is zero and bits [31:1] contain the PC.Register 16 is the CPSR (Current Program Status Register) This contains condition code flags and

the current mode bits

FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq) In ARM state, many FIQ handlers do notneed to save any registers User, IRQ, Supervisor, Abort and Undefined each have two banked registers mapped toR13 and R14, allowing each of these modes to have a private stack pointer and link registers