Microsensors, MEMS and Smart Devices - Gardner Varadhan and Awadelkarim Part 13 pdf

12.2.4.1 Etching process The etching process begins with the initial cleaning of the metallised wafers, followed bythe deposition of a positive photoresist.. Then, it is cooled to room t

MEASUREMENT SETUP 343

fref x f sample

Figure 11.5 Block diagram of dual reference and sample analogue mixing circuit

sensor and reference oscillators, producing some degree of baseline offset Although themixing circuit technique will significantly reduce the effects of common mode interfer-ence, there is always the possibility that interference could compound and, therefore,increase measurement errors

Another option is to use an environmentally isolated precision reference oscillator

As the frequency from this protected reference oscillator will remain fixed, the mixedfrequencies from the reference and indicator sensor oscillator will not contain frequencycontributions from any interfering source (Crabb and Lewis 1973)

11.8 MEASUREMENT SETUP

The vector network analyser and associated calibration techniques make it possible toaccurately measure the transmission parameters of the devices under test The measure-ment schematic is shown in Figure 11.6 The network analyser consists of a synthesizedsweeper (10 MHz-40 GHz), test setup (45 MHz-40 GHz), HP8510B network analyser,and a display processor (Subramanian 1998; Piscotty 1998) The sweeper provides thestimulus and the test setup provides signal separation The display panel of the HP8510B

is used to define and conduct various measurements The system bus is instrumental incontrolling various other instruments The device to be tested is connected between thetest Port 1 and Port 2 The point at which the device is connected to the test setup is

called the reference plane All measurements are made with respect to this reference

plane The measurements are expressed in terms of the scattering parameters referred to

as S parameters (Subramanian 1998) These describe the signal flow within the network.

S parameters are defined as ratios and are represented by Sinn/out, where the subscripts in

and out refer to the input and output signal, respectively Figure 11.7 shows the energy

flow in a two-port network It can be shown that (see HP 8510B Network AnalyserManual 1987)

b1 = a1S11 = a 2 S1 2 and b 2 = a1S2 1 = a 2 S 22 (11–2)where S11 is b\la\ and 521 is b 2 la1 when a 2 is zero; 512 is b\la 2 and 522 is b 2 /a 2 when

a\ is zero S\\ and 521 (5i2 and 522) are the reflection and transmission coefficients forPort 1(2), respectively

Synthesized sweeper 0.01–40 GHz

HP 8510B Network analyzer

Test set 0.045-40 GHz Port l

Coaxial cable

Port 2

Power Macintosh 6100/66

HP plotter

Apple laser printer

Sample holder with SAW device T101 T101

Coaxial cable

Figure 11.7 Signal flow of a two-port network11.9 CALIBRATION

Calibration of any measurement is essential in order to ensure the accuracy of the system.The errors that exist in systems may be random or systematic Systemic errors are themost significant source of measurement uncertainty These errors are repeatable and can

be measured by the network analyser Correction terms can then be computed from these

measurements This process is known as calibration Random errors are not repeatable

and are caused by variations due to noise, temperature, and other environmental factorsthat surround the measurement system

REFERENCES 345

A series of known standards are connected to the system during calibration Thesystemic effects are determined as the difference between the measurand and the knownresponse of the standards These errors can be mathematically related by solving thesignal-flow graph (Subramanian 1998) The frequency response is the vector sum of alltest setup variations in magnitude and phase and the frequency This is inclusive of allsignal-separation devices, such as test setup and cabling

The mathematical process of removing errors is called error correction Ideally, using

perfectly known standards, these errors should be completely characterised The ment system is calibrated using the full two-port calibration method The four standardsthat are commonly used are shielded open circuit, short circuit, load, and through Thismethod provides full correction of directivity, source match, reflection and transmission-

measure-signal path, frequency response, load match, and isolation for S11, S12, S21, and S22 Theprocedure involves taking a reflection, transmission, and isolation measurement

For the reflection measurement ( S1 1, S2 2) , the open, short, and load standards are

connected to each port in turn and the frequency response is measured These six ments result in the calculation of the reflection error coefficients for both ports

measure-For the transmission measurement, the two ports are connected and the followingmeasurements are carried out forward through transmission (S21 -frequency response),forward through match (S21-load), reverse through transmission (S12-frequency response),and reverse through match (S12-load) The transmission error coefficients are computedfrom these four measurements

Loads are connected to the two ports and the S12 and S21 noise floor level ismeasured From these measurements, the forward and reverse-isolation error coefficientsare computed The calibration is saved in the memory of the network analyser and thecorrection is turned on to correct systemic errors that may occur

By making these measurements, it is possible to identify the critical acoustic parametersand thus design the optimal IDT-SAW microsensor The SAW microsensor may now befabricated, and the process is provided in the following chapter

REFERENCES

Avramov, I D (1989) Analysis and design aspects of SAW-delay-line-stabilised oscillators,

Proceedings of the 2nd Int Conf on Frequency Synthesis and Control, London, April 10–13,

pp 36-40

Campbell, C (1998) Surface Acoustic Wave Devices and their Signal Processing Applications,

Academic Press, London

Crabb, J and Lewis, M F (1973) "Surface acoustic wave oscillators: mode selection and frequency

modulation," Electronics Lett., 9, 195–197.

Gangadharan, S (1999) Design, development and fabrication of a conformal Love wave ice sensor,

MS thesis, Pennsylvania State University, USA

Grate, J W., Martin, S J and White, R M (1993) "Acoustic wave microsensors, Parts I and II,"

Anal Chem., 65, 940–948, 987–996.

HP 8510B Network Analyzer Manual (1987) Hewlett-Packard Company, Santa Rosa, Calif.Piscotty, D J (1998) 150 MHz wireless detection of a ST-cut quartz substrate surface acousticwave device, MS thesis, Pennsylvania State University, USA

Shiokawa, S and Moriizumi, T (1988) Design of SAW sensor in liquid, Proc of 8th Symp on Ultrasonic Electronics, Tokyo, July, pp 142–144.

Smith, W R and Gerard, H M (1971) "Differences between in-line and cross-field three-port

circuit models for integrated transducers," IEEE Trans Microw Theory Techniques, 19,416-417 Smith, W R et al (1969) "Analysis of interdigital surface wave transducers by use of an equiv- alent circuit model," IEEE Trans Microw Theory Techniques, 16, 856–864.

Subramanian, H (1998) Experimental validation and design of wireless microaccelerometer,

MS thesis, Pennsylvania State University, USA

Wohltjen, H and Dessy, R (1979) "Surface acoustic wave probe for chemical analysis," Anal Chem., 51,471–477.

trans-are commonly used to define the IDTs: etching and lift-off (Hatzakis et al 1980) Both

methods1 are suitable for the fabrication of IDT-SAW delay-line sensors, but the ultimatechoice of either the etching or the lift-off process mainly depends on the minimum featuresize (resolution and accuracy) of the patterned structure required Although the etchingprocedure is relatively easy to realise and acceptable resolution is achievable, it is moresusceptible to electrical shorts between features than that of the lift-off process This is amajor concern, especially for minimum feature sizes approaching 1–2 um, where the influ-ence of contaminants, such as large dust particles, becomes more significant (Vellekoop1994) However, for larger minimum feature sizes, of 5 um or greater, it is recognisedthat the etching process is acceptable and comparable in terms of device fabrication yieldand quality to that of the lift-off process

Section 12.2 provides full details of the steps required to make an IDT microsensorthrough either an etching process or a lift-off technique The process given here is meant

to serve as an example, and variations in the precise choice of materials and equipmentused will vary from laboratory to laboratory

Next, the steps required to make a Rayleigh-SAW microsensor from the IDTs areshown, together with a waveguiding layer of SiO2 (Section 12.3) to fabricate a Lovewave microsensor

Finally, in Section 12.4, we provide tables that summarise the etching and lift-offprocesses and present their relative merits

12.2 SAW-IDT MICROSENSOR FABRICATION

12.2.1 Mask Generation

SAW-IDT designs are written onto square, low-expansion glass plates using a process

of electron-beam (E-beam) lithography The SAW designs are first created using a Pattern transfer and etching methods were introduced in Chapter 2.

12

IDT Microsensor Fabrication

Figure 12.1 Overview of process required to fabricate Rayleigh wave and Love wave IDT

microsensors

computer-aided design (CAD) system (e.g L-Edit from Tanner Tools Inc.) and thenthe electronic design files are exported in a standard format (e.g GDS II) that offerscompatibility with the E-beam writer The IDT structures are thus written on a positiveresist material that coats the mask plate on which a thin chromium layer has alreadybeen deposited The resist is developed and the chrome is etched away to leave thedesired IDT structures It is common practice to make an inverse mask, or negative, fromthe master positive mask plates using a quicker and more inexpensive ultraviolet (UV)optical lithographic process It is these copies that are then used in the silicon run and,

if damaged, can be replaced immediately Figure 12.2 shows a typical IDT design thatwould be written onto the positive and negative mask plates

12.2.2 Wafer Preparation

Effective cleaning of the quartz wafers is a vital procedure, which is an essential ment for the successful fabrication of IDT microsensors In order to obtain good adhesionand a uniform coating of the metallic film used to make the IDTs, a thorough cleaning of

require-SAW-IDT MICROSENSOR FABRICATION 349

Figure 12.2 Basic layout of a photolithographic mask plate showing an IDT structure: (a) positive

and (b) negative fields

the wafer surface is essential The cleaning of the wafers should be performed in a fumecupboard (in a clean room) to allow the safe and fast removal of any possible harmfulfumes produced during the cleaning process (Campbell 1998; Atashbar 1999)

The wafers are initially cleaned of any surface contaminants, such as dust, grease,

or any other soluble organic particles, by immersion in trichloroethylene2 at 60 °C for

10 minutes, followed by an acetone bath at 60 °C for 10 minutes The wafers are thenrinsed with methanol and finally with deionised water It is best to avoid the use ofnitrogen gas for drying the sample during the aforementioned procedure so as to minimisefurther surface contaminants Instead, a slow evaporation in a protected fume cupboard

is employed Further cleaning is then undertaken for the removal of the more obstinatecontaminants The wafers are immersed in a mixture of three parts of deionised water(3H2O), one part ammonium hydroxide (NH4OH), and one part of 30 percent unsta-bilised hydrogen peroxide (H2O2) at 75 °C for 10 minutes Caution is required becausethe mixture is harmful, and it is recommended that the hydrogen peroxide is added last

so as to minimise any reaction side effects Next, the wafers are placed in a solution ofindustrial grade detergent and subjected to ultrasonic agitation at 60 °C for ten minutes.Following a rinse in deionised water, the wafers are placed in a circulating deionisedwater bath for 30 minutes The wafers are then dried using compressed filtered nitrogenand stored in an appropriate container and environment

12.2.3 Metallisation

A metal layer now needs to be deposited, from which IDT structures are to be formed Ingeneral, aluminum is evaporated using, for example, a Kurt Lesker™ E-beam evaporator.Aluminum is employed because it is commonly used in IC foundries and exhibits chemicalresistance to many different liquids3

Typically, a 100 to 150 nm layer of aluminum is deposited on the clean surface of aquartz wafer For example, the beam voltage of an E-beam evaporator is set to 6 keVduring the deposition of 150 nm of aluminum, the pre-evaporation pressure is set at

10-6 torr, and the beam current is set to almost 100 mA This gives an evaporation rate

of 0.2 nm/s It is to be noted that aluminum could have also been evaporated onto the' Caution needs to be exercised since trichloroethylene fumes are toxic.

Clearly, strong acids attack aluminum and should be avoided.

device using thermal evaporation instead of using the E-beam technique The E-beamtechnique, however, allows more control over the deposition rate, and the films tend to

be more uniform and to possess fewer stacking faults and dislocations

E-beam evaporation of aluminum is, indeed, compatible with both the etching and thelift-off processes used later on

12.2.4 Photolithography

The photolithography process is conducted in a clean room environment at a constanttemperature of, typically, 25 °C ± 1 °C and at a relative humidity of 40 ± 5 percent.The IDT structures need to be oriented correctly with respect to the quartz wafer in

order to generate the required Rayleigh (or Love) waves Figure 12.3 shows the correct

orientation of the wafer and the SAW-IDTs4

12.2.4.1 Etching process

The etching process begins with the initial cleaning of the metallised wafers, followed bythe deposition of a positive photoresist The wafers are first rinsed in a bath of acetone andthen in isopropanol to remove any possible loose surface contaminants that could haveappeared during storage since the initial wafer-cleaning procedure Next, the wafer isthoroughly rinsed in a deionised water bath for 5 minutes, followed by an oven bake

at 75 °C for 20 minutes This removes any moisture from the surface of the wafer.Using a Headway Research Inc.® spinner, hexamethyl disilazane (HMDS) is spun onthe wafer at 3000 rpm for 60 seconds to improve the adhesion of the resist to the wafers.After allowing the HMDS thin film to sit for 2 minutes, AZ-1512® positive photoresist(Hoechst) is then spun at 3000 rpm for 30 seconds A photoresist layer, approximately1.2 n,m thick, is formed The wafer is then baked in an oven at 90 °C for 30 minutes to

Major flat ST-quartz

Major flat ST-quartz

Figure 12.3 Orientation of an ST-quartz wafer and the SAW-IDT structures to fabricate Love

and Rayleigh wave sensors

The relationship between wafer flats and crystal orientation is defined in Section 4.2.

SAW-IDT MICROSENSOR FABRICATION 351remove any excess solvents from the photoresist Then, it is cooled to room temperaturefor approximately 15 minutes before exposing it to UV light in the mask aligner.

A contact mask aligner (Karl Suss MRK-3) is used to align the positive chrome mask

plate with the quartz that is wafer-coated with the photoresist A UV light exposure of

6 seconds is subsequently required The exposed wafer is then developed in a mixture of(ratio 1:4) AZ–450® developer (Hoechst) and deionised water for 40 seconds Great careshould be taken at this stage because under or overdeveloping the photoresist layer willdegrade the fabrication success It is strongly recommended that an immersion style isadopted, so that the wafer is slowly agitated during the developing process at 10 secondintervals, followed by a deionised water rinse and a close inspection using a microscope.This will provide for greater control in the important developing stage of fabrication A'soft' post bake is then performed at 75 °C for 10 minutes, which assists in the hardeningand formation of sharp features of the photoresist The wafer is then allowed to cool toroom temperature for approximately 15 minutes At this stage, the IDT pattern shouldhave been successfully transferred to the wafer; if not, the photoresist can be stripped off

in acetone and the entire procedure repeated before the etching of the wafer

Chemical wet-etching of the unwanted aluminum is then performed The aluminumlayer is first etched in a solution of a commercial etchant and deionised water (3.25 g ofetchant in 50 ml of deionised water) at room temperature for approximately 60 seconds.The etching time is extremely critical because undercutting of the structure walls mayoccur if prolonged times are employed It is strongly recommended that etching isperformed at 10 second intervals, followed by a deionised water rinse and close inspectionwith a microscope

The temperatures of the etchant solutions, together with the thickness of the metallayers, are important factors that have a significant influence on the etching times It isrecommended that the etching procedure is inspected for assurance before the processing

of valuable quartz wafers

Once the IDT design has been successfully transferred to the metallised wafer via theetching process, the wafer is ready for dicing (Campbell 1996, 1998) The dicing process

is described briefly in Section 12.2.5

12.2.4.2 Lift-off process

The lift-off process begins with an initial cleaning of the wafers, followed by the deposition

of a positive photoresist A similar cleaning procedure to that used for the etching process

is used to remove any possible loose surface contaminants that may have appeared duringstorage since the initial wafer-cleaning procedure Similarly, HMDS is spun on to thewafer using, for example, a Headway Research Inc.® spinner at 3000 rpm for 60 seconds

to improve the adhesion of the resist to the wafer After allowing the HMDS thin film

to sit for 2 minutes, AZ-1512® positive photoresist (Hoechst) is then spun at 3000 rpmfor 30 seconds A photoresist layer of approximately 1.2 um is formed The wafers arethen baked in an oven at 75 °C for 30 minutes to remove any excess solvents from thephotoresist The wafers are cooled to room temperature for approximately 15 minutesbefore UV light exposure

After aligning the negative IDT chrome mask plate with the photoresist-coated wafer

having a similar orientation to that used in the etching process, the wafer is exposed to

UV light for 6 seconds To improve the lift-off capability, the wafer is then immersed in

a chlorobenzene bath at room temperature for 3 to 3.5 minutes It is important to notethat this time varies depending on the intensity of the UV exposure lamp; typically, for

an intensity of 21 W/cm2, the characteristic time in chlorobenzene ranges from about 220

to 280 seconds This is an extremely critical step, and the procedure should be validatedbefore it is applied to the set of SAW wafers

Chlorobenzene modifies the surface of the photoresist by developing a characteristic'lip' in the developed pattern This creates a discontinuity at the edges of the patternedphotoresist when a metal is evaporated on the surface of the wafer; thus, unwanted metal

is subsequently removed more easily The wafer is then baked in an oven at 75 °C for

30 minutes to remove any excess solvents from the photoresist and allowed to cool toroom temperature for approximately 15 minutes The wafer is then developed in a mixture(ratio 1:4) of AZ-450® developer (Hoechst) and deionised water for 40 seconds

Again, great care should be taken at this stage, as under or overdeveloping the sist layer will degrade the fabrication success As in the etching process, an immersionmethod is strongly recommended, whereby the wafer is slowly agitated during the devel-oping process at 10 second intervals, followed by a deionised water rinse and thenclose inspection with a microscope It is important to prevent damage to the photoresist-patterned structures at this stage, so extremely gentle agitation is required in the immersionstep, and the use of compressed filtered nitrogen for drying the wafer should be avoided.Close inspection of the wafer surface using an optical microscope is then performed toexamine the transferred SAW-IDT pattern The edges of the photoresist patterns should

photore-be well defined and sharp to facilitate the lift-off process Again, if found unacceptable,the photoresist can be removed using acetone and the entire procedure can be repeatedbefore the metallisation of the wafer

After the metallisation of the photoresist-patterned wafer using the metal evaporationtechnique (Section 12.2.4), the photoresist is removed by immersing the wafers in anacetone bath at room temperature for 30 minutes Ultrasonic agitation may be used toassist in the removal process but caution is advised as damage to small patterned structures(feature sizes <2 nm) may occur

Once the IDT designs have been successfully transferred to the wafers via the lift-offprocess, the wafers are then ready for dicing (Section 12.2.5)

A summary of the photolithography process for both the etching and lift-off procedures

is shown in Figure 12.4

12.2.5 Wafer Dicing

The wafers are finally cut into small, individual chips using, for example, a Deckel™ wiresaw, together with a diamond impregnated wire and slurry The slurry is made from amixture of silicon, glycerol, and deionised water (3:5:1) and has a particle size of 25 um.Before cutting the wafer, a thick layer of AZ-4562® positive photoresist (Hoechst) isspun at 2000 rpm for 30 seconds, following the deposition of a thin HMDS layer spun on

to improve the photoresist adherence on the wafer The wafer is then baked in an oven at

75 °C for 30 minutes and then allowed to cool to room temperature The resulting thicklayer protects the delicately patterned IDT structures during the debris cutting

DEPOSITION OF WAVEGUIDE LAYER 353

Figure 12.4 Basic steps involved in two lithographic processes used to make IDT structure:

etching (left) and lift-off (right) on a piezoelectric (PE) substrate

12.3 DEPOSITION OF WAVEGUIDE LAYER

12.3.1 Introduction

Love wave sensors require the deposition of a guiding layer made from an acousticmaterial that has a shear wave velocity less than that of the quartz wafer Described nextare the process conditions and steps that should be followed to deposit SiO2 as a guidinglayer on top of a quartz wafer

Steps that occur during a typical chemical deposition process include (Campbell 1996)the following:

1 The transport of precursors from the chamber inlet to the proximity of the wafer

2 Reaction of these gases to form a range of daughter molecules

3 Transport of these reactants to the surface of the wafer

4 Surface reaction to release the SiO2

5 Desorption of the gaseous by-products

6 Transport of the by-products away from the surface of the wafer

7 Transport of the by-products away from the reactor

12.3.2 TMS PECVD Process and Conditions

One of the necessary conditions for the deposition of SiO2 is that the temperature ofdeposition should be as low as possible This is desirable because higher temperaturescan adversely affect the poling characteristics of quartz (in spite of the fact that quartz

is a naturally piezoelectric material) and because the melting point of the metallisationlayer (aluminum is 650 °C) should not be exceeded

We should therefore choose SiO2 that is either sputtered or deposited by enhanced chemical vapour deposition (PECVD) from silane gas The sputtering processprovides better step-coverage than evaporation and far less radiation damage than E-beam evaporation (Campbell 1996) A simple sputtering system consists of a parallel-plateplasma reactor in a vacuum chamber and the target material (SiO2) placed on the electrodesuch that it receives the maximum ion flux An inert gas (at a pressure of 0.1 torr) is usuallyused to supply the chamber with high-energy ions that strike the target at high velocitiesand dislodge the SiO2 molecules, which deposit conformal to the wafer (the SAW-IDTdevice) The only disadvantage in this process is that on account of the physical nature

plasma-of the process, sputtering could also bombard and damage the delicate IDT fingers on thesurface of the quartz Sputtering can also introduce a variety of contaminants from thesubstrate holder because of the physical nature of the process Hence, sputtering is notthe ideal means of depositing SiO2, despite the fact that the process can be carried outunder conditions of low temperature

An alternative approach is to use chemical vapour deposition (CVD) A simple CVDprocess is shown in Figure 12.5 The reactor consists of a tube with a rectangular cross

section, and the walls of the tube are maintained at a temperature T w A single wafer rests

on a heated susceptor in the centre of the tube

This susceptor is maintained at a temperature T s (where T s Tw) The obvious choice

is to use oxidised silane gas (SiH4) (also referred to as tetraethoxysilane TEOS) to formSiO2 in the presence of an oxidising agent, such as O2, and an inert carrier gas, such asH2 (to improve the uniformity of deposition) Excessive homogeneous reactions occurringspontaneously in the gas above the wafer will result in the deposition of large Si particles

in the gas phase, and their subsequent deposition on the wafer will cause poor surfacemorphology and inconsistent film properties

Figure 12.5 A simple CVD process flow system

DEPOSITION OF WAVEGUIDE LAYER 355Some of the other problems associated with PECVD (TEOS) are that (7) qualityplasma-enhanced chemical vapour-deposited tetraethoxysilane (PETEOS) SiO2 films are

difficult to achieve at temperatures below 250 °C (Alaonso et al 1992; Itani and Fukuyama

1997) and (2) TEOS has a low vapour pressure of approximately 2 mTorr (25 °C and

1 atm), which necessitates the heating of all delivery lines and chamber surfaces toprevent TEOS condensation and prevents gas metering with conventional mass-flow

controllers, thus rendering the resulting process prohibitively expensive (Ballantine et al.

1997) Conventional mass-flow controllers, on the other hand, easily meter silane gas,but great care must be used because silane is a toxic and pyrophoric gas and constitutes

an explosion hazard at high SiFU concentrations These limitations add to the cost andcomplexity of TEOS and silane-based silicon deposition equipment To achieve a lowtemperature, good quality oxide, and for the circumvention of the safety issues associ-ated with silane-based oxides and the manufacturing complexities inherent with TEOS,

an alternative precursor needs to be employed

Potential organo-silicon precursors are compiled and their critical physical and chemicalproperties are tabulated for comparison with the properties of silane and TEOS Of allthe precursors listed in Table 12.1, tetramethylsilane (TMS) can be chosen as the bestprecursor for the current low-temperature application for several reasons

TMS is known to be nontoxic and nonpyrophoric, and its high vapour pressure(580 mTorr) allows for the use of conventional mass-flow controllers at room temperature

Table 12.1 Tabulation of relevant parameters for feasible PECVD precursors (Gangadharan

208.3 Liquid

>99.991.5NoStableYesNoNontoxic (100)

TMS

Tetramethyl silane Si(CH 3 ) 4

88.2 Liquid 99.90589YesStableYes

MS

Methyl silane

CH 3 SiH 3

46Gas

C 4 H 16 0 4 Si 4

240.5 Liquid 99.906Not sure

**

YesNot sure

**

LTO-410, DBS Diethyl- silane SiH 2 (C 2 H 5 ) 2

88.2 Liquid

> 99.70207YesStableYes

**

**

Also, each parent TMS molecule (Si(CH3)4) contains half as much carbon and fifths as much hydrogen as a TEOS molecule (Si(OC2H5)4), and it is hypothesisedthat carbon and hydrogen-free films will be obtainable at lower temperatures from thisprecursor Additionally, the lower molecular weight of TMS might allow for higher surfacemobility than TEOS at any given temperature, thereby resulting in better-quality films attemperatures lower than those obtainable by PETEOS (~250 °C) Finally, it is thought thatPECVD TMS oxide (PETMS-Ox) deposition conditions could mimic very closely thoseconditions found to produce high-quality PETEOS and silane oxides in the semiconductorindustry (Campbell 1996; Ghandi 1994) Such deposition is carried out using a clustertool that is specifically fabricated for this process, and the four-chamber showerheadVactronics PDS-5000 S cluster tool PECVD reactor (Figure 12.6) is used.

three-The deposition procedures and conditions involve units 3 and 4 as follows: initially,

in the deposition chambers, TMS, 02, and He gas lines are evacuated of residual gasand then a sample is placed in a load-lock chamber (unit 3), which is evacuated fromatmosphere to a low pressure (typically 10—5-10—6 torr) This preinsertion vacuum time

is held at 30 minutes The SAW-IDT wafer is then placed on the preheated sample stage(unit 4) in the deposition chamber, which is maintained at 10—6 to 10—7 torr, by therobotic loading mechanism A period of 1 hour is allotted for the sample to come totemperature, after which 02 and He gases are input via the gas-dispersion showerheadand a period of 5 minutes is allotted for the flows to stabilise A plasma is struck withthe same pressure, RF power, and gas flow rates This 10-minute preclean plasma purgeserves three purposes:

1 It removes any residual carbonaceous matter left on the SAW device

2 It helps to form a stable interface oxide

3 It provides a high flow, stable plasma into which a miniscule flow of TMS can beinjected

Figure 12.6 Schematic representation of a PECVD unit

DEPOSITION OF WAVEGUIDE LAYER 357

Table 12.2 Main steps involved in the etching process

Step Description

(a) Exposure of photoresist metallised wafer with positive IDT mask plate.

(b) Develop photoresist patterned structures.

(c) Removal of unwanted metallisation layer via chemical wet-etching.

(d) Removal of photoresist layer.

Table 12.3 Main steps involved in the lift-off process

Step Description

(a) Exposure of photoresist bare wafer with negative IDT mask plate.

(b) Develop photoresist and formation of the characteristic lip.

(c) Deposition of metal layer onto the wafer.

(d) Removal of unwanted metallisation via acetone rinse.

Table 12.4 Summary of the main advantages and disadvantages of the etching and lift-off

tendency to undercut Ideal for small batch processing Susceptible to electrical shorts

Lift- off procedu re

Etchants not required Poor 'lift-off possible because of incorrect

formation of characteristic 'lip' Ability to reprocess patterned photoresist

structures before metal layer deposition

At the end of this preclean, the plasma remains and TMS vapour is introduced It is metered using a conventional 10 cubic centimeter per second (cc/s) mass-flow controller (MFC) to the desired volumetric flow rate The oxide deposition begins at this point and

is continued for a predetermined time to achieve an oxide film of the desired thickness Following the deposition, the TMS gas is turned off, but the O -He plasma is kept on