Microsensors, MEMS and Smart Devices - Gardner Varadhan and Awadelkarim Part 4 pdf

Worked Example E4.1: Vertical and Lateral Bipolar Transistors The standard bipolar process begins by taking a p-type substrate i.e.. The buried n-layer is used to minimise both the colle

conductivity In addition, SOI technology offers extremely low unwanted parasitic effectsand excellent isolation between devices (see Section 4.3.5).

4.3.1 Bipolar Processing

The bipolar process has evolved over many years, as has its so-called standard process.Clearly, this is an important issue and the integration of a microsensor, or microactuator,will depend on the exact details of the process that is employed As stated earlier, thepossible approaches to microsensors and MEMS integration and the problems associatedwith compliance to a standard process are both discussed in some detail in later chapters.This section presents what may be regarded as the standard bipolar process, whichemploys an epi-layer to make the two most important types of bipolar components; that

is, vertical and lateral transistors Bipolar n-p-n transistors are the most commonly used

components in circuit design as both amplifiers and switches because of their superior

characteristics compared with p-n-p transistors Let us now consider in detail the process steps required to make a vertical n-p-n and lateral p-n-p transistors A similar process can be defined to make vertical p-n-p transistors or the simpler substrate p-n-p transistors

with slightly different device characteristics

Worked Example E4.1: Vertical and Lateral Bipolar Transistors

The standard bipolar process begins by taking a p-type substrate (i.e single-crystal

silicon wafer) with the topside polished2 A buried n-layer is formed within the p-type

substrate by first growing an oxide layer The oxide is usually grown in an oxidationfurnace using either oxygen gas (dry oxidation) or water vapour (wet oxidation) at atemperature in the range of 900 to 1300 °C The chemical reactions for these oxidationprocesses are as follows:

Si(s) + 2H2O(g) SiO2(s) + 2H2(g) (4.6)Other ways of forming an oxide layer, such as CVD, are discussed in Chapter 5

The thermal oxide layer is then patterned using a process called lithography A basic

description of these processes is given in this chapter and a description about moreadvanced lithographic techniques is given in Chapter 5 Lithography is the name used

to describe the process of imprinting a geometric pattern from a mask onto a thin layer

of material, a resist, which is a radiation-sensitive polymer The resist is usually laiddown onto the substrate using a spin-casting technique (see Figure 4.10)

In spin-casting technique, a small volume of the resist is dropped onto the centre ofthe flat substrate, which is accelerated and spun at a constant low spin speed of about

2000 rpm to spread the resist uniformly The spin speed is then rapidly increased to itsfinal spin speed of about 5000 rpm, and this stage determines its final thickness of 1 to

2 um The thickness of the spun-on resist, dR, is determined by the viscosity 77 of the

2 Double-sided wafers are used if a back-etch is required to define a microstructure.

Figure 4.10 Apparatus used to cast a resist onto a substrate in preparation for optical lithography

resist and final spin speed v approximately according to

where fsc is the percentage solid content in solution The resist-coated wafer is then cured

by a soft-bake at a low temperature (80 to 100°C for 10 to 20 minutes) and a processmask applied for shadow or projection printing3 The mask is generally a reticule maskplate and comprises a glass plate coated with a light-blocking material, such as a thinchromium film, that has itself been patterned using a wet-etching process and a secondresist, but in this case the resist has been written on directly using a high-resolutionelectron-beam writer Then the mask and substrate are exposed to a radiation source,usually ultraviolet (UV) light, and the radiation is transmitted through the clear parts ofthe mask but blocked by the chromium coating The effect of the radiation depends on thetype of resist - positive or negative When a positive resist is exposed to the radiation,

it becomes soluble in the resist developer and dissolves leaving a resist pattern of thesame shape as that of the chromium film Conversely, the negative resist becomes lesssoluble when exposed to the radiation and so leaves the negative of the chromium coating.Negative resists are used more commonly as they yield better results Table 4.3 showssome commercially available resists for both optical and electron-beam lithography4.Figure 4.11 shows the lithographic patterning of a substrate with a negative resist andchrome mask plate (mask 1), and subsequent soft-baking and developing in chemicals,

to leave the resist over predefined parts of the oxide layer The resist is then hard-baked

3 Optical and other lithographic techniques are described later in Section 5.3.

4 These terms are defined later on under bipolar transistor characteristics.

Table 4.3 Some commercially available resists

TypeNegativeNegativeNegativePositiveNegativePositivePositive

Mask

Wafer

Exposing radiation Glass

Chromium (80 nm)

An image-forming system may occupy

a portion of this space

Resist Oxide or mulptiple layers of device Wafer substrate

Resist

Figure 4.11 Use of radiation and a mask plate to create windows in a resist layer through which

the oxide is etched and arsenic-doped to form buried n-regions in a p-type substrate The buried

regions are used to increase device performance

(110 to 130 °C for 10 to 20 minutes) and the oxide is selectively removed using either awet-etching or a dry-etching process

Table 4.4 shows the wet or liquid etchants commonly used to remove oxides and othermaterials during a standard process Dry etching is becoming increasingly popular, andthe details of different wet and dry etching processes, which are often referred to as

micromachining techniques, are described in this Chapter.

Next, arsenic is introduced into the exposed p-type silicon regions There are two

different techniques used: thermal predeposition and ion implantation

In thermal predeposition, a powder, liquid, or gas can be used as the source dopantmaterial for the predeposition process The solid solubility of the dopant in the material,predeposition time, and temperature determine how far the dopant diffuses into the wafer.For a constant source concentration Cs, the dopant concentration at distance x and at time

Table 4.4 Some wet etchants used in processing wafers for semiconductor devices

Material to etch Composition of etchant Etch rate Temperature

(nm/min) (°C) Thermal SiO2

KOH

50:10:2:3 Phosphoric acid/acetic acid/nitric acid/water

80-120 180-220 350-500 200-600

20-30 20-30 20-30 20-40

Silicon nitride Phosphoric acid 5-7.5 160-175

Table 4.5 Source materials for doping silicon substrates

Element \/D at Solid Compound

1100°C solubility at name (um 1150°C

Antimony trioxide Solid Arsenic trioxide Solid

Subcollector Closed tube or source furnace;

subcollector Phosphorus

p-type:

Boron

Arsine 0.329 1.4X102 1 Phosphoric

pentoxide Phosphoric oxychloride Phosphine Phosphoric oxychloride Silicon pyrophosphate Silicon

pyrophosphate 0.329 5 x lO20a Boron trioxide

Boron tribromide Diborane Boron nitride

Gas

Solid Liquid

Gas

Liquid Solid Solid Solid Liquid

Gas

Solid

Subcollector/emitter Emitters

Emitters Emitters Emitters Wafer source Wafer source Base/isolation Base/isolation Base/isolation Wafer source

a At 1250°C

t, C(x, t), is determined by the following equation:

where D is the diffusion coefficient.

Table 4.5 shows the different sources used to dope semiconductors After predeposition,there is a drive-in step in which the existing dopant is driven into the silicon and a

protective layer of oxide is regrown in an oxygen atmosphere In practice, the diffusion

coefficient D does vary itself with the level of doping, increasing somewhat linearly with

arsenic and quadratically with phosphorus As a result, calibrated charts, instead of asimple mathematical formula, are used to determine the doping profiles

In the second doping technique, namely, ion implantation, the dopant element is ionised,accelerated to a kinetic energy of several hundred keV, and driven into the substrate Thisalternative method is discussed in Section 2.5.2

After predeposition and drive-in steps, the oxide protection layer is stripped off using a

wet or dry etch to leave the n-regions defined in the p-type substrate An n-type epi-layer

of 4 to 6 um in thickness is grown on top of the substrate (see Section 4.2.3) to create the

buried n-type areas within the p-type substrate The buried n-layer is used to minimise both the collector series resistance of the vertical n-p-n transistor that is formed later and

the common-base (CB) current gain, F, of the parasitic p-n-p transistor formed by the collector and base of the lateral p-n-p transistor and the substrate However, the buried

n-regions can diffuse further into the epi-layer at elevated temperatures, and so caution

is required in any subsequent processing

The transistors need to be electrically separated from each other, and there are a number

of techniques with which to do this Common techniques used are oxide isolation, based

on local oxide isolation of silicon (LOCOS), junction isolation (JI) based on a deep borondope, or trench isolation, which is useful for minimising parasitic capacitance At thisstage, a second mask (mask 2) is used to define the regions into which boron is implantedand thus isolate one transistor from another (see Figure 4.12)

Then the deep n+-type contacts of the vertical n-p-n collector and lateral p-n-p base

are defined using a third mask in another patterning process, followed by an extrinsic

p-type implant for the base of the vertical n-p-n transistor and for both the emitter and collector of the lateral p-n-p transistor (mask 3) The relatively thick, highly doped

extrinsic layer is followed by a thinner, lighter doped intrinsic base implant (mask 4)

below the emitter in the vertical n-p-n transistor The lighter doping provides for a large

common-emitter (CE) current gain BF.

Next, the heavily doped n + contact to the emitter in the vertical n-p-n transistor

is implanted (mask 5) to complete the transistor structures Finally, the oxide layer ispatterned (mask 6) to form contact holes through to the transistor contacts and substrate,and then the metal interconnect (normally 100 to 300 nm of aluminum) is deposited either

by physical evaporation or by sputtering and is patterned (mask 7) to form the completed

IC Figure 4.13 shows the side view of two devices: the vertical n-p-n transistor and lateral p-n-p transistor.

In some cases, a passivation layer of SiO2 or some other material is deposited andpatterned (mask 8) to serve as a physical and chemical protective barrier over the circuit.This depends upon the proposed method of packaging of the die (see Section 4.4) andthe subsequent use The complete bipolar process described here is summarised inFigure 4.14

It could be simplified by fabricating, for example, a pure n-p-n bipolar process, and, in fact, most of the transistors in monolithic ICs are n-p-n structures However, although the characteristics of p-n-p transistors are generally inferior to an n-p-n transistor, as stated

in the preceding text, they are used as active devices in operational amplifiers, and as the

injector transistors in the IIL mentioned earlier Similarly, a substrate p-n-p transistor

Figure 4.12 Formation of an isolation region (p + ) in the substrate to separate devices electrically

in a bipolar process The isolation regions are used to enhance packing densities

Figure 4.13 A vertical n-p-n transistor and lateral p-n-p transistor formed by a standard bipolar

process

Figure 4.14 Standard bipolar process to make a vertical n-p-n transistor and lateral p-n-p

transistor

Top view Side view

Figure 4.15 Various kinds of diodes available from a bipolar process: (a) emitter-base; (b)

base-collector; and (c) epi-isolation

rather than a lateral p-n-p transistor could be fabricated by leaving out the buried n +

-layer The problem that arises then is that it restricts the possible circuit configurations(because the collector is connected to the substrate that gives parasitic problems) and,therefore, the process can no longer be regarded as standard

Various other components can also be formed using this bipolar process For example,Figure 4.15 shows three different types of diode that can be formed, namely, the emitter-base diode that has a low reverse breakdown voltage of 6 to 60 V and can be used as aZener diode; the base-collector diode that has a higher reverse breakdown voltage of 15

to 50 V; and the epi-isolation diode

Figure 4.16 shows five different types of resistor that can be formed: the base resistorwith a typical sheet resistance of 100 to 500 /sq, the pinched-base resistor with a typicalsheet resistance of 2000 to 10000 /sq, the emitter resistor with a typical sheet resistance

of 4 to 20 /sq, the epi-resistor with a sheet resistance that varies from 400 to 2000 /sq,and a pinched epi-resistor that has a higher sheet resistance than an epi-resistor of 500 to

2000 /sq and is often used in preference to the latter

Finally, different capacitors can be formed; Figure 4.17 shows both the dielectric itor, in which the thermal oxide or thinner emitter oxide is used as the dielectric, andthe junction capacitance, which is suitable when there is no requirement for low leakage

1

1 fit

1 1

Figure 4.16 Various kinds of resistors available from a bipolar process: (a) base resistor; (b)

pin-ched base resistor; (c) emitter resistor; (d) epi-resistor; and (e) pinpin-ched epi-resistor

currents or a constant capacitance In general, these components tend to have inferior trical properties compared with discrete devices that are fabricated by employing othertechnologies; therefore, extra care is required to design circuits using these components

elec-It is common to use discrete components as external reference capacitors and resistorstogether with an 1C to achieve the necessary performance

Top view

(a)

Side View Aluminium

of the bipolar transistor from the basic (e.g Sze 1985) through to an advanced ment of the device physics, the construction of sophisticated models (e.g Hart 1994),and bipolar circuitry Most of this material is outside the scope of this book, becausehere we are mainly interested in the technologies that are relevant to the integration

treat-of standard ICs with microtransducers and MEMS devices However, it is necessary toinclude some basic material on bipolar devices for three reasons: First, as a backgroundmaterial to the readers who are less familiar with electrical engineering topics and whowant to know more about the basic electrical properties of a junction diode and tran-sistor and the technical terms used, such as threshold voltage or current gain; second,

to serve as a reminder to other readers of the typical characteristics of a bipolar devicefor use when designing an IC Finally, and perhaps most important, to provide back-ground information on microelectronic devices that can be exploited directly, or within

an 1C, as a microtransducer or MEMS device For instance, a bipolar diode or bipolartransistor may be used to measure the ambient temperature (see Chapter 8) Therefore,for all these reasons, a brief discussion of the properties of the bipolar junction and FETs

Figure 4.18 shows (a) a schematic of the structure and (b) its symbol and implementation

in a simple direct current (DC) circuit The concentration of the donors and acceptors areshown in Figure 4.18(c)

In the absence of an external voltage V applied across the diode, there is a tendency

for acceptors in the p-type material to diffuse across into the n-type region driven by the difference in electrochemical potential caused by the high concentration of acceptors p p

in p-type region compared with that in the n-type region n p (i.e p p » n p ) Similarly, there is a tendency for the donors in the n-type material to move into the p-type material because of the mismatch in carrier concentration, namely n n >> p n Because no current

can flow across the junction without an external voltage, a depletion region that is free

of mobile charge carriers is formed This region is called the space charge region and

it is shown in Figure 4.18(c), where the region near the p-type material is left with a

net negative charge and the region near the n-type material is left with a net positive

charge Together, these form a dipole layer and hence a potential barrier of height Vd

(Figure 4.18(d)) that prevents the flow of majority carriers from one side to the other

The height of the potential barrier, which is also known as the diffusion potential or contact potential, is determined by the carrier concentrations

q P P

(4.9)

where T is the absolute temperature and q is the charge on an electron The diffusion

potential varies for different technologies and is about 0.5 to 0.8 V for silicon, 0.1 to0.2 V for germanium, and about 1.5 V for GaAs

(a)

p-type n-type

aia^i^fijggg;'^

(d)

Space-charge region

Figure 4.18 Schematic diagram of (a) a p-n junction diode; (b) equivalent symbol; (c)

space-charge region; (d) contact potential

The depletion region has an associated depletion or junction capacitance that is given by

of 0.5, that is, a plot of 1/C2 versus V would be a straight line Typical characteristics

of a silicon junction diode with the conductivity of the p-type and n-type regions being

100 S/cm and 1 S/cm, respectively, are a space charge layer / of 0.5 urn at V = 0 and 1.2 um at V = —5.0 (reverse-biased) and a junction capacitance of 23 pF at 0 V and 8.3 pF at —5.0 V The nonlinear C- V characteristic of a junction diode, together with

its significant leakage current, makes its use better suited to digital rather than analoguecircuitry

When the junction is forward-biased (i.e V > 0), the height of the potential barrier

is reduced, and more holes flow through diffusion from the p-type region to the n-type region and more electrons flow through diffusion from the n-type region to the p-type

region In a simple diffusion model, in which the transition width / is much smallerthan the diffusion length, the recombination in the depletion region can be ignored andthen the net current flow is determined from the continuity equation with an exponentialprobability of carriers crossing the barrier:

where J is the current density, D denotes the diffusion coefficient of the carrier and L is its diffusion length The V-I characteristic of a p-n junction diode is usually rewritten

in the slightly more general form of

where is an empirical scaling factor and would be 1.0 for an ideal diode Figure 4.19

shows the typical /- V characteristic of a discrete silicon p-n diode at room temperature.

The scaling factor A is about 0.58 here5 and the saturation current IS is about 1 nA Thesimple theory (Equation (4.13)) gives a saturation current of about 1 fA, but recombi-nation effects, thermal generation, and series resistance effects increase it by 6 orders

of magnitude Note that the saturation current is itself very temperature-dependent and

increases by approximately 20 percent per °C Therefore, in the reverse-bias regime, the shift in the I - V characteristic of the diode could be used to create a nonlinear temperature

sensor

The basic theory ignores the reverse-bias breakdown of the diode, and this is shown

in Figure 4.19 as occurring around —60 V because of avalanche breakdown6 In a zenerdiode, the breakdown voltage is reduced to below — 10 V by higher doping levels andcan be used as a reference voltage

In the forward-bias region, the diode appears to switch on at a certain voltage and thenbecomes fully conducting This voltage VT will be referred to here as the threshold voltage but is also called the cut-in or turn-on voltage The threshold voltage is determined by

fitting a line to the high voltage values and extrapolating to the zero current axis, as

/(rnA)

10

Breakdown region

Threshold voltage VT

-l.0 uA

(Note the scale change

in the reverse characteristics) 2.0

Reverse bias Forward bias

Figure 4.19 Typical I-V characteristic of a silicon p-n junction diode showing the forward- and

reverse-bias regions

5 In normal operation is 1.0, but at low and very high levels of injection, it approaches 0.5.

6 Diodes can be designed in silicon to have a breakdown voltage of up to 6.5 kV.

shown in Figure 4.19 The threshold voltage VT of a typical silicon junction diode is0.6 V and has a linear temperature coefficient of about —1.7 mV/°C at 20 °C Therefore,operating a diode at constant current in the forward-bias regime produces a simple andlinear temperature sensor.

The BJT consists of either a p-type region sandwiched between two n-type regions

for an n-p-n transistor or an n-type region sandwiched between two p-type regions for

a p-n-p transistor; hence, it could be regarded as an n-p and p-n diode back to back.

In the last section, we saw how a bipolar process can be used to fabricate a vertical

n-p-n transistor and lateral p-n-p transistor for an IC All the transistor voltages and currents are defined in Figure 4.20 for both the n-p-n and p-n-p transistors Bipolar

transistors are basically current-controlled devices in contrast to MOS transistors that arevoltage-controlled devices; therefore, we need to consider the currents in the transistor tocharacterise it

A bipolar transistor can be configured in three different ways (see Figure 4.21 for

n-p-n): (a) the CE, in which the emitter is the common terminal to both the base input voltage

VBE and the collector output voltage VCE; (b) the CB, in which the base is the commonterminal to both the emitter input voltage VEB and the collector output voltage VCB; and (c)the common-collector (CC) configuration in which the collector is the common terminal

to both the base input voltage VBC and the emitter output voltage VEC- Bipolar transistorsare normally operated in the CE configuration because it usually provides the largestpower gain

Figure 4.21 The three possible configurations of an n-p-n transistor: (a) common-emitter; (b)

common-base; and (c) common-collector

In the normal mode of operation7 of an n-p-n transistor in the CE configuration, the

emitter-base junction is forward-biased (i.e VBE > 0) and the collector-base junction isreverse-biased (i.e VBC < 0) Therefore, the collector current Ic consists of two terms,

the main term being a fraction a F of the emitter current and the other being the reverse

saturation current I Co of the collector-base junction diode; hence

From Kirchoff's current law, the collector current can be related to the base current by

ap=-±orftp=-± (4.19)

Ideally, ap takes a value close to unity and ftp takes a value that is large.

The typical measured input characteristic IB — VBE and output characteristic Ic — VCE

of an n-p-n transistor are shown in Figure 4.22 The input characteristic is that of a diode

with a threshold voltage that is about 0.7 V corresponding to a silicon transistor Theoutput characteristic shows all the possible regions of operation for the transistor

As mentioned in the preceding text, the transistor is normally operated in the active region (VBE > 0; VBC < 0) where the forward current parameters of aF and ftp

forward-apply In this region, the output characteristic may be described by a simple model(excluding the breakdown region) in which the collector current is given by