This thesis investigates the fabrication and characterization of p-type CuOx based thin-film transistors TFTs using DC magnetron sputtering.. Aiming to advance high-performance p-type ox
OVERVIEW
The Rise of TFT Technology
The concept of thin-film transistors (TFTs) originated with J.E Lilienfeld and O Heil, who filed patents between 1925 and 1930, laying the groundwork for modern TFT technology However, the first functional TFT did not emerge until 1962 by P.K Weimer, constrained by the era’s limited semiconductor material knowledge and vacuum technology This early device used a thin film of polycrystalline cadmium sulfide (CdS) as its active layer, while researchers also explored cadmium selenide (CdSe) for its potentially higher field-effect mobility In 1970, the first TFT-LCD driven by CdSe TFTs was demonstrated, but mass production on large-area substrates faced significant challenges in maintaining semiconductor properties and ensuring device reliability.
In 1973, P G LeComber and W E Spear demonstrated the first practical thin-film transistor (TFT) using a hydrogenated amorphous silicon (a-Si:H) active layer deposited by plasma-enhanced chemical vapor deposition (PECVD) The simple fabrication process, low cost, and uniform properties of a-Si:H TFTs made them highly suitable for commercial large-area displays, especially active-matrix LCDs (AM-LCDs) and active-matrix OLEDs (AM-OLEDs).
As anticipated, amorphous silicon thin-film transistors (a-Si:H TFTs) rose to become a driving force in the AM-LCD market during the mid-1980s and proved essential for large-area display applications With increasing demand for display panels and progress in mass production, the development of TFT technology has continued to attract intense attention from both industry and research, fueling ongoing advancements in large-area displays and AM-LCDs.
Figure 1.1: Main landmarks achieved with TFTs [9]
Opportunities for oxide-semiconductor thin film electronics
While a-Si:H TFT-LCDs have achieved commercial success, their field-effect mobility is typically below 1 cm²/(Vãs), which limits their suitability for high -speed or high-current applications [10] This limitation has driven the demand for alternative TFT technologies, particularly for applications such as displays, sensors, costly disposable electronics, portable devices, low-consumable power systems, and paper-based electronics, which require flexible and transparent TFTs capable of the operation at low voltages Fortunately, oxide semiconductor TFTs have gained significant attention as a promising alternative to a-Si:H TFTs This is largely because of their high field-effect mobility and excellent optical transparency These attributes make oxide -based TFTs likely to play a crucial role in the development of next-generation TFT devices
Oxide semiconductors, particularly metal oxides, offer several advantages for thin-film transistors (TFTs): low-temperature processing enables fabrication on large-area substrates, and these materials deliver high carrier mobility in the range of about 1 to 20 cm²/(V·s).
n-type oxides have a conduction band formed by overlapping s-orbitals, which yields high electron mobility even in amorphous structures and enables uniform large-area deposition This attribute has propelled the display industry forward, with n-type oxide semiconductors like a-IGZO used in display backplanes Moreover, the wide bandgap of amorphous n-type oxides, together with their optical transparency, high breakdown voltage, and low leakage current, has spurred research into new applications such as transparent electronics and BEOL memory and power-control devices.
Due to the difficulty of achieving p-type doping in oxide semiconductors, most devices currently employ n-type thin-film transistors (TFTs) with unipolar operation P-type transistors are still in the early research stage, while n-type TFTs have been industrialized because of low-temperature processing, cost-effectiveness, and well-established fabrication techniques The main challenge in advancing thin-film semiconductor technology is the lack of high-performance p-type semiconductors that can match the performance of n-type materials.
N-type TFTs with unipolar characteristics are predominantly used in current devices due to the difficulty of achieving p-type doping in oxide semiconductors While efforts to develop p-type transistors have recently begun (e.g., Figure 1.2), their advancement is still at the experimental stage In contrast, n-type TFTs are well- established in the industry due to their low-temperature processing, cost-effectiveness, and technological maturity The lack of p-type thin-film semiconductors with comparable performance to n-type materials represents a significant barrier to advancing thin-film semiconductor technology further
Figure 1.2: Proportion of n-type oxides and p-type oxides in different materials
Oxide Semiconductor Materials
Oxide semiconductor materials have been extensively studied as channel layers for thin-film transistor (TFT) devices, with results demonstrating their potential in thin-film electronics Representative outcomes highlight the viability of oxide semiconductors as TFT channel materials In 2017, a Taiwanese research group reported ZnO as the semiconductor channel material, with the findings illustrated in Figure 1.3 The output characteristics show the drain current (ID) increasing with higher positive gate voltage, which is consistent with the behavior of an n-type semiconductor.
Figure 1.3: Output characteristics of TFT using ZnO as channel [24]
Beyond n-type semiconductors like ZnO, researchers have also explored p-type oxide semiconductors, notably CuOx In 2010, a Portuguese research group published results using CuOx as the channel material in thin-film transistors (TFTs), as shown in Figure 1.4 The data indicate that the drain current (ID) increases with more negative gate voltage, aligning with the characteristic behavior of a p-type semiconductor.
Figure 1.4: Output characteristics of TFT using Cu 2 O as channel [25]
Across Figures 1.3 and 1.4, the transfer characteristics reveal that CuOx-based thin-film transistors require a larger magnitude of drain–source voltage (VDS) to reach current saturation (ID) than ZnO-based TFTs This indicates distinct charge-transport behavior and higher operating voltage requirements for CuOx devices compared with ZnO TFTs.
There are seven key requirements for the integration of n-type and p-type oxide semiconductors in thin-film transistor (TFT) applications Consequently, the field-effect behavior of the p-type CuOx semiconductor remains an area requiring further investigation Our research group has, however, developed several copper oxide–based devices, such as infrared sensors and memristors The integration of these devices with the field-effect characteristics of TFTs opens the possibility of high-density integration on a single chip Therefore, this study launches a new research direction within our group, focusing on the field-effect behavior of p-type CuOx semiconductors fabricated by the sputtering method.
Research objectives
Numerous research groups have focused on optimizing the active layer of thin-film transistors (TFTs) and have explored various deposition techniques for copper oxide thin films, including sputtering and thermal oxidation Among these methods, sputtering is particularly advantageous for fabricating copper oxide TFTs due to its ability to produce high-quality films with precise thickness control and uniformity over large areas Accordingly, this thesis centers on fabricating copper oxide (CuOx) as the active layer in TFTs, with the aim of developing p-type copper oxide thin films deposited at room temperature from a metallic copper (Cu) target using reactive magnetron sputtering Additionally, several process modifications are introduced to optimize the properties and performance of the CuOx channel in TFTs To evaluate these improvements, I–V measurements are conducted to assess the electrical performance of CuOx-based TFTs.
TECHNICAL BACKGROUND
Thin film transistors
Thin-film transistors (TFTs) have attracted substantial attention in semiconductor research due to their simple architecture and crucial role in controlling individual pixels in modern display technologies They are fundamental to flat-panel displays, including liquid-crystal displays (LCDs) and active-matrix organic light-emitting diode (AMOLED) panels, where TFTs act as the active switching elements in the pixel matrix True to their name, TFTs are constructed from ultrathin layers, typically only a few hundred nanometers thick, and most devices operate on the principles of field-effect transistors.
Fundamentally, a thin-film transistor is built from three main components: the semiconducting layer, the electrodes (source, drain, and gate), and an insulating dielectric layer, as shown in Figure 2.1 The dielectric electrically isolates the gate electrode from the semiconductor, enabling effective gate control The source and drain electrodes contact the semiconductor directly, defining the transistor’s physical dimensions and providing the path for current flow.
Figure 2.1: Basic thin film transistor structure [8]
The spatial arrangement of transistor components significantly influences both device performance and fabrication complexity Thin-film transistors (TFTs) are typically categorized into two structural types: coplanar and staggered This classification is based on how the source and drain electrodes relate to the gate dielectric and the semiconductor channel As shown in Figure 2.2 [12], the coplanar configuration places the source, drain, gate, and channel on the same plane, enabling a compact layout, whereas the staggered arrangement offsets the electrodes to create a vertical separation that can alter electric field distribution and fabrication steps.
Nine designs place both the source/drain electrodes and the dielectric gate on the same side of the active layer, while staggered designs position them on opposite sides In addition, the gate electrode location creates bottom-gate or top-gate configurations, depending on whether the gate sits below or above the active layer.
Figure 2.2: Illustration of TFT structures: (staggered) bottom-gate structure and top-gate structure, coplanar bottom-gate structure and top-gate structure
The choice of a TFT architecture is driven by the materials used and the intended operating conditions Top-gate configurations are typically favored when the semiconductor requires high-temperature processing that could compromise dielectric layers or source/drain contacts TG structures also support higher-quality crystalline semiconductors by enabling better lattice alignment with single-crystal substrates In contrast, bottom-gate designs are more prevalent in practice due to simpler fabrication steps and the ready availability of commercial ITO/glass substrates that come with pre-patterned gate electrodes.
A substantial carrier concentration within the channel region is essential for enabling a strong operating current in a TFT This is typically achieved by inducing
Carrier accumulation occurs at the interface between the semiconductor and the insulator In the off-state, a depletion region forms at this interface, which limits current flow To better visualize the mechanisms of carrier accumulation and depletion, Figure 2.3 displays energy band diagrams of an n-type TFT under three different gate voltage conditions.
Figure 2.3: Energy band diagrams illustrating the behavior at the semiconductor/gate insulator interface under different applied gate voltages [23 ]
Figure 2.3 shows energy band diagrams illustrating how the semiconductor/insulator interface responds to gate bias In panel (a), the bands are flat, signaling equilibrium with no external gate voltage When a negative gate bias is applied, an electric field develops directed toward the gate electrode, repelling electrons from the interface and causing upward band bending due to the negative surface potential This creates a depletion region, increases resistivity, and effectively switches the device off by preventing current flow through the semiconductor.
In contrast, Figure 2.3(c) demonstrates the effect of a positive gate bias on the device The applied voltage draws electrons toward the semiconductor–insulator interface, increasing electron concentration and promoting carrier accumulation As a result, the energy bands bend downward under the positive surface potential, forming a conductive channel that turns the device on The threshold voltage (VT) is the minimum gate voltage required to initiate electron accumulation and channel formation; when the gate voltage is below VT, the conductive channel does not form and the device remains off.
11 the resulting drain current is referred to as the threshold current, representing the device's subthreshold operation
n-type TFTs operate in two principal modes: enhancement mode, featuring a positive threshold voltage, and depletion mode, with a negative threshold voltage Enhancement mode is preferred for energy efficiency since no extra bias is needed to turn off the TFT Depending on the applied gate and drain voltages, TFTs can function in either the linear region or the saturation region, as shown in Figure 2.4 In the off state (Figure 2.4a), the gate voltage remains below the threshold voltage, preventing carrier accumulation at the semiconductor–insulator interface, which results in a low carrier concentration and no conductive channel formation, leading to minimal drain current.
In the MOSFET’s linear region, the gate voltage exceeds the threshold voltage while the drain voltage remains small relative to (VG – VT) (VD ≪ (VG – VT)) This condition enables uniform carrier accumulation that forms a conductive channel between the source and drain (represented by the gray region), causing the drain current to increase linearly with the drain voltage as carriers flow from the source to the drain.
In contrast, Figure 2.4(c) illustrates the saturation region, where the gate voltage remains above the threshold voltage, but the drain voltage is sufficiently high (VD > (VG
– VT)) Under these conditions, the conductive channel near the drain electrode experiences pinch-off, leading to drain current saturation, making it largely independent of the drain voltage
Figure 2.4: Illustration of TFTs operating under different voltage bias conditions: a) cut-off region, b) linear region, c) saturation region [23]
The electrical performance of a thin-film transistor (TFT) is defined by several critical parameters—on/off current ratio, threshold voltage, turn-on voltage, field-effect mobility, and subthreshold swing—that are typically extracted from the device’s output and transfer curves Figures 2.5 and 2.6 show representative output and transfer characteristics of a thin-film transistor, respectively.
The output characteristic illustrates the relationship between drain current and drain voltage at fixed gate voltages As shown in Figure 2.5, the drain current–voltage curve comprises two distinct regions: linear (ohmic) and saturation In the linear region, the drain current increases proportional to the drain voltage, reflecting a direct I–V relationship As the drain voltage continues to rise, the device transitions into the saturation region, where the drain current levels off and reaches a steady value Understanding these regions is essential for accurately modeling MOSFET behavior and designing analog circuits.
To facilitate the analysis of TFT performance and enable a quick assessment of device efficiency, certain evaluation parameters are established, as shown in Figure 2.6
- The on-off ratio (Ion/Ioff): is the ratio of the maximum to minimum ID A higher
"on" current improves driving capability, while a lower "off" current reduces leakage Therefore, a higher on-off ratio is preferred
- The threshold voltage (VT): refers to the gate-to-source voltage (VGS) at which a significant amount of charge starts accumulating near the dielectric/semiconductor interface
- Turn-on voltage (Von): corresponds to the VGS at which ID starts increasing
Subthreshold swing (S.S) is a key parameter that indicates a transistor's switching efficiency It is defined as the inverse of the maximum slope of the transfer characteristic, and it represents the gate-source voltage (V_GS) required to increase the drain current (I_DS) by one order of magnitude in the subthreshold region.
P-type copper oxide semiconductor material
Copper oxide exists in two major oxidation states, cuprous oxide (Cu2O) and cupric oxide (CuO) Cu2O crystallizes in a cubic structure formed by two interpenetrating diamond-like lattices of copper and oxygen, with copper atoms located between oxygen layers arranged in a body-centered cubic configuration; each oxygen atom is tetrahedrally coordinated by copper and each copper atom is bonded to two oxygen atoms By contrast, CuO exhibits a monoclinic crystal structure known as tenorite, where Cu2+ ions form planar bonds with four oxygen atoms within the space group C2/c The valence-band maximum in these oxides arises from the hybridization of Cu 3d10 and O 2p6 orbitals, because these energy levels are close, enabling strong covalent Cu–O bonding This bonding leads to more delocalized hole transport and lower hole effective masses, thereby enhancing both field-effect mobility and hole mobility.
Figure 2.7: Cu 2 O crystal structure and (b) schematic illustration of valence band formation in Cu 2 O [9]
An Indian research group led by M R Shijeesh and M K Jayaraj fabricated and investigated thin-film transistors (TFTs) using Cu2O and CuO as the semiconductor materials They report optical bandgaps of 2.1–2.6 eV for Cu2O and 1.3–2.1 eV for CuO, with both materials identified as p-type oxides The study finds that Cu2O-based TFTs exhibit a higher field-effect mobility of 5.20 × 10^-4 cm^2 V^-1 s^-1 compared with 2.33 × 10^-4 cm^2 V^-1 s^-1 for CuO-based TFTs, a result that aligns with the higher drain current observed in Cu2O devices Overall, the results highlight Cu2O as the more favorable semiconductor for TFT performance in this comparison.
CuO thin films exhibit a higher subgap state density than Cu2O thin films, and these subgap states act as traps for charge carriers that hinder charge transport and reduce mobility in CuO films Cu2O thin films, on the other hand, generally possess higher crystallinity, contributing to better electrical performance Post-annealing markedly increases the roughness of Cu2O films compared with CuO films, signaling improved crystallinity Therefore, Cu2O is a more suitable channel material for thin-film transistors than CuO.
Buoyed by these advantages, Cu2O has been investigated using a range of deposition methods Among the approaches, DC/RF magnetron sputtering stands out as one of the most promising thin-film deposition techniques, owing to its cost-effective process and its capability for large-area deposition, which makes it highly suitable for manufacturing.
EXPERIMENT
Substrate preparation
The microfabrication process begins with the preparation and cleaning of the silicon (100) wafer using as a substrate as shown in Figure 3.1
Figure 3.1: Silicon (100) wafer as substrate
During the silicon wafer cleaning process, inorganic compounds, organic substances, and impurities remaining on the wafer surface after production are effectively removed The entire cleaning operation is carried out inside a fume hood located in the cleanroom, as illustrated in Figure 3.2a.
Figure 3.2: Tools and equipment used for cleaning the wafer: a) fume hood, b) round- glass tray, and c) an ultrasonic vibration
During wafer cleaning, the wafer is placed in a 3-liter round glass tray (Figure 3.2b) and fully submerged in acetone to remove surface impurities and organic residues To boost cleaning efficiency, the wafer is subjected to ultrasonic vibration in the acetone bath for 10 minutes (Figure 3.2c) After ultrasonication, the acetone is drained and replaced with isopropyl alcohol (IPA) to rinse away any remaining acetone, completing the cleaning sequence.
The wafer is transferred to a 5-liter overflow tank filled with deionized (DI) water, and DI water is continuously added to the overflow tank until the rinsing solution’s conductivity falls below 0.5 µS/cm, at which point the rinsing process is complete Next, the wafer is immersed in a piranha solution, a strong acidic mixture of concentrated sulfuric acid (H2SO4) and 30% hydrogen peroxide (H2O2) in a 3:1 ratio.
2 hours This step effectively removes all remaining organic and inorganic compou nds from the wafer surface due to the high oxidizing properties of the solution
After the piranha bath, the wafer undergoes another DI water overflow rinse and is then dried using a spin coater operating at 4000 rpm The entire cleaning and drying process is summarized in Table 3.1, which outlines steps a, b, and c.
Table 3.1: The steps for cleaning the wafer surface
1 Ultra vibration in the acetone solution 10
2 Rinsed off acetone by isopropyl alcohol
3 Overflow rinse by DI water 5
5 Overflow rinse by DI water 5
The cleaned silicon wafer is placed in a wet oxidation furnace (Figure 3.3a) to form a 200 nm thick insulating SiO2 layer on the underlying silicon substrate, a standard step in MEMS fabrication Mounted on a sample holder, the wafer is positioned vertically and inserted into the reaction chamber, where a continuous nitrogen purge expels any flammable gases at high temperature The wafer is gradually heated to 950°C over one hour, and once the chamber temperature stabilizes, oxygen and water vapor are introduced to drive the wet oxidation process The resulting silicon dioxide layer is 200 nm thick, as shown in Figure 3.3b.
Figure 3.3: Wet oxidation system for silicon wafers: a) wet oxidation furnace system, b) oxidation silicon wafer.
TFT microfabrication process
Microfabrication is a sequence of precise steps used to build the target device structure Three photomasks, as shown in Figure 3.4, define the intricate TFT features through photolithography Thin-film deposition for both the conductive layers and the semiconductor sensing layer is performed by magnetron sputtering Silicon nitride (Si3N4), used as the insulating material for the gate electrode, is deposited by plasma-enhanced chemical vapor deposition (PECVD) and then patterned with reactive ion etching (RIE) to realize the desired geometry.
Figure 3.4: Three photomasks were used to fabricate thin film transistors: mask 1 for source/drain electrodes, mask 2 for channel layer and mask 3 for gate electrode
Figure 3.5: Illustration of full TFT fabrication process
Figure 3.5 illustrates a sequential fabrication workflow for the device To begin, a thin molybdenum (Mo) layer is deposited onto a prepared SiO2/Si wafer by magnetron sputtering to serve as the electrode material (Figure 3.5a) Next, photolithography with Mask 1 defines the source (S) and drain (D) electrodes: a photoresist layer is spun on, precisely aligned, and patterned to establish the S and D regions (Figure 3.5b) The electrodes are then shaped by wet etching in an acidic solution, and any remaining photoresist is removed with acetone (Figures 3.5c and 3.5d).
Next, a lift-off technique is employed to form the channel connecting the S and
D electrodes This involves applying a photoresist, aligning Mask 2 during i) j) k)
Photolithography is used to define the desired channel pattern (Figure 3.5e) A thin layer of CuOx is deposited as the semiconductor material by sputtering (Figure 3.5f) Excess photoresist and CuOx are subsequently removed with acetone, unveiling the completed patterned channels (Figure 3.5g).
A silicon nitride (Si3N4) dielectric layer is deposited across the wafer by plasma-enhanced chemical vapor deposition (PECVD) to serve as the insulating layer for the gate electrode To define the gate, a lift-off process is performed: a photoresist layer is applied and Mask 3 is aligned during photolithography to pattern the gate electrode A Mo layer is then deposited over the gate electrode region, and the excess photoresist is stripped using acetone, completing the gate electrode fabrication.
To expose the source and drain pads and enable reliable electrical connections, the Si3N4 dielectric layer is selectively removed by plasma dry etching (Figure 3.5l) The wafer is then cleaned with nitrogen gas to remove residual contaminants, and the fabricated structure is inspected to verify process quality and ensure device integrity.
Fabrication method
This section outlines the TFT fabrication workflow, detailing the core methods used to build thin‑film transistor devices It covers thin‑film deposition techniques such as sputtering and PECVD, explains photolithography for precise patterning, and describes removal and transfer steps including wet etching and lift‑off, along with other complementary processes used in device fabrication Together, these methods define the material layers, pattern geometries, and interfaces that drive device performance, reliability, and yield.
Sputtering is a physical vapor deposition process in which atoms are ejected from a solid target’s surface when it is bombarded by charged particles Thin films form as these ejected atoms are transferred from the target to a substrate In this process, a beam of gas ions bombards the target material, ejecting atoms that are propelled toward the substrate by their acquired kinetic energy, where they are deposited to create a thin film.
Figure 3.6: Principle of sputtering process
Thin films of conductive molybdenum and metal oxide semiconductors (CuOx) were deposited using the SYSKEY magnetron sputtering system The SYSKEY platform houses four plasma sources feeding four magnetron guns, consisting of two radio frequency (RF) AC sources and two direct current (DC) sources RF sputtering, typically used for ceramic or dielectric materials such as SiO2 and Si3N4, prevents charge build-up on the target surface caused by plasma ion bombardment, thereby avoiding arcing and ensuring fabrication quality Conversely, DC sputtering is cost-effective and ideal for metallic or other highly conductive materials.
Figure 3.7: Illustration of Syskey sputtering system with 4 magnetron guns
The process begins with placing the sample on a holder above the deposition chamber, and the system uses two pumps (primary and secondary) to evacuate the chamber to below 5×10^-6 torr Plasma-generating gases are then introduced and maintained at 7.5×10^-3 torr using mass-flow controllers, after which the Mo electrode deposition is performed with the wafer rotating at 10 rpm, the substrate heated to 300°C by halogen lamps, Argon introduced at 20 sccm, and the Mo target sputtered at 100 W DC for 20 minutes For the copper oxide semiconductor CuOx layer, a gas mixture of Ar:O2 in either 15:5 or 14:6 flow ratios is used, the Cu target is sputtered at 50 W DC for 30 minutes, and all sputtering parameters for each fabrication step are summarized in Table 3.2.
Table 3.2: Sputtering parameters of each fabrication step
Gas flow ratio of Ar-O 2
Photolithography is a process used in microfabrication to shape single -layer or multi-layer thin films This method employs a polymer material capable of changing its properties upon absorbing light, commonly referred to as photoresist To pattern thin film structures, photolithography typically uses two different techniques: lift off and etching (Figure 3.8)
Both lift-off and etching are fundamental microfabrication patterning techniques In the lift-off approach, a resist is applied and patterned to define the desired design, followed by the deposition of a material layer; after deposition, the resist is removed, carrying away the overlying portions of the deposited film to leave the intended material patterns In the etching approach, a layer is deposited first, then a resist is formed and patterned to act as a masking layer that protects the underlying patterned regions during etching; the unprotected areas are etched away, and finally the remaining resist above the patterned layer is stripped with an acetone solution.
Etching starts with the deposition of the initial layer, followed by applying and patterning a photoresist that serves as a masking layer to protect the intended areas during the etching process Any material not covered by the resist is etched away, and the resist is finally stripped from the patterned layer using an acetone solution to reveal the final pattern.
Figure 3.8: Lift off (left) and etching (right) technique
In this thesis, both lift off and etching techniques will be used to fabricate the TFT structure The photolithography process is performed three times using three different photomasks
During the photolithography-based wet-etching step, mask 1 is used to pattern the source and drain electrodes on a molybdenum thin film deposited by sputtering A positive photoresist (AZ-1505) is spin-coated onto the substrate to a thickness of 0.5 μm at 4000 rpm for 35 s, followed by soft-baking at 110 °C for 60 s to remove solvent and improve resist adhesion (Figure 3.9) The sample is then exposed to UV light through photomask 1 in a photolithography system (Figure 3.10) with an exposure time of 1.2 s and a UV intensity of 22 mW/cm², maintaining a 4 μm gap between the substrate and the mask After exposure, development in a 2.5% tetramethylammonium hydroxide (TMAH) solution for 8 s defines the desired pattern, and the patterned features are stabilized by heating the sample at 110 °C for 120 s The sample is subsequently prepared for the next fabrication step.
A holder, often made of Teflon, securely holds the sample during the etching process to ensure uniform exposure to the solution The sample is etched in an acid bath consisting of H3PO4, HNO3, deionized water (DI), and CH3COOH in a 40:15:30:9 ratio (Figure 3.11) Afterward, the remaining photoresist is removed using an acetone solution Finally, the sample is rinsed with DI water to dilute the acetone, then placed on a spin coater for drying and subsequently heated on a hot plate.
Figure 3.9: The spin coater (left) and hot plate (right) in the photolithography process
Figure 3.10: OAI806MPA photolithography system in cleanroom
Figure 3.11: Teflon-made sample holder (left) and acid mixture bath (right)
The lift-off technique in photolithography is employed to pattern CuOx channels and gate electrodes using masks 2 and 3 A positive photoresist, AZ ECI-3012, is spin-coated to a thickness of 1.5 µm at 4000 rpm and baked at 100°C for 60 seconds to evaporate the solvent and improve adhesion The sample is then UV-exposed through the photomask for 16 seconds with a 4 µm gap between the substrate and the mask After exposure, the resist is developed in 2.5% TMAH (tetramethylammonium hydroxide) solution for 35 seconds to define the pattern Following patterning, a thin film of the desired material is deposited The sample is subsequently immersed in acetone to lift off the photoresist along with the overlying material, revealing the patterned CuOx channel and gate structures Finally, the sample is rinsed with deionized water, dried, and thermally treated on a hot plate.
3.3.3 Plasma enhanced chemical vapor deposition (PECVD)
Silicon nitride (Si3N4) is of significant interest in microelectronics due to its exceptional chemical stability and mechanical strength, making it an ideal insulating layer and protective coating for microelectronic devices In this thesis, Si3N4 thin films are deposited by plasma-enhanced chemical vapor deposition (PECVD) to serve as the insulating layer between the channel and the gate, as shown in Figure 3.12.
Figure 3.12: PECVD system in the cleanroom
To begin the process, the sample is placed into a vacuum chamber that is cleaned and evacuated to a pressure below 5×10⁻ 6 mbar, as shown in Figure 3.13 To produce
Si3N4 thin films are deposited by introducing precursor gases into the chamber—silane (SiH4), ammonia (NH3), and argon (Ar)—at flow rates of 2:32:101 sccm, with the chamber pressure held at about 0.3 torr Two electrodes placed on the top and bottom apply suitable power to ionize the gases, driving plasma chemistry and enhancing surface reactions for silicon nitride formation In this plasma-enhanced chemical vapor deposition (PECVD) process, silicon nitride is produced according to the balanced reaction: 3 SiH4 + 4 NH3 → Si3N4 + 12 H2.
Argon, while not part of the silicon nitride thin-film formation, is introduced into the deposition chamber to minimize the collision of highly reactive silicon ions that can create silicon dust on the substrate surface The process is conducted with the substrate temperature set to 179 °C and the RF power at 7 W.
30 minutes The resulting thin film has a thickness of approximately 60 nm.
Figure 3.13: Illustrated of PECVD chamber
Reactive ion etching (or dry etching) is a chemical etching method that uses etching gases and plasma to etch materials Since the Si3N4 dielectric thin film has been fully deposited on the substrate surface and covers the source and drain region, ion etching is carried out to remove the Si3N4 layer in this region and expose the electrode pads The precursor gas used for etching is sulfur hexafluoride (SF6), introduced to etch the Si3N4 material The Si3N4 part is dry etched by using the PC2 chamber of the PECVD system as shown above in Figure 3.14 The sample is placed into the vacuum chamber, which is cleaned and evacuated to a pressure below 5x10^-6 mbar as shown in Figure 23 SF6 gas is then introduced into the chamber at a flow rate of 50 sccm The etching pressure is set at 0.03 Torr, and the RF power is applied at 250 W for etching. -**Sponsor**Looking to optimize your article on reactive ion etching for SEO? Focus on the key sentences describing the process, like how SF6 gas is used to etch the Si3N4 layer in the source and drain regions, as well as the importance of the vacuum chamber and gas flow rate Consider also expanding on the benefits of ETFs for diversification and risk mitigation—just like refining your content, diversifying your investments can lead to better outcomes; explore options with [Freedom24 ETF - English](https://pollinations.ai/redirect-nexad/AM37UKJc?user_id=229098989) and see how their wide selection of ETFs can help you diversify With Freedom24, you can access thousands of European and global ETFs with transparent fees and expert analysis Invest in ETFs with Freedom24!
Characterization method
Seeing micro-scale features in thin-film transistor (TFT) devices with the naked eye is impractical, so an optical microscope is used to examine samples after photolithography and etching, as shown in Figure 3.15 Equipped with a MU300 camera and integrated Amscope software, the microscope facilitates easy observation, precise dimensional measurements, and image capture of fabrication details, illustrated in Figure 3.16 The instrument features three objective lenses—5X, 10X, and 50X—allowing accurate assessment of small features and sample dimensions Beyond measuring size and capturing images, it is also employed to evaluate the cleanliness of fabricated films and the surface quality of the deposited layers.
Figure 3.15: Optical microscope in cleanroom
Figure 3.16: Amscope software connecting to MU300 camera to capture the microscope image
In this study, the I-V characteristics of TFTs are measured using an Ossila X200 source measure unit connected to a Cascade MPS150 probe station (Figure 3.17), with the measurement setup shown in Figure 3.18
Figure 3.17: Ossila SMU connected to a probe station
Figure 3.18: Schematic of I-V characteristics measurement setup
Figure 3.19: Probe Station Configuration for TFT Characterization
Electrical characterization of the fabricated thin-film transistors (TFTs) is performed using a probe station and micro-probes to ensure precise measurements First, the TFT sample is positioned on the probe station, and micro-probes are connected to the gate, source, and drain electrodes, as illustrated in Figure 3.19, where three micro-probes contact the S/D/G electrodes on the sample A drain-source voltage (Vds) is applied, ranging from -10 V to 10 V, while the drain current (Id) is controlled within a defined measurement range.
Using the Ossila system, the gate voltage is applied while the drain current is measured, and this process is repeated across several gate voltages to generate the I-V characteristics of the TFTs The collected data are analyzed on a computer with Ossila software, as shown in Figure 3.20, providing precise measurements and a comprehensive analysis of the TFTs' electrical properties.
RESULTS AND DISCUSSION
Fabrication of CuO x – based TFTs
This section presents fabrication process results that confirm the successful completion of a wafer containing TFT chips using CuOx as the channel material Microscope images captured at each fabrication step illustrate the TFT structure and the progressive build-up of the device, validating the sequence from deposition to patterning Figure 4.1 shows the wafer after sputtering a highly uniform thin film of molybdenum, providing a reliable electrode foundation for subsequent CuOx channel integration.
Figure 4.1: Wafer after sputtering the Mo thin film
Subsequently, the wafer undergoes photolithography with mask number 1 to define the detailed geometry of the source/drain (S/D) electrodes Figure 4.2 shows the patterned photoresist layer (light green) forming the two S/D electrodes atop the molybdenum (Mo) thin film (white) The patterns are sharp and defect-free, providing robust protection for the underlying metal during the subsequent wet etching step using acid.
Figure 4.2: Details after photolithography using mask number 1: the patterned
S/D electrodes (light green) and the Mo thin film (white)
In the next fabrication step, the wafer undergoes wet chemical etching with acid to form the source/drain (S/D) electrodes, as illustrated in Figure 4.3 Unprotected white Mo regions not covered by photoresist are etched away, exposing the underlying Si/SiO2 substrate, while the green-patterned areas remain intact The etched features are uniform and sharp, with the S/D dimensions remaining unchanged relative to the photolithography-patterned structures This demonstrates that precise control of the etching time preserves the original design dimensions and prevents unintended short circuits between the two electrodes.
Figure 4.3: Details after wet etching
Following the final photoresist removal with an acetone solution, the S/D electrodes are revealed, as shown in Figure 4.4 The green photoresist is completely stripped, exposing sharp, well-defined white Mo electrodes that precisely match the protected patterns The electrode surfaces are smooth, free of wrinkles or dust particles Before advancing to the next fabrication steps, it is essential to verify that the two electrodes are not short-circuited.
Figure 4.4: S/D electrode details after photoresist removal
After successfully forming the source/drain (S/D) electrodes and ensuring there is no short circuit, the wafer undergoes photolithography to define the channel region before depositing the CuOx thin film As shown in Figure 4.5, mask 2 creates a rectangular hollow gap between the two S/D electrodes Within this gap, the exposed wafer substrate and the white edges of the S/D electrodes are visible, while the surrounding areas remain covered by the red-pink photoresist layer.
Figure 4.5: Channel details after photolithography
First, a CuOx thin film is sputtered onto the wafer, followed by immersion in an acetone solution to dissolve the photoresist and lift off the excess semiconductor material This process yields a precisely defined CuOx channel that maintains direct contact with the two source/drain (S/D) electrodes, as illustrated in Figure 4.6.
Figure 4.6: CuO x channel layer details formed in contact with the two S/D electrodes
During lift-off photolithography, the entire photoresist layer and a portion of the CuOx thin film are removed, leaving a rectangular reddish-brown semiconductor layer that matches the intended design Unlike the sharp edges of the source/drain electrodes, the remaining CuOx feature exhibits rounded edges due to shadowing from the photoresist This shadowing arises because the photoresist is designed with a re-entrant or undercut profile to prevent deposition on sidewalls and enable easier lift-off As sputtering proceeds, the top edge of the resist casts a shadow, partially obstructing material deposition on the edges and corners, which leads to rounded top surfaces and uneven thickness Consequently, the reverse-profiled photoresist causes reduced edge definition and rounding as a direct result of the shadowing effect.
Subsequently, the wafer is entirely coated with an insulating Si3N4 layer using the PECVD method, as described in the experimental section Figures 4.7 and 4.8 show images of the wafer before and after the deposition of the insulating layer It is evident that the entire wafer surface has changed to a deep blue-purple color, characteristic of the Si3N4 layer.
Figure 4.7: Wafer before (left) and after (right) the deposition of the insulating layer
Figure 4.8: Microscope image of the structure after the deposition of the insulating layer
After depositing the insulation layer, the gate electrode fabrication is performed using the lift-off technique, in the same manner as the channel fabrication step The process begins with photolithography to define the electrode pattern, and Figure 4.9 presents the gate electrode details after lithography, illustrating the successful pattern transfer and lift-off outcome.
Figure 4.9: Gate electrode details after patterning by photolithography
Finally, a thin molybdenum (Mo) layer is sputtered onto the wafer, forming the gate material The wafer is then immersed in an acetone solution to remove the excess photoresist via lift-off, yielding the gate electrode as shown in Figure 4.10.
Figure 4.10: Gate electrode formed after sputtering and lift-off
During wafer fabrication, the Si3N4 insulating layer deposited across the wafer completely covers the source/drain (S/D) electrodes, giving them a gray appearance and preventing direct electrical connection To enable measurement, the excess insulating layer is removed by dry etching with SF6, as described in Chapter 3 Figure 4.11 compares the wafer before and after removal, showing that the blue-purple insulating layer is fully etched away and the original SiO2/Si substrate is exposed A closer microscope view in Figure 4.12 reveals a white Mo layer on the S/D electrodes, confirming that the insulating layer covering them has been entirely eliminated.
Figure 4.11: Wafer before (left) and after (right) the removal of the excess Si 3 N 4 insulating layer.
I-V Characteristic Analysis of TFTs
Following fabrication, the thin-film transistors (TFTs) were evaluated to determine how variations in channel size and gate bias voltage influence their field-effect behavior A single wafer houses six chips, and each chip comprises 54 TFTs, each with distinct channel and electrode dimensions Copper oxide thin-film channels were deposited by sputtering under Ar–O2 gas flow with a ratio of 15:5 sccm By analyzing the measured I–V curves, the effects of electrode size and channel size on the TFTs’ field-effect characteristics can be established In one set of experiments, TFTs were designed with conductive channels that maintain a constant channel length.
20 μm) and a variable channel width, ranging from 20 μm to 200 μm
Figure 4.13: I-V Characteristics with Varying Channel Width (Constant 20 μm
Length) with zero bias on gate electrode of (15-5 sccm) TFTs
Figure 4.13 illustrates the drain current (Id)–drain voltage (Vds) characteristics of thin-film transistors (TFTs) with a fixed channel length of 20 μm while the channel width ranges from 20 μm to 200 μm under zero gate bias The plot shows that the device resistance decreases as the channel width increases, indicating that channel width directly influences current flow in a TFT A wider channel provides more space for charge carriers to move, thereby reducing the overall resistance and enhancing current transport.
To further validate this observation, we characterized the I‑V behavior of another set of thin‑film transistors (TFTs) In these devices, the channel length was fixed at 40 μm, while the channel width was varied from 20 μm to 200 μm, providing a systematic assessment of width‑dependent electrical performance.
Dr ain cu rr en t (I d ) (A)
Figure 4.14: I-V Characteristics with Varying Channel Width (Constant 40 μm
Length) with zero bias on gate electrode of (15-5 sccm) TFTs
Figure 4.14 presents the drain current–voltage (Id–Vds) characteristics of thin-film transistors (TFTs) with a fixed channel length of 40 μm while the channel width varies from 20 μm to 200 μm under zero gate bias The data show that, consistent with Figure 42, increasing the TFT channel width reduces the device resistance By analyzing the observed Id–Vds response, we derive a resistance expression for the TFT that accounts for channel size, obtained from the conduction‑mode current equation of the TFT together with Ohm’s law [12].
R is the channel resistance of the TFT, determined by the channel length L, channel width W, carrier mobility μ, and gate capacitance per unit area Cox, with the gate-source voltage VGS and the threshold voltage Vth governing device operation As shown in the equation, increasing L raises the channel resistance because electrons must travel a longer distance, while increasing W, μ, or Cox lowers resistance by enabling more current for a given voltage The gate-source voltage VGS relative to Vth controls the channel conductance, turning the TFT on when VGS exceeds Vth and defining the current flow in the channel Consequently, when L increases, the channel resistance increases; conversely, when L decreases, the channel resistance decreases, improving current drive for the same VGS.
As the channel width W increases, the TFT channel resistance decreases because the larger cross-sectional area allows more current to flow Conversely, Figures 4.13 and 4.14 show that the TFT resistance increases when the channel length grows from 20 μm to 40 μm, illustrating how a longer channel impedes current flow and raises resistance.
Dr ain cu rr en t (I d ) (A)
Figure 4.15: I-V Characteristics with Constant Channel Length-to-Width Ratio of (15-5 sccm) TFTs
In thin-film transistor (TFT) design, maintaining a channel length–to–width ratio of 4:1 ensures the channel resistance scales proportionally with the W/L parameter Because resistance is governed by W/L, keeping W/L at 4 ensures that any simultaneous changes in length and width preserve the same resistance scaling, so increasing both L and W proportionally (for example from 20 micrometers by 80 micrometers to 30 micrometers by 120 micrometers) yields the same resistance behavior and preserves the TFT's electrical characteristics Figure 4.15 shows the Id–Vds characteristics of TFTs with channel length and width varied while maintaining a 1:4 ratio under zero gate bias; the graph demonstrates that when the channel length–to–width ratio remains constant, the resistance exhibits minimal variation.
4.2.2 Effect of oxygen partial pressure
To evaluate the optimal sputtering conditions for CuOx thin films in TFT fabrication, key process parameters such as the Ar–O2 gas flow ratio are varied, with a focus on increasing the oxygen flow rate from 15-5 to 14-6 sccm The results reported in the IWAMSN 2024 proceedings show that oxygen flow variation during copper oxide sputtering significantly influences the resistance of TFTs These findings underscore the critical role of precise oxygen incorporation in CuOx sputtering for tailoring the electrical performance of TFTs.
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Figure 4.16 and Figure 4.17 present the drain current (Id) versus drain voltage (Vds) characteristics of TFTs prepared at a 14:6 sccm flow ratio, with fixed channel lengths of 20 μm and 40 μm respectively In these measurements, the channel width is varied from 20 μm to 200 μm while the gate electrode is at zero bias The resulting Id–Vds plots reveal how the drain current responds to changes in drain voltage under a grounded gate and highlight the impact of channel length and channel width on TFT performance.
Figure 4.16: I-V Characteristics with Varying Channel Width (Constant 20 μm and 40 μm Length) with zero bias on gate electrode of (14-6 sccm) TFTs
Figure 4.17: I-V Characteristics with Varying Channel Width (Constant 40 μm
Length) with zero bias on gate electrode of (14-6 sccm) TFTs
Dr ain cu rr en t (I d ) (A)
Dr ain cu rr en t (I d ) (A)
Similar to the 15:5 samples, the graphs show that channel size governs TFT resistance: a wider channel reduces resistance, whereas a longer channel increases it The most striking finding is that raising the oxygen flow rate during sputtering causes about a fivefold increase in channel resistance, highlighting the close link between oxygen incorporation and electrical properties in CuOx thin films This behavior stems from changes in the film's composition and structure: at a 15:5 oxygen ratio, the film contains less oxygen and favors the Cu2O phase, which has higher conductivity than CuO; with a higher oxygen ratio (14:6), the environment becomes more oxygen-rich, driving the oxidation of Cu2O to CuO CuO's wider bandgap and lower conductivity raise the film resistance, and additional grain boundaries formed during oxidation can further impede carrier transport, amplifying the resistance increase.
4.2.3 The effect of gate voltage
Figure 4.17 illustrates the drain current (Id) versus drain voltage (Vds) characteristics of a 14-6 sccm TFT sample with a channel size of 40 μm x 200 μm, as the gate electrode bias voltage (VG) is varied over 0 V, -2 V, -4 V, -6 V, and -10 V The data show that channel resistance decreases with negative gate bias, confirming the p-type semiconducting behavior of CuOx The channel resistance is lowest at VG = -6 V and -10 V, and at -10 V it is approximately four times smaller than at zero gate bias A noticeable change in channel resistance occurs in response to the gate voltage variations.
Figure 4.18: I-V Characteristics with Varying Gate Bias Voltage (40x200 μm channel size)
CuOx thin-film transistors (TFTs) in this study exhibit I–V characteristics that are nearly symmetric with respect to the drain–source voltage, indicating that the field-effect behavior is not clearly manifested This near-symmetric current–voltage response suggests that the device does not function as a conventional field-effect transistor, where gate modulation would produce asymmetric output curves and a distinct saturation region The device was fabricated in a top-gate, bottom-contact configuration with molybdenum (Mo) used as the source, drain, and gate electrodes, Si3N4 as the gate dielectric, and CuOx as the active channel material.
CuOx is a p-type oxide semiconductor with a relatively low intrinsic carrier concentration and a wide bandgap, both of which can limit charge transport in the channel The material’s electrical properties are highly sensitive to film thickness, stoichiometry, crystallinity, and post-deposition treatment As a result, the CuOx channel often exhibits low conductivity and insufficient modulation under gate bias, contributing to the absence of typical transistor behavior.
Molybdenum, with its relatively low work function, forms an energy barrier with the higher-Fermi-level p-type CuOx, resulting in symmetric Schottky-type contacts at both the source and drain that can dominate the current–voltage characteristics, especially when gate modulation is ineffective Although silicon nitride (Si3N4) as the gate insulator provides decent dielectric properties, it can lead to weak electrostatic coupling if the layer is too thick or contains interface traps Additionally, the Mo gate electrode's low work function may not be optimal for generating sufficient electric fields to effectively modulate the p-type CuOx channel.
The observed symmetric I–V characteristics arise from the combined effects of poor gate control, low channel conductivity, and symmetric Schottky barriers at the contacts This combination drives charge transport into a contact-limited regime, where injection at the contacts dominates over field-effect modulation, causing the device to behave like a two-terminal resistor with symmetric response rather than a true three-terminal transistor with gate-dependent switching.