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From those tradeoffs, one mayderive a digital reference platform capable of embracing the necessary range of digital hardware designs.. The chapter begins with an overview of digitalproc

storage, I/O channels, and/or general-purpose processors A digital hardwarearchitecture may be characterized via a reference platform, the minimum set

of characteristics necessary to define a consistent family of designs of SDRhardware This chapter develops the core technical aspects of digital hardwarearchitecture by considering the digital building blocks These insights permitone to characterize the architecture tradeoffs From those tradeoffs, one mayderive a digital reference platform capable of embracing the necessary range

of digital hardware designs The chapter begins with an overview of digitalprocessing metrics and then describes each of the digital building blocks fromthe perspective of its SDR architecture implications

I METRICS

Processors deliver processing capacity to the radio software The ment of processing capacity is problematic Candidate metrics for processingcapacity are shown in Table 10-1 Each metric has strengths and limitations.One goal of architecture analysis is to define the relationship between thesemetrics and achievable performance of the SDR The point of view employed

measure-is that one must predict the performance of an unimplemented software suite

on an unimplemented hardware platform One must then manage the tational demands of the software against the benchmarked capacities of thehardware as the product is implemented Finally, one must determine whether

compu-an existing software personality is compatible with compu-an existing hardware suite

TABLE 10-1 Processing Metrics

MIPS Millions of Instructions per Second

MOPS Millions of Operations per Second

MFLOPS Millions of Floating Point Operations per Second

Whetstone Supercomputing MFLOPS Benchmark

Dhrystone Supercomputing MIPS Benchmark

SPECmark SpecINT, SpecFP Instruction Mix Benchmarks (92 and 95)

312

METRICS 313

Consistent use of appropriate metrics assures that these tasks can be plished without unpleasant surprises

accom-1 Differentiating the Metrics MIPS, MOPS, and MFLOPS are differentiated

by logical scope An operation (OP) is a logical transformation of the data in

a designated element of hardware in one clock cycle Processor architecturestypically include hardware elements such as arithmetic and logic units (ALUs),multipliers, address generators, data caches, instruction caches, all operating

in parallel at a synchronous clock rate MOPS are obtained by multiplyingthe number of parallel hardware elements times the clock speed If multipleoperations are required to complete a machine instruction (e.g., a floating-point multiply), then

MIPS = ®MOPS, ® < 1

If, on the other hand, the processor has a very long instruction word (VLIW),

® may be greater than 1 Suppose, for example, that a processor includes a

“smart” cache, an ALU, and two parallel multiplier units with a 250 MHzsystem clock One could characterize this processor in terms of the operations

of the ALU and multipliers If ® = 1, then it can deliver 250" 3 or 750 MIPS,maximum If the multipliers accomplish one 32-bit floating-point multiply onevery clock cycle, then the processor provides 500 MFLOPS Thus, one maycharacterize such a device as capable of a peak of 750 MIPS/500 MFLOPS.This notation means “750 MIPS of which up to 500 may be MFLOPS.” Digitalfiltering takes more floating-point operations than, say, protocol processing,

or FEC algorithms If the SDR application uses a mix of 50% ALU and50% floating point operations, then the processor delivers a maximum of0:5" 250 ALU operations plus 0:5 " 500 MFLOPS for a total of 125 + 250 =

375 MIPS Clearly, processing capacity realized is a function of instructionmix

Alternatively, one could consider just the memory cache operations, tributing 250 MOPS of memory operations (MEOPS) If the memory cacheoperates fast enough so that the ALU and multipliers are never waiting fordata or instructions, then the memory cache is not a bottleneck If, however,there are states in which it must wait, then the potential 750 MIPS will not

at-be realized In this case, since MEOPS < MIPS, then the peak of 750 MIPScannot be sustained beyond the capacity of the cache For extremely com-putationally intensive operations like digital filtering, one may in fact realizethe maximum capacity because all the data is resident in cache Cache-missesthen degrade performance

2 Processor-Memory Interplay The execution of an instruction requires cessing memory for instructions and data or accessing local registers Pro-cessors that are more complex may fill a pipeline with instructions to beexecuted concurrently Pipelines produce no results until the pipeline is full.Thereafter, pipelines produce a result per clock cycle Newer architectures

3 Standard Benchmarks Consequently, MIPS are hard to define Often, thepopular literature attributes MIPS based on a nonstatistical transformation of

MOPS into instructions that could be executed in an ideal instruction mix.

This approach makes the chip look as fast as it possibly could be Sincemost manufacturers do this, the SDR engineer learns that achievable per-formance on the given application will be significantly less than the nomi-nal MIPS rating The manufacturer’s MIPS estimate is useful because it de-fines an upper bound to realizable performance Most chips deliver 30 to60% of such nominal MIPS as usable processing capacity in a realistic SDRmix

In the 1970s, scientists and engineers concerned with quantifying the fectiveness of supercomputers developed the Whetstone, Dhrystone, and otherbenchmarks consisting of standard problem sets against which each new gen-eration of supercomputer could be assessed These benchmarks focused onthe central processor unit (CPU) and on the match between the CPU andthe memory architecture in keeping data available for the CPU But theydid not address many of the aspects of computing that became important

ef-to prospective buyers of workstations and PCs The speed with which the play is updated is a key parameter of graphics applications, for example TheSPECmarks evolved during the 1990s to better address the concerns of theearly-adopter buying public Consequently, SPECmarks are informative butthese also are not the ideal SDR metric in that they do not generally reflectthe mix of instructions employed by SDR applications Turletti [293], how-ever, has benchmarked a complete GSM base station using SPECmarks, asdiscussed further below

dis-4 SDR Benchmarks At this point, the reader may be expecting some new

“SDR benchmark” to be presented as the ultimate weapon in choosing amongnew DSP chips Unfortunately, one cannot define such a benchmark First

METRICS 315

Figure 10-1 Identify processing resources

of all, the radio performance depends on the interaction among the ASICs,DSP, digital interconnect, memory, mass storage, and the data-use structure ofthe radio application These interactions are more fully addressed in Chapter

13 on performance management It is indeed possible to reliably estimatethe performance that will be achieved on the never-before-implemented SDRapplication But the way to do this is not to blindly rely on a benchmark.Instead, one must analyze the hardware and software architecture (using thetools described later) One may then accurately capture the functional andstatistical structure of the interactions among hardware and software Thissystems analysis proceeds in the following steps:

1 Identify the processing resources

2 Characterize the processing capacity of each class of digital hardware

3 Characterize the processing demands of the software objects

4 Determine how the capacity of the hardware supports the processingdemands of the software by mapping the software objects onto the sig-nificant hardware partitions

There is a trap in identifying the hardware processor classes ASICs and DSPsare easily identified as processing modules But one must traverse each sig-nal processing path through the system to identify buses, shared memory,disks, general-purpose CPUs, and any other component that is on the pathfrom source to destination (outside the system) Each such path is a process-ing thread Each such processor has its own processing demand and prioritystructure against which the needs of the thread will be met One then abstractsthe block diagram into a set of critical resources, as illustrated in Figure 10-1.This chapter begins the process of characterizing the capacity of SDR hard-ware It summarizes the tradeoffs among classes of processor, functional ar-chitecture, and special instruction sets Other source material describes how

to program them for typical DSP applications [294] The extensive literatureavailable on the web pursues detailed aspects of processors further [295–298].The popular press provides product highlights (e.g., [299–303]) This text, onthe other hand, focuses on characterizing the processors with respect to thesupport of SDR applications This is accomplished by the derivation of a dig-ital processing platform model that complements the RF platform developedpreviously

II HETEROGENEOUS MULTIPROCESSING HARDWARE

Segment boundaries among antennas, RF, IF, baseband, bitstream, and sourcesegments defined in the earlier chapters make it easy to map multiband, multi-mode, multiuser SDR personalities to parallel, pipelined, heterogeneous mul-tiprocessing hardware

A Hardware Classes

Some design strategies map radio functions to affordable open-architectureCOTS hardware In one example, the VME or PCI chassis hosts the RF, IF,baseband, and bitstream segments as illustrated in Table 10-2 The workstationhosts the OA&M, systems management, or research tools including the userinterface, development tools, networking, and source coding/decoding Eachmodule shown in the table represents a class of hardware The parameters ofthese modules that assure that a software personality will work properly aredefined in the digital processing reference platform

Consider the roles of these hardware classes The bus host serves as tems control processor The DSPs support the real-time channel-processingstream, sometimes configured as one DSP per N subscriber channels, where

sys-N typically ranges from 1 to 16 The path from the ADC to the first ing/decimation stage may use a dedicated point-to-point mezzanine intercon-nect such as DT ConnectTM, Data Translation Customized FibreChannel andTransputer links have also been used Synchronization of the block-by-blocktransfers across this bus with the point-by-point operations of the first fil-tering and decimation stage introduces inefficiencies that reduce throughput.Fan-out from IF processing to multiple baseband-processing DSPs also may

filter-be accomplished via a dedicated point-to-point path such as a mezzanine bus.Alternatively, an open-architecture high-data-rate bus might be used

Instead of configuring such a heterogeneous multiprocessor at the boardlevel, one might use a preconfigured system MercuryTM, for example, hasoffered a mix of SHARC 21060 [304] (Analog Devices), PowerPC RISC, and

HETEROGENEOUS MULTIPROCESSING HARDWARE 317

Figure 10-2 Alternative processing modules and interconnect

Intel i860 chips with Raceway interconnect [305–307] Raceway I had inally three paths at 160 MByte/sec interconnect capacity Arrays of WE32’swere used in AT&T’s DSP-3 system Arrays of i860’s were available from SkyComputer [308], CSPI [309], and others Of particular note is UNISYS’ mil-itarized TOUCHSTONE processor, which was also based on the i860 [310].Although the i860 is no longer a supported Intel product, the architectures areillustrative

nom-System-on-a-chip level architectures also employ ASIC functions, sharedmemory, programmable logic arrays, and/or DSP cores The physical packag-ing of these functions may be organized in point-to-point connections, buses,pipelines, or meshes In each case, digital interconnect intervenes betweenfunctional building blocks and memory Threads are traced from RF stimuli

to analog and digital responses Often in handsets, there is no ADC or DAC.Instead, RF ASICs perform channel modem functions to yield an alternativefunctional flow

Figure 10-2 contrasts these complementary views of interconnect and otherhardware classes The boundaries of the digital flow are the external interfacecomponents These include the display drivers, audio ASICs, and I/O boardsthat access the PSTN Tradeoffs among internal interconnect are addressed inthe next section

B Digital Interconnect

Digital interconnect in systems-on-a-chip architectures is an emerging area.Over time, standards may emerge because of the need to integrate IP from amix of suppliers on a single chip Macroscale digital interconnect has a longer

history of product evolution, and that is the focus of this discussion Thesemacroscale architectures may serve as precursors to future nanoscale on-chipinterconnect.

Illustrative approaches to digital interconnect for open-architecture ing nodes are the dedicated interconnect, wideband bus, and shared memory(Figure 10-3)

process-1 Dedicated Interconnect Dedicated interconnect is typically available fromsubsystem suppliers like Pentek [311] Pentek provides 70 MHz ADC boardsand Harris or Graychip digital receiver boards Its MIXTM bus interconnectsthese cards efficiently In addition, if the set of boards and interconnect doesnot work, the vendor resolves the issues This approach leverages COTS prod-ucts, with low cost and low risk For applications with relatively small numbers

of IF channels, it represents a solid engineering approach

2 Wideband Bus The next step up in technical sophistication is the band bus The SCI bus [312], for example, has been used in supercomputersystems for several years It is becoming available in turnkey formats includ-ing interface chip sets The gigabyte-per-second capacity of the SCI bus couldcontinue to increase with the underlying device technology In addition, thedesign scales up easily to 8" 140 MBps channels The MIX bus, DT Connect,Raceway, SkyChannel [313], and other lower-capacity designs may be con-figured in parallel to attain high aggregate rates This requires the hardwarecomponents to be appropriately partitioned Other high-speed bus technologiesare emerging, such as Vertical Laser at 115 GHz [314, 315]

wide-3 Shared Memory Shared memory can deliver the ultimate in interconnectbandwidth Bulk memory of 64 MBytes easily has 16- to 64-bit paths Scaling

to 128 or 256 bits is feasible Clock rates of 25 to 250 MHz are within reach.Thus, aggregate throughput of 3.2 to 64 gigabytes per second are becoming

HETEROGENEOUS MULTIPROCESSING HARDWARE 319

Figure 10-4 Wideband ADC rate versus interconnect complexity

practicable with 4 ported shared memory As the number of ports increasesabove 4, clock contention drives throughput down But the switching, blockingand routing of data streams need not degrade throughput if the shared memory

is supported by programmable direct memory access (DMA) or equivalenthardware If only two very wideband input streams and two output streamsneed to be interconnected simultaneously (possibly out of a choice of 4 or8), the shared memory architecture may be the best choice Shared memoryhistorically has the greatest performance, design/development cost, and risk

of these approaches to digital interconnect

4 SDR Applications As illustrated in Figure 10-4, the ADC drives the ital interconnect architecture Considering only the ADC’s output data rate(in millions of bytes per second) and the nominal capacity of typical buses,the figure shows the relationship between aggregate ADC rate and number ofbuses One 40 MByte per second VME bus can support a 3 MByte per secondADC stream using less than 1/10 of its capacity As data rates increase, multi-ple buses and/or buses of greater bandwidth must be used to support the datarate The 600 MByte per second ADC rate represents two bytes of resolution

dig-at 300 MHz, while the 500 MHz ADC has only one byte of resolution in thisexample Interconnect efficiency is usually a function of the size of the datablocks being transferred DMA transfers require setup, an overhead task thatdetracts from overall throughput Buses also have bus-associated handshakingthat constitutes overhead

Figure 10-5 Interconnect efficiency.

Most buses experience low throughput for small block sizes Mercury acterizes the performance of its products thoroughly The maximum sustain-able transfer rate of Raceway I varies as a function of DMA block length asillustrated in Figure 10-5 Although the peak rate of 160 MB/sec is not sus-tainable, it is approached with block sizes above 4096 bytes Some devices(e.g., ADCs) may have short on-board buffers, constraining blocks to smallersizes In addition, algorithm constraints may proscribe smaller block sizes A0.5 ms GSM frame, digitized at 500 k samples per second, for example, may

char-be processed with a block size of 250 samples (500 Bytes) If presented toRaceway in that format, the sustainable throughput would fall between 80 and

120 MB/sec as shown in the figure If this is understood, then a constraint can

be established between the algorithm and Raceway as an interconnect module.Constraint-management software can then assure that the capacity of the in-terconnect is not exceeded when instantiating a waveform into such hardware

In a more representative example, the entire bandwidth of the GSM allocationcould be sampled at 50 M samples/sec, yielding 25.5 k samples per GSMframe, or over 50 kBytes This data could be efficiently transferred to digitalfilter ASICs in 8 kByte blocks

5 Architecture Implications The physical format of digital interconnect(e.g., PCI, VME, etc.) need not be incorporated into an open-architecturestandard for SDR The less specific standard encourages competition and tech-nology insertion by not unnecessarily constraining the implementations On

APPLICATIONS-SPECIFIC INTEGRATED CIRCUITS (ASICS) 321

the other hand, such an architecture must recognize the fact that each class

of physical interconnect entails implementation-specific constraints An openarchitecture that supports multivendor product integration therefore must char-acterize those constraints to assure that software is installed on hardware withthe necessary interconnect capabilities Otherwise, interconnect capacity maybecome the system bottleneck that causes the node to fail or degrade unex-pectedly

An architecture standard used by a large enterprise to establish productmigration paths, on the other hand, should specify the digital interconnect (e.g.,PCI) and its migration from one physical realization to others as technologymatures

III APPLICATIONS-SPECIFIC INTEGRATED CIRCUITS (ASICs)

The next step in the digital flow from the ADC to the back-end processors in abase station is typically a pool of ASICs ASICs particularly suited to softwareradios include digital filters, FEC, and hybrid analog-digital RF-transceivermodules with programmable capabilities Waveform-specific ASICs are ex-hibiting increased programmability, mixing the capabilities of digital filters,FEC, and general-purpose processors for new classes of waveform (e.g., W-CDMA) In addition, DSP cores with custom on-chip capabilities are ASICs,but for clarity, they are addressed in the section on DSP architectures

A Digital Filter ASICs

Base station architectures need digital frequency translation and filtering forhundreds of simultaneous users Minimum distortion and nonlinearities are re-quired in the base-station receiver architecture to meet near–far requirements.Digital-filter ASICs therefore extract weak signals in the presence of strongsignals The architecture for such ASICs is illustrated in Figure 10-6 The fre-quency and phase of the ASIC is set so that the complex multiply-accumulatorchip (CMAC) translates the wideband input to a programmable baseband.For first-generation cellular applications, the decimating digital filters (DDFs)yielded 25 or 30 kHz narrowband voice channels through computationallyintensive filtering

Hogenaur realized that adjustment of the integrator, comb, and tor parameters reduces aliasing as illustrated in Figure 10-7 [316] Aliasingbands are folded into baseband at the complex sampling frequency Choice

decima-of decimation rate and comb filter parameters places a deep null in the band

of interest, achieving 90 dB of dynamic range using limited-precision ger arithmetic The Hogenaur filter thus facilitated the efficient realization ofthe Harris ASICs The product-line evolved to the HSP series now owned byIntersil

inte-Oh [317] has proposed the use of interpolated second-order polynomials as

an improvement over the Hogenaur filter Graychip has also been

develop-Figure 10-6 Digital filter ASIC architecture (a) top-level ASIC architecture; (b)

digital decimating filter architecture

Figure 10-7 Hogenaur filter reduces aliasing

ing filtering ASICs since the late 1980s In addition, Zangi [318] describes

a transmultiplexer architecture that yields all channels in a cell site using

a Discrete Fourier Transform (DFT) stage Zangi’s transmultiplexer offersadvantages for ASIC implementations For example, with 1800 points perfilter in a Digital AMPS application, Fs = 34:02 MHz, and decimation of

350, the DFT requires 1134 points for a complexity of 826 M multiplies persecond Such ASICs would simplify cell-site designs

The complexity of frequency conversion and filtering is the first-order minant of the digital signal processing demand of the IF segment In a typicalapplication, a 12.5 MHz mobile cellular band is sampled at 30.72 MHz (Msamples per second) Frequency translation, filtering, and decimation requiring

deter-APPLICATIONS-SPECIFIC INTEGRATED CIRCUITS (ASICS) 323

Figure 10-8 FEC ASIC architecture

200 operations per sample equates to over 6000 MIPS of processing demand.Although GFLOPS microprocessors are now available, one may offload thiscomputationally intensive demand to dedicated ASICs chips such as the Inter-sil or Gray digital receiver chip Spreading and despreading of CDMA, also an

IF processing function, creates demand that is proportional to the bandwidth

of the spreading waveform (typically the chip rate) times the baseband signalbandwidth This function also may be so computationally intensive that withcurrent technology limitations, it is typically allocated to ASIC chips as well

B Forward Error Control (FEC) ASICs

Forward error control ASICs offload computationally intensive aspects of ror control coding onto dedicated hardware As shown in Figure 10-8, theFEC decoder synchronizes the input bitstream, reverses symbol puncturing,and computes the majority logic best-estimate of the transmitted bits (e.g.,using a Viterbi decoder) It then differentially decodes the stream and de-scrambles the resulting bitstream by adding the scrambling bitstream (e.g.,V.35) synchronously to the output stream

er-FEC operations are bit-serial, usually involving register lengths that areprime numbers like 11, 13, 17, etc These bits operations do not pack and un-pack efficiently into 8-, 16-, and 32-bit arithmetic offered by the typical DSP.Consequently, there is significant bit-masking and other nonessential steps toimplement the FEC functions When implemented in a conventional DSP, theFEC operations consume considerable power An FEC chip, on the other hand,consists of exactly the right bitstream structure (e.g., an 11-bit register), withonly those interconnects among bits required by the FEC algorithm As a re-sult, FEC ASICs dissipate the absolute minimum power for a given data rate.Some FEC chips are programmable across a range of FEC functions, with-out much loss of power efficiency The issue of power efficiency is central totradeoffs in the handsets where power is at a premium

Turbocodes have been shown to improve error protection by interleavingtwo systematic concatenated codes Since fading is generally correlated, it canhave an impact on the success of turbocoding in CDMA systems [319] The

Figure 10-9 Turbocoded CDMA system.

complexity of the turbo encoding subsystem is such that it is a strong candidatefor ASIC or FPGA implementation In addition, the interleaver, pulse shaping,delay, and combining circuits may be included on the same FPGA or ASIC.The decoder has a somewhat higher level of complexity, as illustrated in Figure10-10

C Transceiver ASICs

Alcatel, Siemens, Motorola, Ericsson, Nokia and others employ direct version transceiver ASICs in handsets as presented in Chapter 8 Other RFASICs integrate dual-mode amplifiers, matching circuits, and related RF and

con-RF conversion modules in a single package GaAs has been a popular devicetechnology for these circuits, but RF CMOS is making progress for handsetapplications Handset ASICs may nonlinearly distort the RF, provided the sub-scriber’s signal is not distorted beyond recovery Some digital ASICs includeRF/IF functions

The STEL-2000, for example, is a highly programmable ASIC with tions similar to the digital filter ASICs, but with additional transceiver func-tions as illustrated in Figure 10-11 The numerically controlled oscillator(NCO) and clock feed the CPSK modulator The NCO’s I&Q (SIN, COS)channels provide the reference signal for the down conversion stage Differ-ential encoding and decoding pairs are provided The receiver clock generator,

func-PN code generator, matched filter, power detector, and symbol tracking cessor may function as a despreader Control and interface logic permit anexternal microprocessor to integrate this ASIC into a spread-spectrum class

pro-APPLICATIONS-SPECIFIC INTEGRATED CIRCUITS (ASICS) 325

Figure 10-10 Turbocoded CDMA receiver archiecture

Figure 10-11 STEL-2000A block diagram

Figure 10-12 Architecture alignment of ASIC functions.

SDR The Bitspreader-2000 SDR transceiver [320] integrates the STEL-2000,

a synthesized sampling clock generator, and an FEC ASIC under the control of

an 89C51 microcontroller As gate densities continue to increase, such ASICfunctions may be integrated around a DSP-core for volume production

D Architecture Implications

Digital filtering ASICs contribute to both base-station and handset tures Since there is continuing research in this area, one can expect further de-velopment of associated intellectual property and related products The sameapplies to FEC The advantages of ASIC implementations include reducedsize, weight, and power of the target devices In addition, these devices re-duce parts count, reducing manufacturing costs proportionally

architec-These ASICs represent a category of optimization of SDR products thatmust be addressed in SDR architecture One approach is to encapsulate suchdevices within the modem entity This blurs the distinction between modemand IF processing FEC may be encapsulated within some modems, but digitalfilter ASICs are better represented as digital IF processing since they performIF-to-baseband frequency translation and related filtering This alignment ofASIC functions to architecture-level functions is illustrated in Figure 10-12.Clearly, the Modem function has been generalized to include some FEC as-pects of bitstream processing In addition, the service and network supportfunction includes many aspects of protocol stack processing besides FEC

If an SDR architecture is to facilitate the integration of such power-efficientdevices as ASICs, then the architecture has to include a mechanism for passingcontrol and data to these facilities Efficient access from architecture-level

APPLICATIONS-SPECIFIC INTEGRATED CIRCUITS (ASICS) 327

Figure 10-13 Tunneling provides open-architecture access to proprietary IP

functions to component-level building blocks may be called tunneling It

re-quires the refinement of the layered virtual machine architecture illustrated inFigure 10-13

Several aspects of the tunneling facility need to be pointed out These clude the definition of interface points, the use of the tunneled component, theidentification of constraints, and the resolution of conflicts These aspects aresupported by Tunnel( ) functions that tell the radio infrastructure about theinterfaces to the applications objects and the capabilities of the ASIC objects

This may not always be the case In the example, the TCP software for aspecific waveform personality may use the ASIC to provide some additional

If INFOSEC is not null, then TCP bits first may be scrambled and thenpassed to the modem to add error-protecting redundancy The FEC ASIC couldallow buffers to be used independently by networking and modem functionsvia its FEC( ) method In this case, the radio-applications-level software ob-jects execute FEC(buffer) to block-encode the data in the FEC’s input buffer.The driver associated with the ASIC converts this call to a signal on an ap-propriate hardware control line This is similar to the Hayes AT language formodems Instead of expressing commands as a sequence of ASCII strings,commands are expressed by passing a message to the FEC ASIC to executeone of its public methods.

An FEC ASIC has some maximum input buffer size and maximum put or FEC conversion rate These parameters define constraints under whichtunneling will yield specific levels of performance Such constraints are typicalfor optimized devices In order for tunneling to be effective, these constraintsneed to be represented in the architecture for the use of a constraint-manager.Architecture compliance, then, should entail a design rule that “constraints onASICs are defined.” The constraint manager must be capable of processingthese constraints Constraint-violation responses should be defined and theusers should have an easy way of understanding the error conditions Inter-nal constraints might include clocking the bits through the ASIC at a certaindata rate Other constraints may include a limit on the number of input-outputbuffer pairs There may be a limit on the size of a specific input buffer (e.g.,Reed–Solomon coding occurs on blocks of specific integer multiples), or oninitialization (e.g., convolutional codes remember the internal states of the shiftregister) All of the constraints may be enforced without user intervention ifthe computational demands of the radio application are compatible with theresources of the hardware platform But the satisfaction of such constraints

through-is only the first step in addressing potential conflicts between the personalityand the platform

Some INFOSEC design rules, for example, preclude the use of one ASIC

to process both the clear bits and the protected bits If so, then the FEC ASIC