Digital systems final exam of semester 1, 2018 2019

d Re-design the logic circuit for the CLEAR function inthe MOD-11 counter to use the NAND gates with 2 inputs only.. Question 2 3 points Given the following table: a Write the output exp

HCMC University of Technology and

Education

Faculty for High Quality Training

Digital Systems FINAL EXAM OF SEMESTER-1, 2018-2019

Course: Digital Systems

Course code: DIGI330163E

Number of pages: 01 pages

Duration: 90 minutes

Only used one A4-handwriting paper

Question 1 (2.5 points)

Given an asynchronous counter with 4 JK-FFs

a) Design and draw one asynchronous counter with the

MOD 11, in which its inputs

and outputs need to be noted clearly

b) Explain the operation of this MOD-11 counter.

c) Draw the output waveforms of the MOD-11 counter.

d) Re-design the logic circuit for the CLEAR function in

the MOD-11 counter to use

the NAND gates with 2 inputs only

Question 2 (3 points)

Given the following table:

a) Write the output expressions and draw a

logic circuit with the output expressions

using logic gates

b) What is the name of this logic circuit?

Why?

c) Draw the Pin diagram of this circuit

Question 3 (2.5 points)

Given the ROM memory as shown in Figure

a) Determine the memory capacity corresponding to the

addresses from the 9th register to the 25th register in byte

b) Describe functions, inputs and outputs of ROM in

Figure

c) Determine the address at the 60th register in Hex

Question 4: (2 points)

Given a Digital to Analog converter with 5 digital inputs and 1

analog output, its maximum voltage is 15.5V

a) Determine the K resolution

b) Assume that the digital input is 11001, determine the

analog

output?

Notice: The teacher is not allowed to explain any more

ĐÁP ÁN

Question 1 (2.5 points)

Given an asynchronous counter with 4 JK-FFs

a) Design and draw one asynchronous counter with the

MOD-11, in which its inputs

and outputs need to be noted clearly

With an asynchronous counter using the negative clock pulse, the low active CLEARs

and PRESETs in FF-JKs are set to be 1 for operation respond to CKs, Mod-11 has

Q1Q2Q3Q4=1101 which are connected to a NAND with

3 inputs as shown in Fig 1.1

b) Explain the operation of this MOD-11 counter.

In this asynchronous counter with the negative clock pulse, Mod-11 has

Q1Q2Q3Q4=1101 Therefore, three outputs Q1, Q2, Q4

of the FF-JK with 1s will be

connected to the inputs of a NAND gate as shown in Figure 1 Thus when the circuit

counts from zero to this state 11, it means that the FF-JK inputs Q1, Q2, Q4

simultaneously are one and the NAND will be zero It means that the CLR is zero and

all outputs are zero Thus, the inputs of the NAND are zero and its output is one, this

makes the circuit counts again from zero.

c) Draw the output waveforms of the MOD-11 counter.

After 11 CKs, the circuit is reset so that all outputs of JK-FFs are zero and the

circuit counts again as shown in Fig 1.2

d) Re-design the logic circuit for the CLEAR function in

the MOD-11 counter to use

the NAND gates with 2 inputs only.

A CLEAR circuit is designed to use 3 NAND gates with

2 inputs as shown in Fig

1.3

Question 2 (3 points)

Given the following table:

a) Write the output expressions and draw a logic circuit

with the output expressions

using logic gates

b) What is the name of this logic circuit? Why?

This is the encoder, in which 4 inputs with the active, zero and 2 outputs It means

that there is an input code, there will be a corresponding

to output as shown in

Figure 3

c) Draw the Pin diagram of this circuit

Given the ROM memory as shown in Figure 4

a) Determine the memory capacity corresponding to the

addresses from the 9th register to the 25th register in byte

The memory capacity is calculated as follows:

B=25-9+1=17 bytes, corresponding to 17 registers due to its

data bus is 8-bit

b) Describe functions, inputs and outputs of ROM in

Figure

This is a memory IC with Read Only, in which there are

6

addresses (from A0 to A5), 8 data lines (8-bit data) and

CE

(Chip Enable, low active) enables the operating IC with the

low level

c) Determine the address at the 60th register in Hex

In this case, it means that we calculate from the register 0

to the register 59 Thus

(A5A4A3A2A1A0=111011=3BH)

Question 4: (2 points)

Given a Digital to Analog converter with 5 digital inputs and 1 analog output, its maximum voltage is 15.5 V

a) Determine the K resolution

The resolution: K=Vmax/Digital input=15.5/31=0.5 V,

in which the digital input

of 5-bit is 111112=31

b) Assume that the digital input is 11001, determine the

analog output?

We have:

V=K* Digital input=0.5*25=12.5 V