MINISTRY OF EDUCATION AND TRAININGHO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION GRADUATION THESIS MAJOR: COMPUTER ENGINEERING TECHNOLOGY INSTRUCTOR: PHAM VAN KHOA Ho Chi Minh c
INTRODUCTION
Problem Statement
Electronic circuit design is a vital and intriguing field that captivates engineers, researchers, and hobbyists alike It encompasses the evolution of semiconductor technology, progressing from 90nm to 3nm and beyond, and involves the intricate design of integrated circuits Key components in electronic circuits, such as diodes, transistors, resistors, capacitors, and inductors, facilitate the flow of electric charges, enabling functional circuits Analog circuits manage consistent voltage or current flows, delivering steady audio or video signals, while digital circuits utilize binary pulses to convey information, characterized by their distinct jagged waveforms that differentiate them from analog signals.
Utilizing Synopsys tools for designing 6T SRAM bit cells within TSMC 16nm technology is a significant focus in the semiconductor industry This article emphasizes the critical role of electrical circuit design in driving technological advancements, particularly highlighting the application of Static Random-Access Memory (SRAM) in modern digital systems.
It then goes on to describe the manufacturing process, schematic design and structure of 6T SRAM bit cells as well as their importance in memory storage
As technology advances, the significance of layout design in Electronic Design Automation (EDA) increases, with tools like Fusion Compiler, Custom Compiler, and PrimeTime from Synopsys aiding designers in creating accurate layouts Analyzing performance metrics such as power consumption and delay is essential for validating circuit designs, especially as challenges intensify with smaller semiconductor nodes, like 16nm technology The effectiveness of SRAM circuit design heavily relies on the employed technology, and without these modern tools, researching, evaluating, and comprehending circuits would be significantly more challenging.
In conclusion, the design of 6T SRAM bit cells with Synopsys tools highlights the significance of these tools in enhancing electronic circuit design Understanding the workflow facilitated by these tools, from schematic to layout design, is essential for driving technological advancement.
Project objective
Gain knowledge of FinFET technology in order to comprehend the architecture of TSMC 16nm technology
Acquire proficiency with the tools and comprehension of the workflow including schematic drawing and layout verification (pre-sim and post-sim)
Comprehend the 6T SRAM circuits working principles and the internal phenomena that occur in order to understand the DRC/LVS checking procedures
Create a circuit design for the 6T SRAM that can accurately execute read/write operations in both schematic and layout drawings
Assess the circuit’s power usage and read/write latency Compare the Pre- simulation and Post-simulation results.
Research Substance
This article details the comprehensive design process of a 6T SRAM bit cell, beginning with the creation of the schematic for the main memory cell and supplementary components such as write drivers, differential sense amplifiers, and pre-charge circuits The schematic undergoes meticulous design and testing through HSPICE modeling and simulation, utilizing WaveViews to assess performance and optimize the overall design The Synopsys Custom Compiler plays a crucial role in facilitating this process.
Once the schematic design is converted into an SP file in HSPICE format, it undergoes functional testing to determine transistor sizes and operational parameters, along with the translation of the schematic into HSPICE netlists Before proceeding to the layout stage, the circuit is simulated using Synopsys WaveViews, enabling designers to easily identify errors and predict performance outcomes.
The layout design is completed using the approved schematic, with Custom Compiler facilitating the arrangement of transistors, wire routing, and metal layer production to create a physical representation of the circuits To ensure compliance with production standards, Design Rule Check (DRC) and Layout versus Schematic (LVS) checks are performed to verify that the layout aligns with the schematic.
The extraction of parasitic items from the layout view generates a layout netlist, which is usually saved as an SPF file Subsequent simulations are performed using this netlist to ensure optimal layout performance after the extraction process.
3 netlist through WaveViews Correcting any anomalies waveform analysis looks at timing delays signal integrity and power usage
The design of 6T SRAM bit cells requires comprehensive validation layout creation and schematic development By employing these techniques, engineers can improve memory technology, resulting in more reliable and efficient integrated circuits Additionally, Synopsys tools facilitate increased productivity and effectively manage 16nm technology parameters throughout the entire 6T SRAM layout design process.
Research Limitations
The primary objective of this project is to simulate waveforms to verify the functional correctness of 6T SRAM between pre-simulation and post-simulation phases Due to time constraints, the project does not delve into layout design complexities or the implementation of Synopsys technology It omits discussions on the necessity of the DRC stage, noise phenomena, and the reasoning behind foundry-imposed guidelines during DRC checks, focusing instead on logic and operational functionality The project exclusively utilizes 16nm technology, with sensitive information excluded in compliance with censorship regulations.
The primary objective of this project is to standardize 6T SRAM design, utilizing Synopsys tools for optimal results The process will involve meticulous documentation at every stage, from pre-simulation to post-simulation, ensuring a comprehensive evaluation of the circuit's efficiency once completed.
Methodology
The methodology of the project is as follows:
The comparison of delay and power consumption in 6T SRAM reveals significant differences between pre-simulation and post-simulation results When additional detailed parameters for resistance and capacitance are integrated for each wire, the post-simulation outcomes demonstrate a more accurate representation of performance metrics This highlights the importance of incorporating comprehensive wire characteristics to enhance the reliability of SRAM analysis, ultimately leading to better optimization in circuit design.
Analyze the changes and differences when the layout circuit is added
Complete the layout and schematic design to accurately reflect the read and write operations of the 6T SRAM
Structure of an essay
This chapter describes the significance and need for the topic giving the reasoning behind the topic selection and outlining the goals subjects under investigation and project parameters
Chapter 2: LITERATURE REVIEW AND BACKGROUND
This section introduces FinFET theory and provides a brief comparison with MOSFET technology It includes details on 6T SRAM and an overview of the Synopsys tools used in its design Additionally, it discusses essential design components such as the Write Driver, Pre-charge, and Differential Sense Amplifier, which enhance the read and write operations of 6T SRAM.
This chapter examines the Pre-simulation and Post-simulation procedures, offers the complete Schematic and Layout drawings and offers observations on the operation of both circuits
This section examines the power consumption of both designs, compares the pre- and post-simulation outputs and analyzes the read/write delays of the two designs
This chapter provides an overview of the topics covered in the project evaluates its advantages and disadvantages and suggests future research and useful applications.
LITERATURE REVIEW AND BACKGROUND
Literature review
The 6T SRAM bit cell is a crucial component in various memory systems, making it a focal point of significant interest This article explores the intricate design process of the 6T SRAM bit cell, drawing insights from relevant research studies and industry standards.
The study "Performance Analysis of SRAM Designs Using TSMC 90nm CMOS Technology" offers a detailed comparison of the 8-transistor (8T) SRAM design against the traditional 6-transistor (6T) configuration, highlighting their advantages in 90nm technology It examines power consumption and delay characteristics under various operating conditions, providing crucial insights into the testing processes for 6T SRAM cells across different technologies and tools Additionally, the analysis of waveform-based results deepens the understanding of these SRAM designs.
The paper "Design of SRAM Cell with Sense and Precharge Amplifiers" investigates the 6T SRAM design featuring a differential sense amplifier It details the schematic aspects of pre-charge and read-write operations, emphasizing the importance of these auxiliary components in verifying the bitcell's functionality This foundational research acts as a valuable reference for pre-simulation processes in 6T SRAM designs.
The research titled "Analysis of the Parasitic Capacitance Effects on the Layout of Latch-Based Sense Amplifiers for Improving SRAM Performance" utilizes low-voltage 22nm UMC CMOS technology to enhance latch-based sense amplifier (LSA) design It thoroughly examines the factors affecting post-layout performance and implements layout optimization techniques to reduce parasitic capacitance's impact on critical signal lines, including the data line and data line bar These optimizations can achieve a 15% reduction in power consumption and a 5% decrease in read delay time, highlighting the crucial role of layout decisions in enhancing circuit performance.
As a result these research publications provide a clearer and more thorough
This essay explores the intricacies of 6T SRAM circuit design, emphasizing the importance of adhering to industry standards and consulting empirical research for a comprehensive understanding It goes beyond merely replicating the schematic design by incorporating the layout design process, showcasing how Synopsys tools can expedite this process Key concepts include layout creation, generating an HSPICE version of the schematic, and conducting LVS and DRC checks Additionally, the essay highlights the differences in managing layout views when working with TSMC 16nm technology.
FinFET
The three-dimensional FinFET design has superseded the traditional two-dimensional transistor structure in CMOS technology, effectively addressing subthreshold leakage caused by the gate's inability to fully halt channel flow FinFET technology enhances control by surrounding the channel with multiple gate sides, forming a fin structure composed of vertical silicon This structure is covered by a dielectric layer, such as oxide, with a metal or polysilicon gate positioned above it Current flows through the fin under the influence of gate voltage, while the source/drain fin is encased on three sides by the gate To create wider devices, fins are arranged in parallel, with their height directly influencing the device width, drawing a parallel to the top view of planar MOSFETs.
Figure 2 1: (a) The FinFET 3D structure; (b) Top views of FinFET [4]
As the channel length decreases below 20 nm, the performance advantages of FinFET technology become evident The I-V characteristics of FinFETs exhibit a theoretical resemblance to square-law behavior, which enhances the stability of high-intensity signals Figure 2-2 illustrates the I-V characteristics for 18 nm to 16 nm technology, as referenced in thesis [6].
Figure 2 2: IV characteristics of FinFET for an oxide thickness of two gates (m) 16 nm; (n) 17 nm; (o) 18 nm [6]
The I-V curve at a drain voltage of 1V is represented by the red line at a drain voltage of 0 05V the green line is used As can be observed it rises linearly before entering the saturation zone which is represented by a nearly flat curve
Figure 2 3: Comparison of conductance of FinFET and MOSFET [6]
MOSFETs experience various effects such as channel length modulation, subthreshold conduction, and current leakage, leading to power dissipation and reduced performance In contrast, FinFETs offer enhanced channel control due to their unique structure, providing a significant advantage over traditional MOSFETs.
FinFETs are considered a superior alternative to single-gate MOSFETs for applications with the same input voltage, as they provide enhanced conductance and efficiency, making them less susceptible to current leakage.
3 to see the conductance between FinFET and MOSFET
The selection of 16nm technology is ideal for testing and validating SRAM, as it effectively utilizes the FinFET structure first introduced at 20nm While less complex than newer technologies like 14nm and 10nm, the 16nm structure retains the advantages of FinFET, leading to a more streamlined research and testing process This reduced complexity results in fewer variables to manage, making 16nm the optimal choice for the project, allowing for quicker familiarization with tools and efficient SRAM layout creation.
TSMC 16nm technology nodes
In November 2013, TSMC became the first foundry to produce a fully functional 16nm FinFET networking processor, marking a significant milestone in semiconductor technology Following this achievement, TSMC introduced the 16nm FinFET Plus (16FF+) process, which offered enhanced performance and rapid yield ramp, leading to volume production by July 2015 By 2017, the versatile 16FF+ technology had made notable advancements in automotive applications.
In the second quarter of 2016, TSMC launched its 16nm FinFET Compact Technology (16FFC), which offers 50% faster performance and 60% lower power consumption compared to its 20nm SoC process This technology stands out in the industry, enabling new applications such as cloud gaming, 4K120 digital TV, and video streaming Continuous improvements in performance, power, and area (PPA) are exemplified by the N16 process The latest innovation, 16nm FinFET Compact Plus (16FFC+), provides enhanced speed and power efficiency, ensuring flexibility and efficiency for future product developments.
TSMC's 16nm FinFET technology represents a significant breakthrough in semiconductor innovation, effectively tackling issues of power consumption and performance While the topic has been discussed previously, it remains timely to reassess and evaluate its impact and advancements in the industry.
16FF technology in the essay based on the release timeline.
Read/Write function of 6T SRAM
The structure of 6T SRAMs is fundamental to memory architecture, with the SRAM cell being a key component A typical SRAM cell consists of a latch circuit formed by two cross-coupled inverters, enabling read and write operations through access transistors connected via two pass-gates In its unaccessed state, the memory cell, or bit cell, is isolated by these access gates When powered, an SRAM cell provides both read/write access and data storage capabilities.
Figure 2 4: The SRAM structure theoretical [5]
The 6T SRAM cell features cross-coupled inverters, as illustrated in Figure 2.4, where inverter D2 P2 receives input from inverter D1 P1 and vice versa Access transistors A1 and A2 facilitate read and write operations by driving the target value and its complement onto the bitlines, bit and bit_b, while raising the wordline During the write process, the cell is overwhelmed by new data, and for reading, the bitlines are precharged to a high level and allowed to float When the wordline is activated, either bit or bit_b pulls down to indicate the stored data value The primary design challenges include minimizing the SRAM size while ensuring the circuitry is robust enough to maintain state during read operations and weak enough to be easily overwritten during write operations.
Figure 2 5: SRAM waveform of Read operation [5]
The 6T SRAM read operation, illustrated in Figure 2.4, begins with both bitlines precharged to a high state If Q is set to 0 and Q_b is at 1, the driver transistor D1 and access transistor A1 pull down the bitline when the wordline activates As a result, node Q typically rises; however, to maintain read stability and ensure Q remains below the switching threshold of the P2/D2 inverters, D1 must be stronger than A1 This balance prevents Q from rising excessively, allowing for the successful reading of a 0 onto the bit, as demonstrated in the waveforms of Figure 2.5.
Figure 2 6: SRAM waveform of Write operation [5]
The write operation of an SRAM cell involves setting Q to 1, starting with Q at 0 To achieve this, the write driver pulls the complementary bitline (bit_b) low while keeping the bitline (bit) high and floating Due to read stability constraints, bit cannot drive Q high through access transistor A1, necessitating the pulling of Q_b low via access transistor A2 For this to occur, pull-up transistor P2 must be weaker than A2 to allow Q_b to drop sufficiently, a condition referred to as writability Once Q_b is low, the pull-up transistor P1 activates, successfully raising Q high and cutting off the driver transistor D1.
Theoretical Framework
Custom Compiler TM is an advanced tool designed for the creation of unique digital mixed-signal and analog integrated circuits (ICs) within the Synopsys Custom Design Platform It excels in design entry simulation and layout editing, particularly for cutting-edge technologies such as FinFET Key features include automatic wiring symbol generation and easy parameter editing, fostering a productive work environment The tool also offers essential debugging capabilities, such as a hierarchical net tracer and a power domain analyzer With integrations to Synopsys PrimeSim TM, WaveView, HSPICE, and various third-party simulators, it facilitates comprehensive analysis and visualization, supporting both text and schematic views.
Custom Compiler enhances productivity with its user-friendly layout editing features, particularly for complex designs, through visually-assisted automation (VAA) It supports reusable layout templates, pattern routing, and a symbolic editor, streamlining the design process Built-in verification tools, leveraging the Synopsys StarRC™ engine, detect layout errors and ensure compliance with design rules by extracting parasitic capacitance Additionally, the integration with IC Compiler™ II allows for seamless transitions between custom and digital design phases.
Custom Compilers offer a user-friendly and adaptable environment that facilitates seamless integration with third-party tools and enhances adoption The platform is customizable through TCL, Python, and C++, leveraging the OpenAccess database for optimal performance Additionally, Custom Compiler iPDKs are available to support complex node processes.
Furthermore, because of their accuracy and strong validation capabilities, custom compilers are frequently used for designing memory layouts and Intellectual Property (IP) circuits
Custom WaveView™ offers a versatile solution for analyzing waveforms and simulations in mixed-signal and analog integrated circuits It includes various analysis features, supports multiple simulator formats, and enables quick loading, scrolling, and zooming of large waveform files.
Custom WaveView provides a comprehensive environment for presenting and evaluating analog and mixed-signal simulation outcomes It allows designers to display, measure, manipulate, and save simulation results by integrating time and frequency domains in one session The tool's capability to read results from multiple simulators, convert analog waveforms to digital formats, and export them for digital simulations enhances its versatility With features like the HSPICE MEASURE command and parametric plots, it effectively manages large simulation data while supporting various simulators on a single platform Advanced display and analysis capabilities, along with a Tcl API for complex post-processing scripts, facilitate transient AC RF and mixed-signal analysis, enabling flexible waveform grouping from different simulations.
The Custom Designer SE schematic editor offers cross-probing support, while Custom WaveView integrates seamlessly with Synopsys Galaxy Custom Designer®, allowing users to read waveform files from Cadence Mentor and Synopsys simulators Its user-friendly interface enables easy drag-and-drop of signals into a customizable display window with multiple panel arrangements, facilitating efficient browsing of waveform data hierarchies Key features include a hierarchy browser, signal list drag-and-drop functionality, pattern-matching signal search, user-definable hotkeys, a list of recently opened files, and options for saving and restoring sessions Additionally, the tool supports various waveform types, such as digital, analog, Smith chart, polar plot, and eye diagrams.
A variety of measurement tools are also available with Custom WaveView such as an infinite number of cursors for interactive on-screen measurements monitors for intricate
The measurement tool offers over 35 types of measurements, including derivative and RMS values, that continuously update with new simulation results This functionality simplifies design analysis by providing robust tools for visualizing and analyzing waveforms across various simulation environments.
Pre-charge circuits are essential for bit-line pre-charging and equalization, significantly improving access times During idle periods, these circuits elevate the bit lines (BL and BLB) to a mid-level voltage, facilitating the equalization of bit-line capacitances This process ensures that the sense amplifier can accurately detect signals from memory cells during read operations By minimizing voltage differences between the bit lines, equalization is crucial for precise reading Additionally, pre-charging the bit lines enhances overall system performance by reducing the time needed for subsequent read and write operations.
Figure 2 9: Pre-charge schematic circuit
Two transistors were used in the past to implement pre-charge circuits As mentioned
Recent advancements in transistor design have led to the development of a more resilient three-transistor configuration, which includes an additional redundant transistor (M1) This innovative design enhances robustness against defects and reduces sensitivity to resistive-open faults The extra transistor M1 plays a crucial role in equalizing the bit lines, thereby improving both reliability and performance, while transistors M2 and M3 are responsible for connecting the bit lines to the supply voltage (Vdd) for pull-up functionality.
To optimize pre-charge circuit performance, it is essential to consider several factors The equalization transistor (M1) plays a crucial role in ensuring precise read operations by eliminating asymmetric flaws and reducing voltage variations across bit lines Load transistors (M2 and M3) connect the bit lines to Vdd during read operations, maintaining nearly equal potential and limiting voltage variations to ≤80mV for reliable SRAM cell reads Additionally, NFIN transistors can pre-charge bit lines to Vdd - Vth, facilitating faster detection of single-ended bit lines, although this comes with longer pre-charge times and decreased noise margins.
Pre-charge circuits are vital in SRAM design, as they minimize access times and guarantee reliable read operations The evolution from two-transistor to three-transistor layouts highlights significant advancements in semiconductor technology Ongoing research and development in pre-charge circuit optimization will be critical to meet increasing performance and reliability demands.
The design outlined in [13] forms the foundation for the Write Driver blocks design, simplifying the data writing process into 6T SRAM, as detailed in Chapter III, Section.
1 Write drivers in SRAM architecture assist in writing data by controlling the bit lines (BL and BLB) with access transistors By pulling BL to ground (GND) and maintaining BLB at the supply voltage (Vdd) the write driver records a logic 0 in the memory cell
To write a logic 1 into the memory cell transistors M16 and M17 push BLB down to GND and pull BL up to Vdd respectively
Figure 2 10: Write Driver schematic circuit
To write data into an SRAM cell, data is applied to the input pin while selecting the cell using its row and column coordinates The targeted address column is activated, and the write enable line is turned on, allowing data to be entered into the cell After the data is written, the word line is deactivated to conserve energy.
Driver transistors are engineered with higher resistance compared to the lower resistance transistors in memory cells, facilitating the seamless replacement of old data with new Accurate transistor sizing is crucial for the optimal functioning of the entire SRAM design.
DESIGN IMPLEMENTATION
Flow Chart
This chapter aims to elucidate the approach within the context of the theoretical framework discussed in Chapter 2 Additionally, it will demonstrate that the functionalities observed in both the Pre- and Post-simulation phases align with the proposed theory by analyzing their respective waveforms.
The steps involved in creating this thesis are broken down into a flow chart The two primary steps are Pre-sim and Post-sim as illustrated in the figure below
To design a 6T SRAM cell using Synopsys tools, start by creating the schematic Ensure that the auxiliary circuits, including the precharge circuit, differential sense amplifier, and write driver, are incorporated to test the read and write functionalities Finally, integrate these individual schematics to form a complete and cohesive design.
To ensure the accuracy of your schematic, run waveform simulations in WaveView For compatibility with Synopsys simulation tools, modify the circuit and save it as an SP file in HSPICE format Synopsys provides partial support for converting the netlist schematic to HSPICE.
The design of the 6T SRAM cell layout should follow the confirmation of pre-simulation waveform behavior It is essential to ensure that the layout adheres to Layout vs Design Rule Checking (DRC) and Schematic (LVS) conformance requirements These checks validate that the layout meets necessary specifications and aligns with the schematic Both DRC and LVS must successfully pass before moving on to the extraction step.
During the extraction phase, a Standard Parasitic Format (SPF) file is generated This file can be opened in HSPICE to perform post-layout waveform simulations, which incorporate parasitic effects to validate the design effectively.
Figure 3 1: Flow chart describe Pre-sim and Post-sim of 6T SRAM
In summary, the design and verification of a 6T SRAM cell involve redrawing schematic simulation waveforms, creating the layout, and ensuring compliance with DRC and LVS standards, followed by extraction and post-layout simulation.
Pre-sim
The circuit operation consists of three key components: the Pre-charge block, the Differential Sense Amplifier, and the Write Driver block An image illustrates the detailed interaction and functionality of these components working in unison.
Figure 3 2: Schematic circuit for testing the function of 6T SRAM
The Pre-charge block plays a crucial role in preparing the bit lines (BL and BLB) before they connect to the memory cells This block ensures that the bit lines are balanced and precharged, facilitating optimal performance in data retrieval and storage.
To initiate the process, a voltage of 0.8V is applied to the PRE pin, causing transistors M3 and M2 to charge the bit lines Meanwhile, transistor M1 ensures voltage balance between the two bit lines by charging the lower voltage side and discharging the higher voltage side until the voltages are nearly equal.
In a 6T SRAM memory cell, the bit lines can only pass through once the word line (WL) is activated, as illustrated in Figure 2.12 of Chapter 2 When the WL is activated, transistors M8 and M9 facilitate the transmission of the value to be stored in the memory cell, enabling the flow of data through the bit lines.
M4 M5 M6 and M7 combine to form an inverter loop which is the memory cell
The Differential Sense Amplifier enhances the weak signals from the bit lines to accurately read the values stored in memory cells By amplifying these minute signals, the amplifier ensures stronger and more reliable outputs, which are then sent to Data_out For example, if the memory cell holds a 0 between M4 and M5, a 1 will appear at the node between M6 and M7, activating M8 and M9 in the process.
When WL is activated, M4 is enabled while M5 is disabled by a value of 1 Simultaneously, M6 is turned off and M7 is activated Consequently, the memory cells with a value of 0 can now be accessed and outputted through Data_out, due to BL transitioning to 0 and BLB to 1.
The Write Driver circuit manages the writing process to SRAM, facilitating the erasure of previous data and the input of new data when the Write Enable (WE) signal is activated For example, when WE is enabled and Data_in is 0, M12 turns off while M13 turns on, resulting in an output of 1, which subsequently returns to 0 after passing through M14 and M15 Different values are then loaded into BLB and BL, with M16 and M17 receiving 0 and M18 and M19 receiving 1, respectively Consequently, the new data is successfully written into the memory cell by switching BL to 0 and BLB to 1.
To generate simulation waveforms for the 6T SRAM functional block, it is essential to create a schematic and convert it into HSPICE format, saving it as an SP file The basic structure of the HSPICE format, as illustrated in Figure 3.3, outlines the assumptions made for the simulation case of the 6T SRAM.
Figure 3 3: HSPICE format sample for Pre-sim
Writing in HSPICE format consists of three main sections: transient analysis, defining waveform and describing netlist
The describe netlist section involves converting what you have drawn in the schematic view It includes parts such as: Instance_name: a unique name you assign to the
Transistors are essential electronic components characterized by four key terminals: the drain, gate, source, and bulk (or body) They come in various types, including nfin and pfin transistors, with parameters such as width and length significantly influencing their performance Understanding these elements is crucial for optimizing transistor functionality in electronic circuits.
The wire names, listed in order, indicate connection points For example, in the figure,
The designation “x1 4 1 5 0” indicates that the transistor labeled x1 has its Drain connected to wire 4, the Gate to wire 1, and both the Source and Bulk to wire 0 This systematic arrangement facilitates the identification of connection points in a manner akin to a schematic diagram.
Sections 2 and 3 are straightforward due to their clear format, listing each distinct name for waveform simulation in the first column of section 2 The second column identifies the input wire to be controlled, while the final section displays the corresponding waveform The pulse command is utilized to generate a square wave, with the DC type easily defined for VDD as demonstrated in the image Additionally, the tran command establishes a time limit, producing waveforms in 0.1 ns increments over a 20 ns duration starting from 0.
Converting schematic views to HSPICE can be challenging, but Synopsys tools facilitate this process by offering predefined presets To minimize discrepancies between the schematic view and the netlist, it's essential to understand the format and meticulously verify connections Mastering the HSPICE netlist format significantly accelerates the design drawing and verification process during Pre-simulation Additionally, Figure 3.4 illustrates the read and write operations of 6T SRAM systems.
Figure 3 4: Waveform of read/write function for 6T SRAM in Pre-sim mode
From top to bottom word, WE, SE, Data_in and Data_out are the waveforms shown in the figure
The signal indicated by the orange rectangle shows that Data_in remains at zero when the WE pin reaches a high level of 0.8 V Consequently, as SE increases, the Data_out output continues to stay at zero.
In the upper left corner of the signal, indicated by the orange rectangle marked with the number 2, the Data_in is at 1 when the WE pin rises When the SE signal is activated, the Data_out output should promptly change to 1, returning to 0 only when the signal is deactivated.
During the read/write process, the word pin, also known as WL, must remain at 0.8V
The schematic circuit effectively simulated the read and write functions of the 6T SRAM, demonstrating its accuracy and theoretical validity The circuit is now ready to advance to the layout design phase.
Post-sim
The post-simulation phase following pre-simulation is essential and must not be overlooked In this process, we will create the layout for 6T SRAM bit cells, utilizing FinFET technology instead of traditional CMOS, in accordance with TSMC's 16nm technology It is crucial to accurately calculate the source and drain widths during the layout design The fundamental layers that constitute the nfin/pfin in TSMC's 16nm process are illustrated in Figure 3.5 below.
Figure 3 5: 6T SRAM functional block - first layout designs
The finished 6T SRAM layout design is displayed in the picture above with the
The article discusses a differential sense amplifier block, which is followed by the bit cell block, write driver block, and pre-charge block It highlights that the bulk nodes for each FinFET are indicated by the small blocks labeled VDD and VSS on the right side of the image.
The design is limited to a 1x1 configuration, as it only accommodates a single cell layout Notably, the layout allows for a shared bulk terminal for all nfin/pfin connections, significantly reducing the area required since over ten nfin and pfin can utilize just two bulk terminals The total area in the 2D form measures 3.636 µm².
The initial one-bit cell layout proved unfeasible due to inefficient routing of the primary wires, BL and BLB, which hindered the potential for expanding the layout to 2x2 or 4x4-bit cells Consequently, a revised design was necessary to optimize space utilization and facilitate future scalability.
BL and BLB lines are easier to route because of the vertical layout
The vertical layout structure illustrated in Figure 3.6 features a sequential arrangement from top to bottom, comprising the Pre-charge block, Write Driver block, bit cell block, and Differential sense amplifier block.
A total of eight bulk terminals are necessary to represent each block in the design: two for the Pre-charge block, two for the Write Driver block, two for the bit cell block, and two for the Differential sense amp block The shared bulk terminal for pfin must be located within the nwell region, preventing the combination of terminals into a single block Due to the vertical layout design, it is not feasible for the nwell to cover every pfin The main function of the bulk terminal in nfin is to ensure equilibrium with the number of bulk terminals in pfin.
Figure 3 6: 6T SRAM functional block - second layout designs
The second design features a total 2D area of 4.501 um², with an enhanced vertical layout that increases overall space The routing of BL and BLB lines has been simplified compared to the previous design, eliminating the need for complex roundabout paths around other wires This ease of adjustment allows for straightforward expansion of bit cells from 1x1 to configurations such as 1x2, 1x3, 2x2, or even 4x4, streamlining the design process.
Post-simulation (Post-sim) writing, like Pre-simulation (Pre-sim), is formatted in HSPICE, but it uniquely incorporates the output from the extraction step of the SPF file, rather than defining each transistor individually When defining a scenario, the SPF file encompasses not only temperature settings but also the specifications for resistors and capacitors for each metal layer, modeling normal conditions based on a typical environment Once the SPF file is established, Sections 2 and 3 are processed similarly to Pre-sim, requiring only a change in names to align with the wire names detailed in the SPF file.
Figure 3.7 illustrates the waveform results of the 6T SRAM from the Post-simulation process include both designs
Figure 3 7: Waveform of read/write function for 6T SRAM in Post-sim mode
The output waveform arrangement resembles the Pre-simulation setup Word, WE,
The signals SE, Data_in, and Data_out flow from top to bottom, with two distinct signals present on the data_out line The purple signal originates from the Second Design, while the pink signal is associated with the First Design.
The read and write functions accurately correspond to the Pre-simulation waveforms When the Write Enable (WE) is activated (set to 1), the value of Data_in is read Subsequently, when the Select Enable (SE) is activated, this value is sent to Data_out Throughout the read/write process, the word line maintains its value until the operation is complete.
With no delays taken into account this completes the Post-simulation procedure and demonstrates that the waveform’s changes in logic levels closely resemble those in the Pre-simulation
Both arrangement designs taken together satisfy the 6T SRAMs read/write capabilities In Chapter 4 we will go over the delay analysis and explanations.
Discussion
In this project, a variety of Synopsys tools played a vital role in completing the Pre-sim and Post-sim runs for the 6T SRAM The ability to generate netlists in HSPICE format significantly accelerates the learning curve for beginners using HSPICE for simulation Additionally, a valuable feature for estimating wire capacitance and resistance enhances the overall efficiency of the simulation process.
Custom Compiler provides unique features for schematic drawing, although this functionality was temporarily set aside due to limitations in theoretical understanding and analysis One significant advantage is the ease of setting maximum metal layer limits prior to layout initiation, which greatly benefits those experienced in layout design and parameter calculations.
Custom WaveView, while requiring a complex input setup, offers a user-friendly interface packed with essential instruments for measuring amplitude, waveform comparison, and delay The Measure Tool encompasses critical measurements like frequency, period, jitter, and peak-to-peak values, facilitating easier analysis and interpretation of waveforms without delving into complicated formulas.
PERFORMANCE ANALYSIS
Different between Pre-sim and Post-sim
Simulations are essential for calculating and analyzing variations in delay, power consumption, and losses associated with resistance and capacitance parameters in wires during Post-simulation Additionally, they facilitate both Pre-simulation and Post-simulation processes to verify that functionality operates as intended at every stage.
The figure below shows the results of the Data_out waveforms in Pre-simulation and Post-simulation:
Figure 4 1: Waveform of Data out between Pre-sim and Post-sim modes
The image illustrates two layout designs alongside the schematic of Data_out, with the yellow line indicating the first layout design, the blue line representing the second layout design, and the red line depicting the schematic.
The Data_out output transitions from 0 to 1 across three signals, maintaining a steady voltage of 0.8V in an ideal state without any delays or parasitic capacitance However, the current flowing through the device is diminished due to the layout design, which introduces resistance and parasitic capacitance on the wires In comparing designs, the second design shows an output voltage drop to 770mV, while the first design experiences a drop to 774mV, indicating that the vertical design leads to a greater reduction in voltage compared to the horizontal design.
Despite the extra resistance and parasitic capacitance delays in the layout it is found
The schematic signal experiences a delay compared to the layout signals, with the voltage in the schematic surpassing 0.1V at 47.61 ns, while the layout outputs remain below this threshold Despite this early voltage change, the schematic switches at a significantly slower rate, requiring 12.6 ns to complete its transition.
0 to 0.8V, 6.57ns for the Layout to produce the first design, and 6.51ns for the second design
As for the delay between the two layouts, the second design is approximately 233fs faster than the first design
Figure 4 2: BLB signal between Pre-sim and Post-sim modes
Figure 4 3: BL signal between Pre-sim and Post-sim modes
The observed discrepancy in circuit performance likely stems from suboptimal layout design, particularly due to bulk connections and wire delay issues In an ideal schematic, when data_in is at 1 (0.8V), both BL and BLB wires are approximately at Vdd/2; however, when data_in is 0, BLB is around 0.7V while BL drops to about 0.3V In the layout design, BLB approaches Vdd/2 at 0.8V data_in, but BL only reaches Vdd/2 when data_in is at 0, indicating a potential delay in the Data_in path through the inverter affecting BL and BLB signals.
When Data_out is read as 1, the schematic BL wire voltage shifts from 501mV to 566mV, and the layout BL wire voltage changes from 739mV to 758mV Additionally, variations in BLB voltage levels have a minor impact on the output switching speed, which contributes to the observed outcomes.
Delay read/write and Power
In addition to verifying that the 6T SRAM is functioning steadily this section looks at how Synopsys tools facilitate result evaluation and analysis
Figure 4 4: Delay read of Pre-sim
Figure 4 5: Delay read of Post-sim – first layout design
Figure 4 6: Delay read of Post-sim – second layout design
With the circuit operating at a frequency of 50MHz the read and write delays were measured in both the post- and pre-simulation phases Measured from the rising edge of
The read delay is defined as the time taken for Data_out to present the result As illustrated in the figure, engaging the SE rising edge results in a pre-simulation time of approximately 11.5 ps, while the post-simulation times are 8.61 ps for the first layout design and 8.38 ps for the second layout design This discrepancy arises because, although Data_out transitions earlier during pre-simulation, it requires around 30 ps for the rise time to shift from 0 to 1 in pre-simulation, compared to just 15 ps in post-simulation.
Figure 4 7: Delay write of Pre-sim
Figure 4 8: Delay write of Post-sim – first layout design
Figure 4 9: Delay write of Post-sim – second layout design
The write latency for pre-simulation and post-simulation shows a slight variation, with the schematic design experiencing a write delay of only 6.43 ps, while the first and second layout designs have delays of 8.06 ps and 7.82 ps, respectively This discrepancy is likely attributed to the different switching voltage levels and wire delays at the 6T SRAMs Q and Q_b nodes Additionally, the longer write delays in the layout designs can be explained by the smaller rate of voltage change at Q_b in the schematic design compared to the layout designs.
To calculate power, we utilize the fundamental formula 𝑃 = 𝐼 × 𝑈 By employing Synopsys tools, we measured the current during active operation as well as the leakage current when the circuit is in an idle state.
Figure 4 10: Current minimum value at 50MHz of Pre-sim
Figure 4 11: Current minimum value at 50MHz of Post-sim – first layout design
Figure 4 12: Current minimum value at 50MHz of Post-sim – second layout design
In a frequency analysis at 50MHz, the dynamic current measured in the Pre-simulation phase was 117uA, whereas the Post-simulation phase recorded a reduced value of 87uA for the first design The second design exhibited a dynamic current of 97.1uA.
Figure 4 13: Current minimum static value of Pre-sim
Figure 4 14: Current minimum static value of Post-sim – first layout design
Figure 4 15: Current minimum static value of Post-sim – second layout design
In the Pre-simulation phase, the leakage current remains stable at 99.2nA in a static state However, during the Post-simulation phase, there is a slight increase in the current value.
Figures 4.14 and 4.15 illustrate that in the Post-simulation phase, the two layout designs show minimal differences However, the first layout design exhibits superior current control, with a measurement of 237nA, compared to the second layout design's current of 256nA.
Below is a table showing the power consumption results of Pre-simulation and Post- simulation at different frequencies:
Frequency Pre-sim Power Post-sim Power
Post-sim Power (Second design)
An analysis of various design layouts at different frequencies reveals that the schematic design exhibits a smaller power discrepancy compared to the other two designs At 50MHz, the schematic design shows slightly higher power consumption, resulting in a power disparity of 6.82x10^-5 W, while the first layout design has a difference of 9.62x10^-5 W and the second layout design shows a difference of 9.51x10^-5 W between 50MHz and 1GHz.
The small power discrepancy observed is due to the dynamic state current remaining in the microampere (uA) range while the voltage is at 0.8V When averaging both the static and dynamic state currents and multiplying by 0.8V, the resulting power values show minimal change Additionally, as illustrated in Figures 4.10 and 4.11, current values fluctuate during read and write operations, particularly during the rise and fall times of signals like WE, SE, and DATA_IN When these switching events occur in quick succession, the circuit may experience undershoot or overshoot, leading to minimum values that are closer than when measuring the average current However, these fluctuations do not significantly impact the overall power assessment of the three designs.
The first layout design demonstrates lower power consumption compared to the second design While the first layout also exhibits slightly better performance in read and write delays regarding power usage, this analysis is limited to a single 1x1 SRAM cell Scaling up the design could significantly complicate the arrangement of the BL and BLB lines if the first layout design is adopted.
The trade-off between Power, Performance, and Area (PPA) presents significant challenges; while increasing area typically enhances power and performance, reducing area can lead to greater delays and increased power consumption Additionally, careful attention must be paid to voltage drop when minimizing area.
This paper ensures a comprehensive flow from Schematic Design to Layout Design, covering all stages from Pre-simulation to Post-simulation, while utilizing 16nm technology instead of the latest 2nm or 3nm advancements It highlights the importance of self-learning in circuit design, focusing on essential skills such as reading HSPICE netlists, creating schematics and layouts, and conducting circuit analysis and verification Additionally, it addresses the critical roles of LVS and DRC, as well as the application of phenomena like Latch-up and ESD in formulating DRC rules.
The thesis successfully completed the read and write procedures of 6T SRAM, utilizing schematic and layout diagrams Key operations were facilitated by the implementation of write drivers and differential sense amplifiers, enhancing SRAM functionality.
The layout design of the 6T SRAM functional block was successfully completed using Synopsys tools Detailed procedures for conducting Design Rule Check (DRC), Layout Versus Schematic (LVS), and extraction checks were established and executed.
The thesis provides a comprehensive guide on writing netlist structures in HSPICE format Mastering HSPICE netlist writing allows for rapid modifications to circuit architecture, significantly reducing editing time by eliminating the need for GUI interaction.
At various frequency points waveforms were produced and the power and delay were assessed
Access restrictions and limitations prevent the use of technologies below 16 nm, leading to insufficient analysis and evaluation due to the lack of comparative data with other technologies.