Due to its powerful brainlike parallel computing and efficient data processing capabilities, memristors are considered to be the core components for building the next generation of artificial intelligence systems. In this study, the CeOxWOy heterojunction is employed as the functional layer, and various metal materials are utilized as the top electrode to fabricate the memristor. The results indicate that the memristive performance of the AgCeOxWOyITO device can be improved by using Ag as the top electrode. By studying the conductivity mechanism of the device, a conductivity model is established that regulates oxygen vacancies and Ag conductive filaments. Furthermore, using the asprepared memristor, it is constructed four basic digital logic circuits: OR, AND, XOR, and XNOR, as well as a half adder and a full adder that can be used for digital arithmetic operations. Specifically, an oddeven checker is developed based on XOR and XNOR logic circuits to verify the correctness of data transmission. Finally, it is also designed and implemented a cryptographic array based on a memristor, which can be applied to encrypt and decrypt a series of numbers and images. Therefore, this work extends the application of memristor toward digital circuits, information transmission, data processing and image security encryption.
Trang 1RESEARCH ARTICLE
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Odd/Even Checker and Encryption/Decryption of Image
Applications
Jiangqiu Wang, Hongyan Wang,* Zelin Cao, Shouhui Zhu, Junmei Du, Chuan Yang,
Chuan Ke, Yong Zhao, and Bai Sun*
Due to its powerful brain-like parallel computing and efficient data processing
capabilities, memristors are considered to be the core components for
building the next generation of artificial intelligence systems In this study, the
CeO x /WO y heterojunction is employed as the functional layer, and various
metal materials are utilized as the top electrode to fabricate the memristor.
The results indicate that the memristive performance of the
Ag/CeO x /WO y /ITO device can be improved by using Ag as the top electrode.
By studying the conductivity mechanism of the device, a conductivity model is
established that regulates oxygen vacancies and Ag conductive filaments.
Furthermore, using the as-prepared memristor, it is constructed four basic
digital logic circuits: OR, AND, XOR, and XNOR, as well as a half adder and a
full adder that can be used for digital arithmetic operations Specifically, an
odd/even checker is developed based on XOR and XNOR logic circuits to
verify the correctness of data transmission Finally, it is also designed and
implemented a cryptographic array based on a memristor, which can be
applied to encrypt and decrypt a series of numbers and images Therefore,
this work extends the application of memristor toward digital circuits,
information transmission, data processing and image security encryption.
1 Introduction
With the continuous development of artificial intelligence
tech-nology, the demand for computer processing energy efficiency
is increasing.[ 1,2 ] Since the current computer based on the von
J Wang, H Wang, S Zhu, J Du, C Yang, Y Zhao
School of Physical Science and Technology
Key Laboratory of Advanced Technology of Materials
Southwest Jiaotong University
Chengdu, Sichuan 610031, China
E-mail: hongyanw@swjtu.edu.cn
Z Cao, B Sun
Frontier Institute of Science and Technology (FIST)
Xi’an Jiaotong University
Xi’an, Shaanxi 710049, China
E-mail: baisun@xjtu.edu.cn
The ORCID identification number(s) for the author(s) of this article
can be found under https://doi.org/10.1002/adfm.202313219
DOI: 10.1002/adfm.202313219
Neumann architecture has independent storage and computing units, frequent data transmission between the central process-ing unit (CPU) and memory will lead
to bottlenecks in information processing speed.[ 3,4 ]As a novel electronic device, the memristor is called the fourth basic circuit element whose internal conductive state de-pends on the history of electrons or ions.[ 5,6 ]
These functions enable data to be processed
in memory, making it a core component
of brain-like computing architectures.[ 7–9 ]
Generally, a memristor is a two-terminal device with a sandwich structure, in which
an insulator or semiconductor is usually used as a functional layer, and a metal or conductive oxide is used as the top and bottom electrodes.[ 10–12 ]When a voltage is applied, the resistance state of the mem-ristor can be switched between the high resistance state (HRS) and the low resis-tance state (LRS).[ 13 ]Up to now, many ma-terials have been reported to be used as the functional layer of memristor, such
as metal oxides, perovskite, ferroelectrics, 2D materials, organic materials, etc.[ 14–19 ]When different func-tional materials are used, the performance of the memris-tor varies greatly, which broadens the application range of memristors.[ 20 ]However, the diverse selection of materials also increases the difficulty of studying the mechanism of resistive
Z Cao, B Sun Micro-and Nano-technology Research Center State Key Laboratory for Manufacturing Systems Engineering Xi’an Jiaotong University
Xi’an, Shaanxi 710049, China
C Ke, Y Zhao Key Laboratory of Magnetic Suspension Technology and Maglev Vehicle (Ministry of Education)
School of Electrical Engineering Southwest Jiaotong University Chengdu 610031, China
Trang 2switching (RS) characteristics RS characteristics are related to
the functional layer material and its thickness, electrode
mate-rial, and the environment of the device.[ 21–23 ]Among them, the
most widely used functional layer material in the manufacture of
memristors is binary metal oxides Many memristors based on
binary metal oxides not only have excellent durability and
reten-tion advantages, but also are well compatible with current
com-plementary metal oxide semiconductor (CMOS) devices, which
can combine memristors with circuits and promote large-scale
and high-density integration of memristors.[ 24,25 ]
In recent years, the memristor based on the rare earth metal
oxide cerium dioxide (CeO2) has attracted much attention due
to its unique performance.[ 26–29 ] CeO2 is a typical n-type
semi-conductor, of whose main crystal defect is oxygen vacancy, and
plays an important role in memristive devices CeO2has a high
dielectric constant (≈26), which has good application prospects in
nonvolatile memory and neuromorphic computing.[ 30,31 ]
How-ever, the preparation of a memristor based on CeO2 still has
some problems, such as it is difficulty in controlling the
dis-tribution of cerium cation and oxygen vacancy in CeO2 film,
large formation voltage, small resistance window, and large
op-erating current Yan et al used BaTiO3/CeO2 thin films to
pre-pare a silicon-based memristor with epitaxial vertically arranged
nanostructures, which can achieve five state storage function and
a durability of up to 109 cycles.[ 32 ] Further, the convolutional
neural network was built based on the device to identify the
CIFAR-10 dataset, and the recognition rates of online and
of-fline learning reached 90.03% and 92.55% respectively Zhou et
al prepared a photoelectric memristor with two terminal
struc-tures based on CeOx/ZnO heterostructure, and tested its
recog-nition, storage, and processing under visible light of 405 nm,
indicating that it has great potential applications in artificial
vi-sion systems.[ 33 ] In addition, Yang et al.[ 34 ]prepared a
memris-tor device with Ag/TiOx/CeOy/FTO structure, in which it was
found that the device shows volatile at low voltage, but it shows
nonvolatile memory behavior at high voltage with typical
mem-ristive characteristics accompanied by negative differential
resis-tance effect in the range of 3.5–4.0 V Therefore, in the above
works, the performance of the memristive devices has been
sig-nificantly improved by introducing a double-layer
heterostruc-ture due to the interface interaction formed by different material
layers
In this work, a memristor with a two-terminal structure was
prepared based on the CeOx/WOy bilayer heterojunction as a
functional layer by magnetron sputtering, which shows a digital
RS behavior with outstanding durability and retention
character-istics By fitting the I–V curves in a double logarithmic form, it
can be proposed that the mechanism of RS characteristics of the
Ag/CeOx/WOy/ITO device should be attributed to
space-charge-limited current (SCLC) and Schottky emission In addition, four
basic OR, AND, XOR, and XNOR digital logic circuits were
con-structed, as well as half-adders and full-adders that can be applied
to digital arithmetic operations Further, we also developed an
odd/even checker based on the XOR and XNOR logic circuits to
verify the correctness of data transmission Finally, a
memristor-based cryptographic array was constructed and implemented for
encrypting/decrypting digital strings and images These results
expand the applications of memristors in the fields of
informa-tion transmission and data security encrypinforma-tion
2 Results and Discussion
In this work, a memristor with the Ag/CeOx/WOy/ITO structure was fabricated The photograph of the as-prepared memristive
device is shown in Figure 1a, and the structural model of the de-vice and the schematic diagram of the electrical testing process are shown in FigureS1a(Supporting Information) To further un-derstand the thickness of the device, the cross-sectional scanning electron microscope (SEM) image confirms the thickness of the CeOx/WOylayer is ∼232 nm in Figure1b, in which it can be seen that the functional film in the SEM image was deposited with CeOxand WOybilayer films The surface of CeOx/WOybilayer film was dense and crack-free as exhibited in FigureS1b (Sup-porting Information) FigureS2(Supporting Information) shows the different elemental distributions in the CeOx/WOyfilm, and the energy dispersive spectroscopy (EDS) spectrum confirms the content of the O, W, and Ce elements is ≈71.16%, 10.69%, and 18.16% in Figure1c Besides, the X-ray diffraction (XRD) analy-sis was performed to determine the structure and composition
of the functional layer of the device The XRD spectrum fea-tured in Figure1dshows intensive peaks attributed to ITO and CeO2, while the WO3(200) crystal plane is represented by a peak
at 33.6° The crystal structures of CeO2and WO3 are shown in FigureS1c(Supporting Information), where the red balls repre-sent O atoms, the yellow balls reprerepre-sent Ce atoms, and the green balls represent W atoms
In particular, the X-ray photoelectron spectroscopy (XPS) was used to analyze the chemical composition and surface chemical states of bilayer films made of CeOx and WOy, and the survey spectrum of the CeOxfilm is depicted in FigureS1d (Support-ing Information) The XPS spectrum displays the presence of C,
Ce, and O elements, in which C elements can be classified as carbon-based contaminants Figure1edisplays the XPS spectra for the O 1s core level of thin films in CeOx At 530.29 eV, the fit-ted peak is assigned to lattice oxygen that is present in CeOx At the same time, the other peak at 531.55 eV is attributed to non-lattice oxygen, indicating the existence of oxygen vacancy defects
in the CeOxlayer As shown in Figure1f, the XPS spectra of Ce 3d core level of thin films in CeOx According to the XPS spectra,
it can be seen that the Ce element in the films is divided into two valence states of Ce4+and Ce3+ions The survey spectrum of the
WOyfilm is illustrated in FigureS1e(Supporting Information), revealing the existence of C, W, and O elements within the XPS spectrum, in which C elements can be classified as carbon-based contaminants Figure1gillustrates the XPS spectra of the O 1s core level in WOyfilms, in which the peak of 531.15 eV is as-sociated with lattice oxygen, specifically in WOy The other peak with a binding energy of 531.91 eV is related to non-lattice oxy-gen and corresponds to oxyoxy-gen vacancy defects in the WOylayer The XPS spectra of the W 4f core level in the WOythin film are shown in Figure1h According to the XPS spectra, three char-acteristic peaks at 36.02, 38.24, and 42.05 eV of the binding en-ergy can be observed, which correspond to W 4f7/2, W 4f5/2,and
W 4f3/2, respectively In addition, ultraviolet photoelectron spec-troscopy (UPS) was used to measure the work function of CeOx and WOy The energy spectra of the measurements are shown in Figure1iwith an applied bias voltage of −10 V The fitting pro-cess produced the work functions of CeOxand WOyto be 4.295 and 3.33 eV, respectively
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Figure 1 a) Photograph of the as-prepared memristive device b) The cross-section SEM image of the device c) EDS analysis of the CeOx/WOyfilm with the ITO electrode d) XRD pattern of CeOx/WOy/ITO film High-resolution XPS spectra and fitted spectra of e) O 1s and f) Ce 3d for the CeOxfilm High-resolution XPS spectra and fitted spectra of g) O 1s and h) W 3d for the WOyfilm i) The work functions of active layer CeOxand WOymeasured using UPS.
In order to investigate the effect of different electrodes on the
performance of the memristor, ITO was used as the bottom
elec-trode, CeOx/WOy heterojunction as the functional layer of the
memristor, and Ag, Ti, and TiN were selected as the top
elec-trodes First of all, the semi-logarithmic I–V curves with 200
cy-cles of the Ag/CeOx/WOy/ITO memristor at ±2 V is shown in
Figure 2a, in which it can be found that the memristive
perfor-mance is stable To explore the durability of the device, the HRS
and LRS resistance values of the device were tested at an applied
voltage of −0.1 V, as shown in Figure2b We can observe that the
HRS and LRS resistance values of the memristor remain stable
as the number of cycles increases, indicating that the device has
excellent endurance characteristics The HRS/LRS resistance
ra-tio of the device can achieve ≈16, which also remains stable with
the increasing of cycle number Further, the retention character-istics of the device were investigated, as shown in Figure2c, and the results show that the retention performance is satisfactory within 104s
Subsequently, the semi-logarithmic I–V curves of the Ti/CeOx/WOy/ITO memristor is plotted in Figure 2d The memristive performance of the device can be seen from the I–V curve that the first 60 cycles are stable and the last 20 cycles show
a jumping phenomenon The HRS and LRS resistance value of the device were measured at −0.1 V to investigate the durability
of the device in Figure2e, in which the HRS and LRS resistance values of the device showed a simultaneous increase in the vicinity of 60 cycles and the stability decreased The HRS/LRS resistance ratio of the device is ∼1, and its value also shows small
Trang 4Figure 2 a) Semi-logarithmic I–V characteristic curves of the device when Ag was used as the top electrode b) Corresponding resistance value of
the device at the HRS and LRS and the HRS/LRS resistance ratio c) Retention characteristics of the corresponding device d) Semi-logarithmic I–V characteristic curves of the device when Ti was used as the top electrode e) Corresponding resistance value of the device at the HRS and LRS and the HRS/LRS resistance ratio f) Retention characteristics of the corresponding device g) Semi-logarithmic I–V characteristic curves of the device when TiN was used as the top electrode h) Corresponding resistance values of the device at the HRS and LRS and the HRS/LRS resistance ratio i) Retention characteristics of the corresponding device.
fluctuations in the later part of the cycle, which indicates the
weak durability of the device The retention characteristics of the
device were further explored, as shown in Figure2f, which show
that both the resistance values of the HRS and LRS increase with
time within 103s
Finally, the semi-logarithmic I–V curve of the
TiN/CeOx/WOy/ITO memristor is shown in Figure 2g It is
evident that the I–V curves changed during the cycling process
In order to assess the durability of the device, we conducted tests
to measure the HRS and LRS resistance values at an applied
voltage of −0.1 V, and the results are shown in Figure2h The
HRS resistance value of the device has a high dispersion in the
first 50 cycles, and the LRS resistance value shows an abrupt
decrease of resistance in the 10th cycle The HRS/LRS resistance
ratio of the device is ≈2, and the resistance value shows small
fluctuations, indicating that the device is relatively unstable The retention characteristics of the device were further explored, as shown in Figure2i, and the results show that the device has
a small fluctuation within 103 s Based on the experimental results presented above, the performance of memristor devices using Ag as the top electrode shows significant improvement compared to devices using Ti and TiN as the top electrode The memristor based on Ag electrode not only exhibits a high resistance ratio, but it also exhibits excellent durability and retention performance
In order to test the RS performance of the as-prepared Ag/CeOx/WOy/ITO device in depth, the I–V curve with 100 cy-cles was obtained at the operating voltage sequence of 0 → +2 V→ 0 → -2 V → 0, as shown in Figure 3a By testing the Ag/CeOx/WOy/ITO memristor, it can be observed that the
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Figure 3 a) I–V curves of the Ag/CeOx/WOy/ITO device under applied voltage of ±2 V b) Corresponding semi-logarithmic I–V curves c) I–V curves of the device under different bias voltage scan rates d) Comparison of HRS and LRS of the device under different bias voltage scan rates and the HRS/LRS resistance ratio e) I–V curves of the device under different voltage amplitude f) Comparison of the HRS and LRS of the device under different voltage amplitude and the HRS/LRS resistance ratio.
vice has a typical bipolar RS behavior, and a typical I–V curve
was taken to obtain a semi-logarithmic curve in Figure3b, which
clearly shows the SET and RESET process When a positive
volt-age scan (0→ +2.0 V) is applied to the device, the SET behavior
will occur ≈+1.0 V, and the device can be switched from HRS to
LRS When the scan voltage direction was changed (+2.0 V→ 0),
the device remained LRS until it entered the negative voltage
re-gion When a negative voltage sweep (0→ −2.0 V) was applied,
the RESET behavior occurs ≈−1.6 V, which lend that the device
can be switched from LRS to HRS, and then the sweep voltage
direction changes (−2.0 V→ 0), but the device can still remain at
HRS until it enters the positive voltage region again
To further explore the RS performance of the
Ag/CeOx/WOy/ITO memristor, we investigated the effect of
different bias voltage scan rates on the performance of the
memristor The I–V curves are shown in Figure 3cwhen the
bias voltage scan rate is 0.2 0.4, 0.6, 0.8, 1.0, and 1.2 V s−1under
an applied voltage of ±2 V In the process of increasing the
bias voltage scan rate from 0.2 V s−1to 1.2 V s−1, the resistance
value of LRS is almost unchanged, while the resistance value
of HRS first decreased and then increased, and the HRS/LRS
resistance ratio reached the maximum value of ≈16 when the
bias voltage scan rate was 0.2 V s−1, as shown in Figure 3d
The RS characteristics can be attributed to the effect of electron
trapping/de-trapping duo on the interface defects At a low bias
voltage scan rate, the injected electrons have enough time to
complete the trapping/de-trapping process.[ 35,36 ] However, at a
high bias voltage scan rate, the injected electrons may be not
have enough time to complete the trapping/de-trapping process,
which causes the resistance value of the HRS to first decrease and then tend to increase It indicates that the bias voltage scan rate has a threshold value for the motion of the injected elec-trons, which affects the motion of the electrons when the bias voltage scan rate is greater than the threshold value Therefore, the HRS/LRS resistance ratio of the device also varies with the bias voltage scan rate
Naturally, the different voltage amplitude was applied to the memristor, which were ±0.5, ±1.0, ±1.5, ±2.0, ±2.5, and ±3.0 V,
as shown in Figure3e The I–V curves under different voltage am-plitude show that the SET and RESET voltages of the device grad-ually increase with the increases of applied voltage amplitude, indicating that the threshold voltage of the memristor depends
on the applied voltage amplitude As shown in Figure 3f, the HRS/LRS resistance ratio of the Ag/CeOx/WOy/ITO memristor also varies under different voltage amplitude, and the HRS/LRS resistance ratio of the device increases continuously with the in-crease of applied voltage amplitude When a voltage amplitude
of ±3 V was applied to the device, the HRS/LRS resistance ra-tio reached a maximum value of 20 Furthermore, the resistance value of the HRS increased with the increase of voltage ampli-tude, while the resistance of the LRS decreased and then sta-bilized This indicates that the voltage amplitude affects both the resistance values of HRS and LRS In conclusion, the RS performance of the device was found to be influenced by vari-ations in voltage amplitude and voltage scan rates This sug-gests that both the bias voltage scan rate and the applied volt-age amplitude can have an impact on the RS performance of the device
Trang 6Figure 4 a) The semi-logarithmic I–V curve of the device b,c) The I–V curve on log(I)–log(V) scale in the positive voltage region d) The I–V curves on a
log(I)–log(V) scale in the negative voltage region e) The Schottky emission is fitted to the I–V curve in the negative voltage region f) Schematic energy band diagram of Schottky emission.
Eventually, to determine whether the device can maintain its
ability to operate effectively under various temperature
condi-tions, the RS performance was evaluated at different
tempera-tures As shown in FigureS3a(Supporting Information), the I–
V curves of the device were tested at a voltage amplitude of 2 V
with the temperature range from 300 to 380 K The results show
that the RS performance remains stable at 300, 320, and 340 K
When the temperature reaches 360 K, the RS performance of the
device begins to degrade In particular, the RESET characteristic
of the device disappears at 380 K As shown in FigureS3b
(Sup-porting Information), the resistance values of HRS and LRS of
the device increase to varying extents as the temperature
contin-ues to increase The HRS/LRS resistance ratio exhibits a pattern
of initially increasing and then decreasing, and the HRS/LRS
re-sistance ratio reaches a peak of 34 at 340 K This phenomenon
can be attributed to the influence of electron trapping and
de-trapping on interfacial defects As the temperature increases, the
injected electrons are accelerated to complete the
trapping/de-trapping process When the temperature exceeds the threshold
of 360 K, it damages the internal structure of the device, leading
to a decline in RS performance
To further analyze the charge transport mechanism of the
Ag/CeOx/WOy/ITO memristor, a typical semi-logarithmic I–V
curve is selected, as shown in Figure 4a, in which the one-cycle
I–V curve was divided into four parts and used different
conduc-tion models to fit the I–V curves under different voltage ranges
At first, a double logarithmic linear fitting of the I–V curve in the
positive region of 0 V→ +2 V, as shown in Figure4b The slopes
of the linear fitting in the 0 V→ +2 V region are ≈1.04,≈1.63,
≈11.9, and ≈1.3, respectively, indicating that the SCLC mecha-nism dominates the fitting results in this region In addition, a double logarithmic linear fitting of the I–V curve in the positive region of +2 V→ 0 V, as shown in Figure4c The slopes of the linear fitting in the +2 V→ 0 V region is ≈1.03, which shows the Ohmic conduction mechanism is consistent with that in this range The above results show that the charge transfer character-istics of the device in the positive voltage region are dominated by the SCLC mechanism The SCLC mechanism is induced by elec-tron injection from ohmic contacts, which is associated with the trapping and separation of carriers in the functional layer.[ 37,38 ]
The SCLC mechanism can be described as follows:[ 39,40 ]
J SCLC= 9
8𝜀 i 𝜇𝜃 V2
where ℇi is the permittivity, μ is the carrier mobility, 𝜃 is the free and shallow trapped charges ratio, and d is the thickness of the
dielectric layer
After that, the I–V curve was fitted with a double logarithm in the negative voltage region, as shown in Figure4d, and the slopes are 1.06 and 0.96 in the voltage regions of 0 V→ -1 V and -2 V
→ 0 V, respectively, which is conformed to Ohmic conductance
As shown in Figure4e, in the high voltage region of -1 V→ -2 V, there is a RESET process of the resistance state from LRS to HRS, which is fitted with the Schottky emission model and the result shows a slope of 3.04 in this region The fitting results indicate that the conduction behavior is consistent with Schottky
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Figure 5 a) Band schematic diagram of the Ag/CeOx/WOy/ITO structure b) Energy band diagram of the CeOx/WOyheterojunction c) Conductive filament model of the device.
sion, suggesting that some electrons are trapped by oxygen
va-cancies during conduction This can be described as follows:[ 41,42 ]
J = A∗T2exp
⎡
⎢
⎢
⎢
−q
(
B−√
qV∕4𝜋𝜀 r 𝜀0d
)
KT
⎤
⎥
⎥
A∗= 4𝜋qk2m∗
where J is the current density, A* is the effective Richardson
con-stant, m 0 is the free electron mass, m* is the effective electron
mass in the dielectric layer, T is the absolute temperature, q is the
electronic charge, ΦB is the Schottky barrier height, k is the
Boltz-mann’s constant, h is the Planck’s constant, ℇ 0is the permittivity
in a vacuum, and ℇr is the optical dielectric constant, V is applied
voltage, and d is the Schottky conduction distance After
exclud-ing the constant parameter in Equation (2), the equation can be
regarded as ln(J) is linear to V ½, so the Schottky barrier plays
an important role in the metal-semiconductor contact Figure4f
shows a band schematic diagram of Schottky emission In
sum-mary, the fitting analysis results of the I–V curve show that the
charge transport mechanism of the device can be explained by
the SCLC mechanism and Schottky emission
The energy band structure of the Ag/CeOx/WOy/ITO
memris-tor is depicted in Figure 5a, illustrating that the work functions of
ITO and Ag electrodes are 4.8 and 4.26 eV, respectively The
en-ergy bands of CeO2and WO3are 3.2 and 2.7 eV, respectively.[ 43–46 ]
As a result of the UPS data in Figure1i, the work functions of CeOx and WOy are 3.33 and 4.295 eV, respectively When two functional materials contact between CeO2and WO3, electrons flow from CeO2with a higher Fermi energy level to WO3with a lower energy level, which bends the energy band at the interface between the two materials until the Fermi energy level can reach equilibrium Finally, an electron depletion layer is formed on the contact surface of CeO2, and an electron accumulation layer is formed on the contact surface of WO3 The interface is modulated
by an applied electric field, which in turn affects the conductiv-ity of this heterojunction, so that the devices can realize mutual transitions between HRS and LRS
The n–n heterojunction is formed on the contact surface, as
shown in Figure5b, which leads to the change of the conductiv-ity In the initial state, due to the formation of a heterojunction barrier to electronic transport having obvious blocking effect, this memristor exhibits HRS When the positive voltage applied to the device is gradually increased to the threshold voltage, oxygen va-cancies are accumulated at the heterojunction interface, causing the heterojunction conductivity to increase dramatically, so that the resistance state of the memristor is switched from HRS to LRS When a negative voltage is applied to the device, the oxy-gen vacancies gradually migrate back to the initial state under the action of the electric field, causing the heterojunction also to gradually return to the initial state, and the resistance state of the device is switched from LRS to HRS again Therefore, by modu-lating the band structure of the heterojunction, the HRS and LRS
Trang 8of the memristor can be switched, which makes the device shows
an excellent RS effect
To further elaborate on the above explanation, a co-modulated
conducting filament model by Ag and oxygen vacancies is
devel-oped to explain the RS performance of the Ag/CeOx/WOy/ITO
memristor, as depicted in Figure5c A representative I–V curve
is chosen, which can be divided into four parts When no
volt-age is initially applied to the device, the resistance state is HRS
When a positive voltage is applied to the top electrode of the
de-vice, the Ag atoms are first ionized to produce Ag+ions Due to
the low mobility of Ag+ ions in metal oxides, the electron gain
reaction occurs near the anode, producing Ag atoms that
aggre-gate at the anode to form Ag conductive filament, so that the Ag
conductive filament grows from the anode to the cathode The
reaction process is as follows:[ 47,48 ]
Ag→ Ag+
+e−
(4)
Ag+
At the same time, under the action of an electric field,
reduc-tion reacreduc-tions occur in the oxygen atoms within the funcreduc-tional
layer, leading to the generation of a large number of oxygen
vacancies The oxygen vacancies generated will carry a positive
charge due to the loss of electrons and will dynamically migrate
to the cathode The cathode will continue to accumulate a large
number of oxygen vacancies and form oxygen vacancy conductive
filaments As a result, the oxygen vacancy conductive filaments
grow from the cathode to the anode The process of oxygen
va-cancy generation is as follows:[ 49 ]
O + 2e−→ V2+
From the I–V curve, it can be inferred that the cathodic oxygen
vacancy (Vo2+) conducting filament and the anodic Ag
conduct-ing filament may be connected at the interface, formconduct-ing a
con-ducting channel between the top and bottom electrodes, making
the resistance state can be switched from HRS to LRS When the
direction of the applied electric field is reversed, the oxygen
va-cancy will combine with O2−ions, causing the conductive
fila-ment formed by the oxygen vacancies to break The reaction is as
follows:
O2−+V2+
At the same time, the Ag conductive filament in the top
elec-trode region loses electrons to form Ag+ions These reactions
lead to the rupture and dissolution of the oxygen vacancy and
Ag conductive filament inside the CeOx/WOyfunctional layer,
re-sulting in the resistance state of the device can be switched from
LRS to HRS Therefore, we use the model of oxygen vacancy and
Ag conducting filament to describe how the resistance state of
the device can be switched between HRS and LRS This model
provides a reasonable explanation for the RS behavior of the
de-vice
The memristor with an Ag/CeOx/WOy/ITO structure exhibits
excellent digital RS characteristics, allowing the resistance states
of the device to transition between HRS and LRS under the
ap-plied electric field The variable conductivity of a memristor
al-lows for its combination with other electronic devices in logic computation, information security transmission, and informa-tion encrypinforma-tion/decrypinforma-tion processing First of all, by connect-ing two memristors in forward parallel with terminals A and B
as inputs and terminal Y as output, as shown in Figure 6a, thus
an OR logic gate circuit is designed.[ 50 ] The OR logic gate cir-cuit is constructed and simulated using the Simulink module of MATLAB The memristor parameters are configured to match those obtained from the Ag/CeOx/WOy/ITO memristor experi-ment, with the LRS set to 30 Ω and the HRS set to 480 Ω During the simulation, the input has a high level of 10 V and a low level
of 0.1 V The output voltage is considered low if it is smaller than
2 V and high if it is higher than 8 V The simulation results of the
OR gate circuit are depicted in FigureS4a(Supporting Informa-tion) The results indicate that the output low level is 0.1 V when both inputs are 0.1 V In all other cases, the output is at a high level The simulation results align with the truth table of the OR logic circuit The histogram generated from the simulation re-sults is depicted in Figure6b, illustrating that the OR logic can
be achieved by connecting two memristors in parallel in the for-ward direction Then, an AND logic gate circuit was constructed using two memristors connected in reverse parallel, as illustrated
in Figure6c The AND logic gate circuit was simulated, and the simulation results are depicted in FigureS4b(Supporting Infor-mation) The output is 10 V when both inputs are 10 V; other-wise, the output is less than 2 V A comparison of the simula-tion results with the truth table of the AND gate reveals that they exhibit the same logical relationship The histogram generated from the simulation results is depicted in Figure6d, indicating that the circuit constructed by reversing the parallel connection
of two memristors is capable of implementing an AND logic gate
In addition, XOR and XNOR logic gate circuits can be designed
by integrating the memristor with CMOS inverters.[ 51 ] As de-picted in Figure6e, the XOR logic gate circuit was created using
a combination of four memristors and two CMOS inverters I 1 and I 2 are CMOS inverters The input of I 1 and I 2 is the output
of an AND logic circuit The top terminal of I1is connected to
the output of an OR logic circuit, and the bottom terminal of I 2
is connected to a low level The output is an XOR logic The XOR logic gate circuit can be simulated, and the simulated output can
be seen in FigureS4c(Supporting Information) The output is 9.41 V when the two input voltages are different, but it is below
2 V in other cases The comparison of the simulation results with the XOR truth table demonstrates that the logical relationship
is consistent The histogram image from the simulation results
is depicted in Figure6f, indicating that the circuit, constructed using a combination of memristor and CMOS inverter, is capa-ble of implementing the XOR logic gate Finally, the XNOR logic gate circuit was designed using a combination of four memris-tors and two CMOS inverters, as shown in Figure6g When V cc
is set to 10 V, the inputs of I 1 and I 2are connected to the outputs
of the OR logic circuit The top terminal of I 1 is linked to V cc,
and the bottom terminal of I2is connected to the output of the AND logic circuit As a result, the circuit produces the output of
an XNOR logic gate The XNOR logic gate circuit was simulated, and the results are depicted in FigureS4d(Supporting Informa-tion) The simulation indicates that the output is 10 V when the two input voltages are the same, and in all other cases, the out-put is below 2 V A comparison of the simulation results with
Trang 9www.advancedsciencenews.com www.afm-journal.de
Figure 6 Logic gate circuits based on memristor a) Schematic diagram of OR gate circuit b) Histogram of the simulation results of the OR gate circuits.
c) Schematic diagram of AND gate circuit d) Histogram of the simulation results of the AND gate circuit e) Schematic diagram of XOR gate circuit f) Histogram of the simulation results of the XOR gate circuit g) Schematic diagram of XNOR gate circuit h) Histogram of the simulation results of the XNOR gate circuit i) Schematic diagram of half adder circuit j) Histogram of the simulation results of the half-adder circuit k) Schematic diagram of full adder circuit l) Histogram of the simulation results of the full adder circuit.
the XNOR truth table confirms the consistency of the logic
re-lationship The histogram image from the simulation results is
presented in Figure6h, demonstrating that the circuit, created by
combining memristors and CMOS inverters, is capable of
imple-menting the XNOR logic gate
In addition to the construction of logic operation circuits,
memristors can also be used in digital circuits for the
construc-tion of arithmetic operaconstruc-tion circuits On the basis of the
im-plementation of the four basic logic gates OR, AND, XOR, and
XNOR, the adder can be further built.[ 52 ] When two one-bit
bi-nary numbers are added together without taking into account
the input of the lower bit, it is believed to be a half-add
opera-tion A circuit that implements the half-add operation becomes
a half-add circuit A half-add circuit is formed by parallel AND
and XOR logic circuits, as shown in Figure6i, in which S is the
summation of the sums and C is the supply to the higher bit.
The circuit was built and simulated in MATLAB, as shown in the
table of FigureS5a(Supporting Information) Comparing the
re-sults with the half-adder truth table, it shows that the device can
perform half-adder operations The histogram obtained from the
simulation results is shown in Figure6j, which indicates that the
circuit built by paralleling two AND and XOR memristor-based
logic circuits can perform semi-additive logic operations
Binary summation involves adding two corresponding
ad-dends and the three input digits in the lower order This operation
is known as full addition, and the circuit is referred to as a full adder Figure6kdepicts the schematic of the full adder circuit The device comprises two half-adders and an OR logic circuit
Here, CI represents the input from the lower bit, S represents the sum of the sums, and CO represents the input to the higher bit.
The full adder circuit was simulated, and the simulation results are presented in the table in FigureS5b(Supporting Informa-tion) A comparison of the results with the full adder truth table demonstrates that the device is capable of performing full adder operations The histogram image of the simulation results is dis-played in Figure6l, indicating that the circuit, constructed with two half adders and two OR logic circuits, is capable of perform-ing full additive logic operations The accuracy of the simulated digital circuits was confirmed by comparing the logic results of the simulation with the truth table of the corresponding circuits The results of the comparison show that the constructed circuits are fully capable of implementing digital logic operations and dig-ital arithmetic operations In addition, the memristor-based logic circuit can significantly reduce the number of components and power consumption compared to traditional digital logic circuits
It also offers improved circuit versatility and cascading character-istics
In digital electronic devices, a large number of binary digits, consisting of “0” and “1” are used to transmit information At the same time, in data transmission or digital communication, errors
Trang 10Figure 7 a) Schematic diagram of odd checker circuit b) Schematic diagram of even checker circuit c) Histogram of the simulation results of the odd
checker circuits d) Histogram of the simulation results of the even checker circuits.
may occur in the transmission of binary information due to the
presence of noise and interference An odd/even checker can
ver-ify whether errors occur in the transmission of information.[ 53 ]
The parity of “1” in a set of binary codes is determined by using
odd numbers, known as an odd checker, and similarly using even
numbers, known as an even checker In this study, an odd/even
checker was constructed using memristors to verify the parity of
the data Additionally, four-bit odd and even checkers were
cre-ated using the constructed logic gate circuit First, a four-bit odd
check device was constructed using three XOR logic gates The
circuit diagram of the device is illustrated in Figure 7a, with A,
B, C, and D representing the input terminals and Y representing
the output terminal If the four input ports contain an odd
num-ber of 10 V inputs, the Y output will be at a high level; otherwise,
it will be at a low level A simulation of the odd-checker circuit
was conducted, and the simulation results are depicted in Figure
S6b(Supporting Information) A comparison of the simulated
re-sults with the truth table for odd-check in FigureS6a(Supporting
Information) shows that the two logic results are identical As
de-picted in Figure7c, the simulation results are presented in a
his-togram The histogram illustrates that the odd number checker,
constructed using memristors, can successfully perform the odd
number check on the four input digits
Then, three XNOR logic gates were used to construct a
four-digit even number checker that verifies whether the number of
“1” in the input code is even Figure7billustrates the circuit
prciple of the even number checker If the number of “1” in the
in-put code is even, the Y terminal inin-put will be high when the
num-ber of “1” for A, B, C, and D is even, and the output will be low
in other cases The four-bit even checker circuit was simulated, and the results of the simulation are depicted in FigureS6b (Sup-porting Information) A comparison of the simulated results with the truth table in FigureS6a(Supporting Information) reveals that their logical outcomes are identical The simulation results were presented in a histogram in Figure7d, demonstrating that the memristor-based even checker is capable of verifying four-bit even numbers Therefore, this memristor-based parity check cir-cuit is useful for design purposes, and it can effectively ensure the accuracy of data during information transmission
Nowadays, it is very important to ensure the security of infor-mation during the process of transmission Therefore, there is
a high demand for information encryption in various security fields, including high-end technology, confidential correspon-dence, military, and national defense Software-based data en-cryption methods are vulnerable to external attacks that can lead
to data leakage Therefore, the development of data encryption methods using physical hardware is essential for ensuring the security of information transmission.[ 54 ]
In this study, a physical hardware-based encryption matrix sys-tem utilizing full adders is designed First, a full adder circuit based on a memristor is designed and implemented to create a
cryptographic unit As shown in Figure 8a, where V represents the original image input, K and J are the inputs for key 1 and key
2, respectively, and S is the output of the encrypted image Then, using the constructed encryption unit as a basis, an m × n array
of encryption units is designed, in which this array can encrypt