Bài giảng hệ thống máy tính chương 4 ts trần thị minh khoa

Disadvantages of Buses Communication bottleneck  Băng thông bus có thể giới hạn thông lượng I/O tối đa  Tốc độ bus tối đa bị giới hạn bởi:  Chiều dài bus  Số lượng thiết bị trên bus

Chap4: I/O Bus and Device

GV: TS Trần Thị Minh Khoa

 Bus systems: ISA, PCI, PCI-E, ATA, SATA

 COM interface

 HDD

General PC bus architecture

Advantages of Buses

 Đa năng

 Dễ dàng them 1 thiết bị mới

 Các thiết bị ngoại vi có thể đc di chuyển giữa các hệ thống máy tính sử dụng cùng chuẩn bus

 Chi phí thấp

 Tập hợp đơn dây dẫn được chia sẻ bằng nhiều cách

 Quản lý sự phức tạp bằng cách phân vùng thiết kế

Disadvantages of Buses

 Communication bottleneck

 Băng thông bus có thể giới hạn thông lượng I/O tối đa

 Tốc độ bus tối đa bị giới hạn bởi:

 Chiều dài bus

 Số lượng thiết bị trên bus

 Cần hỗ trợ một loạt thiết bị với:

 Độ trễ khác nhau

 Tốc độ truyền tải dữ liệu khác nhau

The General Organization of a Bus

 Control lines

 Signals requests and acknowledgment

 Cho biết loại thông tin trên data lines

 Data lines: mang thông tin giữa source và destination

 Data and Address

Master versus Slave

 Bus transation bao gồm 2 phần:

 Phát hành lệnh (và địa chỉ) – request

 Truyền dữ liệu – action

 Master: khởi tạo bus transaction

 phát hành câu lệnh (command) và địa chỉ (address)

 Slave: phản hồi tới địa chỉ

 Gởi dữ liệu cho master nếu master yêu cầu dữ liệu

 Nhận dữ liệu từ master nếu master gởi dữ liệu

General Bus types

 Processor-memory bus (design specific)

 Ngắn, tốc độ cao

 Phù hợp với hệ thống bộ nhớ đối đa bang thông memory-processor

 Tối ưu hoá cho chuyển cache block

 Backplane bus (standard or proprietary, eg., ATA)

 Bus trung gian kết nối I/O bus tới processor-memory bus

 I/O bus (industry standard, eg., SCSI, PCI-e, USB,

Hypertransport)

 Dài, tốc độ chậm

 Cung cấp cho nhiều thiết bị I/O

 Kết nối tới processor-memory bus hoặc backplane bus

A Computer System with One Bus: Backplane Bus

A Two-Bus System

A Three-Bus System

???

Bus communications

 Bus protocols

 Asynchronous

 Synchronous

 Memory Read / Writes

 I/O Read Writes

 Peer communicaBon – e.g CPU to CPU

 Are communications verified?

 Is there error checking (parity, CRC, etc.) ?

Synchronous and Asynchronous buses

 Synchronous bus (e.g., processor-memory buses)

 Sử dụng bộ đếm (clock) ở control line và fixed protocol cho các giao tiếp liên quan tới clock

 Pros:

 Đơn giản ( 1 Finite-State Machine)

 Nhanh

 Cons:

 Clock skew (lệch đồng hồ) giới hạn chiều dài bus

 Các thiết bị phải làm việc cùng tốc độ

 Thích hợp cho processor-memory bus

Synchronous and Asynchronous buses

 Asynchronous bus (e.g., I/O buses)

 Sử dụng giao thức “handshacking” để thi hành một giao dịch

 Pros:

 Đa năng, chung giao thức

 Data rate linh động

 Cons:

 Phức tạp hơn, 2 FSMs

 Chậm hơn

Buses so far

 Bus Master: có khả năng điều khiển bus, khởi tạo giao dịch (transaction)

 Bus Slave: được kích hoạt bởi giao dịch

 Bus Communication Protocol: đặc tả tuần tự các sự kiện và thời gian yêu cầu để truyền tải thông tin

 Asynchronous Bus Transfers: control lines (req, ack) phục vụ theo tuần tự

 Synchronous Bus Transfers: trình tự liên quan đến clock

Bus transaction

 Arbitration

 Request

 Action

Arbitration: Obtaining Access to the Bus

 Data & Address lines

 Data, addresses, and complex commands

 Control lines

 Signal requests and acknowledgments

 Cho biết loại thông tin trên data lines

 Bus transaction consists of

 Master phát hành câu lệnh (command) và địa chỉ (address) – request

 Slave nhận (hoặc gởi) dữ liệu – action

 Định nghĩa loại giao dịch tới bộ nhớ

 Input: nhập dữ liệu từ thiết bị I/O vào bộ nhớ

 Output: xuất dữ liệu từ bộ nhớ ra thiết bị I/O

Bus Arbitration

 Bus master (initator, usually the CPU)

 Slave ( usually the Memory)

 Arbitration signals

 BusRequest

 BusGrant

 BusPriority

 Higher priority served first

 Fairness, no request is locked out

Multiple Potential Bus Masters:

the Need for Arbitration

 ■ Bus arbitration scheme:

– A bus master wanting to use the bus, asserts the bus request– A bus master cannot use the bus until its request is granted– A bus master must signal to the arbiter after finish using the bus

■ Bus arbitration schemes usually try to balance two

factors:

– Bus priority: the highest priority device should be serviced first

– Fairness: Even the lowest priority device should never

be completely locked out from the bus

Bus Arbitration Schemes



■ Daisy chain arbitration

– Grant line runs through all device, highest priority device first – Single device with all request lines.

■ Centralized

– Many request/grant lines

– Complex controller, may be a bottleneck

■ Self Selection

– Many request lines

– The one with highest priority self decides to take bus

■ Collision Detection (Ethernet)

– One request line

– Try to access bus,

– If collision device backoff

– Try again in random + exp

The Daisy Chain Bus Arbitrations Scheme

■ Pros: simple

■ Cons:

– Cannot assure fairness:

A low-priority device may be locked out indefinitely

– The use of the daisy chain grant signal also limits the bus speed

Centralized Parallel Arbitration

 Used in essentially all processor-memory busses and in highspeed I/O busses

Simplest bus pararadigm

 ■ All agents operate syncronously

■ All can source / sink data at same rate

■ => simple protocol

– just manage the source and target

Simple synchronous protocol

– memory (slave) may take time to respond

– it need to control data rate

Typical Synchronous Protocol

 ■ Slave indicates when it is prepared for data xfer

■ Actual transfer goes at bus rate

Increasing the Bus bandwidth

 ■ Separate versus multiplexed address and data lines:

– Address and data can be transmitted in one bus cycle if separate address and data lines are available

– Cost: (a) more bus lines, (b) increased complexity

 ■ Data bus width:

– By increasing the width of the data bus, transfers of multiple words require fewer bus cycles

– Example: SPARCstation 20’s memory bus is 128 bit wide

– Cost: more bus lines

 ■ Block transfers:

– Allow the bus to transfer multiple words in back-to-back bus cycles

– Only one address needs to be sent at the beginning

– The bus is not released until the last word is transferred

– Cost: (a) increased complexity

(b) increased response time (latency) for request

Pipelined Bus Protocols

 Attemp to initiate next address phase during current data phase

Increasing Transaction Rate on Multimaster Bus

 ■ Overlapped arbitration

– perform arbitration for next transaction during current

transaction

■ Bus parking

– master can holds onto bus and performs multiple

transactions as long as no other master makes request

■ Overlapped address / data phases (prev slide)

– requires one of the above techniques

■ Split-phase transaction bus ( Command queueing)

– completely separate address and data phases

– arbitrate separately for each

– address phase yield a tag which is matched with data phase

■ ”All of the above” in most modern mem busses

Split transaction protocol

 When we don’t need the bus, release it!

■ Improves throughput

■ Increases latency and complexity

The I/O bus problem

 ■ Designed to support wide variety of devices

– full set not know at design time

■ Allow data rate match between arbitrary speed deviced – fast processor – slow I/O

– slow processor – fast I/O

High Speed I/O Bus

– Raid controllers

– Graphics adapter

■ Limited number of devices

■ Data transfer bursts at full rate

■ DMA transfers important

– small controller spools stream of bytes to or from memory

■ Either side may need to stall transfer

– buffers fill up

Backplane bus

Direct Memory Access (DMA)

Direct Memory Access

PCI Read/Write Transactions

 ■ All signals sampled on rising edge

■ Centralized Parallel Arbitration

– overlapped with previous transaction

■ All transfers are (unlimited) bursts

■ Address phase starts by asserting FRAME#

■ Next cycle “initiator” asserts cmd and address

– IRDY# asserted by master/initiator when ready to transfer data

– TRDY# asserted by target when ready to transfer data

– transfer when both asserted on rising edge

only one more data transfer

■ Arbitrary Burst length

– intiator and target can exert flow control with xRDY

– target can disconnect request with STOP (abort or retry)

– master can disconnect by deasserting FRAME

– arbiter can disconnect by deasserting GNT

■ Delayed (pended, split-phase) transactions

– free the bus after request to slow device

Additional PCI Issues

 ■ Interrupts: support for controlling I/O devices

■ Cache coherency:

– support for I/O and multiprocessors

■ Locks:

– support timesharing, I/O, and MPs

■ Configuration Address Space

Bus design considerations