Ultra Wideband Communications Novel Trends System, Architecture and Implementation Part 11 potx

Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation 240 4.. Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation... Ult

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A Method for Improving Out-Of-Band Characteristics

Ca1 0.27pF ZS1 46.3 ohm ZSo 45.7 ohm θ 2 10 deg

Table 2 Parameters of the lowpass filters shown in Fig.7

Fig 8 Simulated results of the filter shown in Fig.7

Fig 9 Simulated results of the filter shown in Fig.7, when the coupling condition of the stripline is varied

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Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation

240

4 LTCC structure

Fig.10, Fig.11 and Fig.12 indicate the LTCC structure of the filter The filter is obtained by means of modifying the structure based on the basic circuit shown in Fig.7, taking into consideration the various parasitic effects caused by the three-dimensional LTCC structure The filter consists of the three conductor layers inserted into the middle portion of the LTCC substrate, with the ground planes on the top and bottom layers The conductor thickness is 8

um The diameter of via holes is 0.1 mm The ground planes are connected by the via holes The via hole between the coupled line adjusts the coupling condition The dimensions of the bandpass filter are 6.2 x 2.7 x 0.366 mm3, and this size could be fabricated into the LTCC substrate for wireless modules Fig.13 shows the simulated results using a commercial electromagnetic simulator (HFSS Ansys Inc.) The filter has the wide passband and suppresses second and third harmonics The filter also has an additional attenuation pole at the low-frequency region

Fig 10 Three-dimensional structure of the filter

Fig 11 Cross sectional structure of the filter

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Fig 12 Top view of the filter

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substrate are 8.0 x 5.0 x 0.63 mm3 The presented filter (6.2 x 2.7 x 0.366 mm3) is fabricated in the substrate In order to connect the SMA connectors for the evaluation, the top layer of the LTCC substrate has the electrodes for RF signals and a ground plane The feed lines between the filter and the input/output ports consist of a via hole, a stripline, and the electrode of the top layer These feed lines are designed 50 ohm Fig 15 shows a photograph of the LTCC substrate The prototype which is connected to the SMA connectors is measured by a vector network analyzer (N5230A PNA-L, Agilent Technologies Inc) Fig.16 and Fig.17 indicate the measured results It is confirmed that the filter suppresses the spurious responses less than

20 dB up to 16 GHz and has an additional attenuation pole in the low-frequency region In addition, the insertion loss is less than 3.0dB and the group delay is within 1 ns in the wide passband

Fig 15 Photograph of the prototype

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Fig 16 Measured results of the filter shown in Fig.15

Fig 17 Measured group delay of the filter shown in Fig.15

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6 Conclusion

In this study, we propose a method for improving out-of-band characteristics for the wideband filter in the LTCC substrate This method uses the lowpass filters with the coupling structure, which are set at input and output ports of the bandpass filter This method is very useful for the compact wireless modules because additional compact circuits can suppress spurious responses and can add an attenuation pole in the low-frequency band The fabricated UWB bandpass filter for the low-frequency band achieves the insertion loss less than 3.0 dB and the group delay within 1 ns in the wide passband The filter also suppresses spurious responses up to 16 GHz and has the good attenuation performances in the low-frequency region

7 References

Lin, Y.-S., Liu, C.-C., Li,K.-M., & Chen, C.H (2004) Design of an LTCC tri-band transceiver

module for GPRS mobile applications IEEE Transactions on Microwave Theory and

Techniques, Vol 52, No 12, pp 2718-2724

Wang, G., Van, M., Barlow, F & Elshabini, A (2005) An interdigital bandpass filter

embedded in LTCC for 5- GHz wireless LAN applications IEEE Microwave and

Wireless Components Letters,Vol 15, No 5, pp 357-359

Ishida, H & Araki, K (2004) Design and analysis of UWB bandpass filter with ring filter

IEEE MTT-S International Microwave Symposium, pp 1307-1310

Saitou, A., Aoki, H , Satomi, N., Honjo, K., Sato, K., Koyama, T & Watanabe, K.(2005)

Ultra-wideband differential mode bandpass filters embeded in self-complementary

antennas IEEE MTT-S International Microwave Symposium, pp 717-720

Li, K., Kurita, D & Matsui, T (2005).An ultra-wideband bandpass filter using

broadside-coupled microstrip-coplanar waveguide structure IEEE MTT-S International

Microwave Symposium., pp 675-678

Zhu, L., Sun, S & Menzel, W.(2005) Ultra-wideband (UWB) bandpass filters using

multiple-mode resonator IEEE Microwave and Wireless Components Letters, Vol 15, No 11,

pp 796-798

Horii, Y , Tanaka, A., Hayashi, T., & Iida, Y.(2006) A compact multi-layered wideband

bandpass filter exhibiting left-handed and right-handed behaviors IEICE

Transactions on Electronics, Vol E89-C, No 9, pp 1348-1350

Yamamoto, Y., Li, K & Hashimoto, O.(2007) Ultra-wideband (UWB) bandpass filter using

shunt stub with lumped capacitor IEICE Electronics Express, Vol 4, No.7, pp

227-231

Shaman, H & Hong, J.-S.(2007) Input and output cross-coupled wideband bandpass filter

IEEE Transactions on Microwave Theory and Techniques, Vol 55, No 12, pp 2562-2568 Tanii, K., Shimizu, Y., Nishimura, F., Sasabe, K., Ueno, Y., Wada, K & Iwasaki,T.(2008) A

study of various wide-band BPFs with attenuation poles using distributed

tap-coupling microstrip-line resonators IEICE Transactions on Electronics (Japanese

Edition), Vol.J91-C , No.6 , pp.332-340

Sun, S & Zhu, L.(2009) ``Multimode-resonator-based bandpass filters IEEE Microwave

magazine, Vol 10, No 2, pp 88-98

Oshima, S., Wada, K., Murata, R., & Shimakata, Y (2008) A study of a compact multilayer

wideband bandpass filter in LTCC substrate using distributed resonator with

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attenuation poles consisted of a capacitor and λ/2 open-ended stub,” IEICE

Transactions on Electronics (Japanese Edition), Vol.J91-C, No.8, pp.409-417

Oshima, S., Wada, K., Murata, R., & Shimakata, Y.(2010) Multilayer dual-band bandpass

filter in low temperature co-fired ceramic substrate for ultra-wideband

applications IEEE Transactions on Microwave Theory and Techniques, Vol.58, No.3,

pp.614-623

Ghorashi, S.A., Allen,B., Ghavami, M., & Aghvami, A.H (2004) An overview of MB-UWB

OFDM, IEE Seminar on Ultra Wideband Communications Technologies and System

Design, 2004 , pp.107- 110

Kurita,D.& Li, K (2007) Super UWB lowpass filter using open-circuited radial stubs IEICE

Electronics Express, Vol.4, No.7, pp.211-215

Ohwada, T., Ikematu, H., Oh-hashi, H., Takagi, T & Ishida, O.,(2002) A Ku-band low-loss

stripline low-pass filter for LTCC modules with low-impedance lines to obtain

plural transmission zeros IEEE MTT-S International Microwave Symposium, pp

1617-1620

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13

Calibration Techniques for the Elimination of

Non-Monotonic Errors and the Linearity

Improvement of A/D Converters

Nikos Petrellis1 and Michael Birbas2

While the ADCs may operate in an optimal way when they are initially designed and verified using DC simulation, a transient simulation can designate several problems that appear during the high speed operation Additional linearity errors are posed by process variations and component mismatches after the chip fabrication Finally, operating conditions like voltage supply levels and temperature variations can also affect the linearity

of an ADC Several foreground and background calibration techniques have been proposed

in the literature Most of them are developed for specific ADCs and cannot be applied to different ADC architectures

The most important error sources and the most popular calibration methods for Pipelined, Segmentation/Reassembly and Sigma Delta ADCs as well as a number of generic error compensation methods based on the processing of the ADC output are presented in (Balestrieri et al, 2005) A popular error correction technique used in pipelined ADCs exploits the least significant bit of a “coarse” ADC stage for the error detection and correction For example, in (Colleran & Abidi, 1993) a 10-bit ADC is constructed by a 4-bit

“coarse” and a 7-bit “fine” ADC The least significant bit of the coarse ADC should match the most significant bit of the fine ADC Similarly, a 10-bit pipeline ADC consists of a coarse 6-bit and a fine 5-bit ADC in (Sone et al, 1993) Two more recent approaches that are described in (Kurose et al, 2006) and in (Ahmed & Johns, 2005)(Ahmed & Johns, 2008) use 8 stages of 1.5-bit and a 2-bit Flash ADC stage in a 10-bit (or 11-bit in (Ahmed & Johns, 2008)) pipelined ADC architecture Moreover, in (Ahmed & Johns, 2008), the DAC linearity errors are also taken into consideration The use of a redundant signed digit also appears at an Analogue-to-Quaternary pipelined converter in (Chan et al, 2006)

The ADC architectures that are based on high precision capacitors suffer from the effects of the mismatch In (Wit et al, 1993), an additional array of capacitors is used for real time

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trimming that is performed by an algorithm implemented on-chip in order to handle component ageing Trimming arrays are also used in (Ohara et al, 1987) A digital calibration of the capacitor mismatch, the comparator offsets and the charge injection offsets in a pipelined ADC is performed in (Karanicolas et al, 1993) for the improvement

& Lee, 2009) to correct gain errors in pipelined ADCs This calibration technique performs the error estimation and the adaptive error correction based on the concept of split ADCs In (Sun et al, 2008), a technique called Commutated Feedback Capacitor Switching is used to extract information about the mismatches of the capacitors used and then this information is exploited by a digital background calibration method

Post processing techniques offer a different approach to the linearity error reduction of the ADCs While all the aforementioned techniques target to the correction of the error sources, the post processing methods operate on the ADC output The Differential or Integral Non-Linearity (DNL/INL) errors can be measured in order to estimate correction factors for each output code These correction factors are stored in large lookup tables and are added

to or subtracted from the corresponding output codes at real time These lookup tables are also subject to real time calibration as described in (De Vito et al, 2007) The estimation of the correction factors can be performed in the simplest case by applying successive DC levels at the ADC input and measuring the DNL of the generated ADC output codes (Provost & Sanchez-Sinencio, 2004) More sophisticated techniques apply a sinusoidal signal to the ADC input and construct a Histogram using the resulting ADC output in order to estimate the DNL errors and consequently the correction factors (Correa-Alegria

& Cruz-Sera, 2009)

In this chapter, some representative calibration approaches presented in the literature are described emphasising on the more general ones in the sense that they can be applied to different ADC architectures Moreover, the calibration schemes proposed by the authors in a current mode implementation of a 12-bit ADC with a novel binary tree structure (Petrellis et

al, 2010a) as well as in a voltage mode subrange ADC (Petrellis et al, 2010b, 2010c) are also presented since they can also be used in different target applications

2 Resistor and capacitor trimming

The highest speed ADCs are based on the Flash or Parallel architecture where the input

signal is concurrently compared to 2 n reference levels generated by a resistor ladder

consisting of identical resistors R The Flash ADCs cannot offer a high resolution (it is

practically lower than 8-bits) since the required area and power is increased in an exponential manner Linearity is essential in these ADCs in order to prevent the already low dynamic resolution from a further reduction

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Calibration Techniques for the Elimination of

Non-Monotonic Errors and the Linearity Improvement of A/D Converters 249

A significant linearity error source in these ADCs is the component mismatches in the

resistor ladders If the tolerance in these resistors is expressed as ±kΔR, then it can be reduced to ±ΔR as shown in Fig 1a where each resistor R has been replaced with a resistor

R-kΔR connected in series with 2k trimming ΔR resistors that can be bypassed by the

calibration algorithm or at a final stage of the fabrication process

Fig 1 Resistor (a) and Capacitor (b) trimming

High precision capacitors are used in several ADC architectures that are based on charge redistribution, integrators, Sigma-Delta ADCs etc (Quiquempoix et al, 2006) Capacitor trimming can be performed in a similar way to the resistors whenever high precision capacitors have to be used (Wit et al, 1993) A simple way to perform such a capacitor

trimming is shown in Fig 1b If the tolerance of a capacitor C is ±kΔC then, by using a fundamental C-kΔC capacitance and 2k trimming capacitors ΔC that can be potentially connected in parallel, the tolerance can be reduced to ±ΔC

3 Redundant bits in pipeline ADCs

Pipeline, Subfolder and Subrange ADCs can achieve a descent resolution higher than 8-bit with a conversion speed that is comparable to that of the Flash ADCs This is achieved by using a number of Flash ADC stages with lower resolution For example in a two stage

Pipeline ADC with m+n bits resolution, the analogue input is connected to a “coarse” m-bit ADC that generates the m most significant bits These bits are used as input to a DAC in

order to reconstruct an analogue signal that is subtracted by the original input and a residue

is generated that serves as input to the second “fine” ADC stage that has an n-bit resolution

If the “coarse” ADC generates m+1 instead of m bits but the least significant bit is not input

to the DAC as shown in Fig 2, then this least significant bit should match the most

significant bit of the n-bit “fine” ADC, otherwise the subtraction or the DAC operation has

not been performed accurately enough (Iizuka et al, 2005)(Van De Vel et al, 2009) In this case, the offset of the subtraction operational amplifier or a resistor/capacitance trimming at the side of the DAC may be necessary

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Fig 3 A 3-bit DAC with offset

Vcc

Ic2Ip

I2V

S0 S1

S2

D

A C

n bit Fine ADC

S/H +

-m+1 bit Coarse ADC

Least significant bitm-MSBs

m-MSBs

n- LSBs

Most significant bit

Correct operation indication

Tiêu đề	Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation
Trường học	Standard University
Chuyên ngành	Electrical Engineering
Thể loại	Luận văn
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