Test and diagnosis of analogue, mixed signal and rf integrated circuits the system on chip approach

1 Fault diagnosis of linear and non-linear analogue circuits 1 Yichuang Sun 1.3.1 Class-fault diagnosis and general algebraic method for 1.4.1 Fault modelling and fault incremental circu

Tai Lieu Chat Luong

Test and Diagnosis of Analogue, Mixed-signal and

RF Integrated Circuits

The system on chip approach

Edited by Yichuang Sun

The Institution of Engineering and Technology

Published by The Institution of Engineering and Technology, London, United Kingdom

© 2008 The Institution of Engineering and Technology

by the Copyright Licensing Agency Inquiries concerning reproduction outside those terms should be sent to the publishers at the undermentioned address:

The Institution of Engineering and Technology

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While the authors and the publishers believe that the information and guidance given in this work are correct, all parties must rely upon their own skill and judgement when making use of them Neither the authors nor the publishers assume any liability to anyone for any loss or damage caused by any error or omission in the work, whether such error or omission is the result of negligence or any other cause Any and all such liability is disclaimed.

The moral rights of the authors to be identified as authors of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988.

British Library Cataloguing in Publication Data

Test and diagnosis of analogue, mixed-signal and RF

integrated circuits : the system on chip approach –

(Circuits, devices & systems ; v 19)

1 Linear integrated circuits – Testing 2 Mixed signal

circuits – Testing 3 Radio frequency integrated circuits – Testing

I Sun, Yichuang II Institution of Engineering and Technology

621.3’815’0287

ISBN 978-0-86341-745-0

Typeset in India by Newgen Imaging Systems (P) Ltd, Chennai

Printed in the UK by Athenaeum Press Ltd, Gateshead, Tyne & Wear

System on chip (SoC) integrated circuits (ICs) for communications, multimedia andcomputer applications are receiving considerable international attention One exam-ple of a SoC is a single-chip transceiver Modern microelectronic design processesadopt a mixed-signal approach since a SoC is a mixed-signal system that includesboth analogue and digital circuits There are several IC technologies currently avail-able, however, the low-cost and readily available CMOS technique is the mainstreamtechnology used in IC production for applications such as computer hard disk drivesystems, sensors and sensing systems for health care, video, image and display sys-tems and cable modems for wired communications, radio frequency (RF) transceiversfor wireless communications and high-speed transceivers for optical communications.Currently, microelectronic circuits and systems are mainly based on submicron anddeep-submicron CMOS technologies, although nano-CMOS technology has alreadybeen used in computer, communication and multimedia chip design While still push-ing the limits of CMOS, preparation for the post-CMOS era is well under way withmany other potential alternatives being actively pursued.

There is an increasing interest in the testing of SoC devices as automatic testingbecomes crucially important to drive down the overall cost of SoC devices due to theimperfect nature of the manufacturing process and its associated tolerances Tradi-tional external test has become more and more irrelevant for SoC devices, becausethese devices have a very limited number of test nodes Design for testability (DfT)and built-in self-test (BIST) approaches have thus been the choice for many applica-tions The concept of on chip test systems including test generation, measurement andprocessing has also been proposed for complex integrated systems Test and fault diag-nosis of analogue and mixed-signal circuits, however, is much more difficult than that

of digital circuits due to tolerances, parasitics and non-linearities, and thus it remains

a bottleneck for automatic SoC test Recently, the closely related tuning, calibrationand correction issues of analogue, mixed-signal and RF circuits have been intensivelystudied However, the papers on testing, diagnosis and tuning have been published

in a diverse range of journals and conferences, and thus they have been treated quiteseparately by the associated communities For example, work on tuning has beenmainly published in journals and conferences concerned with circuit design and hasnot therefore come to the attention of the testing community Similarly, analogue fault

xvi Test and diagnosis of analogue, mixed-signal and RF integrated circuits

diagnosis was mainly investigated by circuit theorists in the past, although it has nowbecome a serious topic in the testing community

The scope of this book is to consider the whole range of automatic testing, sis and tuning of analogue, mixed-signal and RF ICs and systems It aims to provide

diagno-a comprehensive trediagno-atment of testing, didiagno-agnosis diagno-and tuning in diagno-a coherent wdiagno-ay diagno-and

to report systematically the most recent developments in all these areas in a singlesource for the first time The book attempts to provide a balanced view of the threeimportant topics, however, stress has been put on the testing side Motivated by recentSoC test concepts, the diagnosis, testing and tuning issues of analogue, mixed-signaland RF circuits are addressed, in particular, from the SoC perspective, which formsanother unique feature of this book

The book contains 11 chapters written by leading international researchers inthe subject areas It covers three theme topics: diagnosis, testing and tuning Thefirst four chapters are concerned with fault diagnosis of analogue circuits Chapter

1 systematically presents various circuit-theory-based diagnosis methodologies forboth linear and non-linear circuits including some material not previously available

in the public domain This chapter also serves as an overview of fault diagnosis.The following three chapters cover the three most popular diagnosis approaches;the symbolic function, neural network and hierarchical decomposition techniques,respectively Then testing of analogue, mixed-signal and RF ICs is discussed exten-sively in Chapters 5-10 Chapter 5 gives a general review of all aspects of testing withemphasis on DfT and BIST Chapters 6–10 focus in depth on recent advances in test-ing analogue filters, data converters, sigma-delta modulators, phase-locked loops, RFtransceivers and components, respectively Finally, Chapter 11 discusses auto-tuningand calibration of analogue, mixed-signal and RF circuits including continuous-timefilters, voltage-controlled oscillators and phase-locked loops synthesizers, impedancematching networks and antenna tuning units

The book can be used as a text or reference for a broad range of readers fromboth academia and industry It is especially useful for those who wish to gain aviewpoint from which to understand the relationship of diagnosis, testing and tuning

An indispensible reference companion to researchers and engineers in electronic andelectrical engineering, the book is also intended to be a text for graduate and seniorundergraduate students, as may be appropriate

I would like to thank staff members in the Publishing Department of the IETfor their support and assistance, especially the former Commissioning Editors SarahKramer and Nick Canty and the current Commissioning Editor, Lisa Reading I amvery grateful to the chapter authors for their considerable efforts in contributing thesehigh-quality chapters; their professionalism is highly appreciated I must also thank

my wife Xiaohui, son Bo and daughter Lucy for their understanding and support;without them behind me this book would not have been possible

As a final note, it has been my long dream to write or edit something in the topicarea of this book The first research paper published in my academic career was aboutfault diagnosis in analogue circuits This was over 20 years ago when I studied forthe MSc degree The real motivation for doing this book, however, came along with

the proposal for a special issue on analogue and mixed-signal test for SoCs for IEE

Proceedings: Circuits, Devices and Systems (published in 2004) It has since been

a long journey for the book to come into being as you see now, however, the bookhas indeed been significantly improved with the time during the editorial process

I sincerely hope that the efforts from the editor and authors pay off as a truly usefuland long-lasting companion in your successful career

Yichuang Sun

1 Fault diagnosis of linear and non-linear analogue circuits 1

Yichuang Sun

1.3.1 Class-fault diagnosis and general algebraic method for

1.4.1 Fault modelling and fault incremental circuits 21

1.4.3 Alternative fault incremental circuits and fault

1.5 Recent advances in fault diagnosis of analogue circuits 291.5.1 Test node selection and test signal generation 29

1.5.2 Symbolic approach for fault diagnosis of analogue

1.5.3 Neural-network- and wavelet-based methods for

1.5.4 Hierarchical approach for large-scale circuit fault

2 Symbolic function approaches for analogue fault diagnosis 37

Stefano Manetti and Maria Cristina Piccirilli

2.3.4 Testability analysis of non-linear circuits 57

2.4.1 Techniques based on bilinear decomposition of fault

2.5.2 Transient analysis models for reactive components 73

3.2 Fault diagnosis of analogue circuits with tolerances using

List of contents ix

3.2.4 Neural-network approach for fault diagnosis of

3.3 Wavelet-based neural-network technique for fault diagnosis of

3.3.2 Wavelet feature extraction of noisy signals 95

3.4 Neural-network-based L1-norm optimization approach for fault

3.4.1 L1-norm optimization approach for fault location of

5 DFT and BIST techniques for analogue and mixed-signal test 141

Mona Safi-Harb and Gordon Roberts

5.5.3 Digital phase-initerpolation techniques: delay line 156

5.5.5 Component-invariant VDL for jitter

5.5.6 Analogue-based jitter measurement device 160

5.5.8 PLL and DLL – injection methods for PLL tests 163

5.7 Complete on-chip test core: proposed architecture in

5.7.8 Limitations of the proposed architecture in

Yichuang Sun and Masood-ul Hasan

6.2.2 Bypassing using duplicated/switched opamp 186

6.3.2 The Kerwin–Huelsman–Newcomb biquad filter 189

6.4.1 Test transformations of active-RC filters 193

List of contents xi

6.5.1 Testing of high-order filters using bypassing 2026.5.2 Testing of high-order cascade filters using

8.5.2 Polynomial model-based BIST 262

9 Phase-locked loop test methodologies: Current characterization

Martin John Burbidge and Andrew Richardson

9.1 Introduction: Phase-locked loop operation and test

9.1.1 PLL key elements’ operation and test issues 277

10.2.3 Implementation as a complete on-chip test system

10.3 CMOS amplitude detector for on-chip testing of

10.3.1 Gain and 1-dB compression point measurement

10.4 Architecture for on-chip testing of wireless transceivers 333

List of contents xiii

11 Tuning and calibration of analogue, mixed-signal and RF circuits 347

James Moritz and Yichuang Sun

11.2.1 Tuning system requirements for on-chip filters 348

11.3 Self-calibration techniques for PLL frequency synthesizers 36511.3.1 Need for calibration in PLL synthesizers 365

11.3.4 Other PLL synthesizer calibration applications 370

11.4.1 Requirement for on-chip antenna impedance

Fault diagnosis of linear and non-linear

analogue circuits

Yichuang Sun

Fault diagnosis of analogue circuits is becoming ever-increasingly important owing

to the rapidly increasing complexity of integrated circuits (ICs) and systems [1–62].Recent interest in mixed-signal systems on a chip provides further motivation foranalogue fault diagnosis automation Fault diagnosis of analogue circuits started with

an investigation of the solvability of network component values in 1960 [13] and hasbeen an active research area ever since Methods for analogue fault diagnosis can

be broadly divided into simulation before test (SBT) or simulation-after-test (SAT)techniques depending on whether simulation is mainly conducted before test or aftertest The most representative SBT technique is the fault dictionary approach, whileSAT techniques include the parameter identification and fault verification approaches.The types of fault most widely considered from the viewpoints of fault diagnosisand location are soft faults and hard faults The former are caused by deviations incomponent values from their nominal ones, whereas the latter refer to catastrophicchanges such as open circuits and short circuits

The fault dictionary method is concerned with the construction of a fault nary by simulating the effects of a set of typical faults and recording the pattern ofthe observable outputs [11, 12] To construct a fault dictionary, all potential faults arelisted and the stimuli are selected The circuit under test (CUT) is then simulated forthe fault-free case and all faulty cases The signatures of the responses are stored andorganized in the dictionary Ambiguity sets are put together as a single entry Aftertest, the measured signatures are compared with those stored in the dictionary forthe fittest to decide the faults The fault dictionary method has the smallest after-testcomputation levels mainly resulting from the comparison of measured test data withthose already stored in the dictionary to decide the faults Because of this, the fault

dictio-2 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

dictionary method is used practically in the fault diagnosis of analogue and signal circuits, especially for single hard-fault diagnosis The drawback of the method

mixed-is the large number of SBT computations that are needed for the construction of afault dictionary, especially for multiple-fault and soft-fault diagnosis of a large cir-cuit Methods for effective fault simulation and large-change sensitivity computationare thus needed [6–10] Tolerance effects need to be considered as simulations areconducted at nominal values for fault-free components

The parameter identification approach calculates all actual component values from

a set of linear or non-linear equations after test and compares them with their nominalvalues to decide which components are faulty [13–17] The method is useful forcircuit design modification and tuning There is no restriction on the number offaults and tolerance is not a problem in this method because the method targets allactual component values However, the method normally assumes that all circuitnodes are accessible and thus it is not practical for modern IC diagnosis [15, 16] Inaddition, some parameter identification requires solving non-linear equations [13, 14],which is computationally demanding especially for large-scale circuits The parameteridentification method has thus become more of a topic of theoretical interest in circuitdiagnosis, in contrast to circuit analysis and circuit design The only exception isperhaps the optimization-based identification technique [17] that can have limitedtests for approximate, but optimized, component value calculation The optimization-based method will be discussed in the context of the neural network approach inChapter 3

The fault verification method [18–39] is concerned with fault location of analoguecircuits with a small number of test nodes and a limited number of faults by using lin-ear diagnosis equations Indeed, modern highly integrated systems have very limitedexternal accessibility and normally only a few components become faulty simulta-neously Under the assumption that the number of faults is fewer than the number ofaccessible nodes, the fault locations of a circuit can be determined by simply checkingthe consistency of a set of linear equations Thus, the SAT computation burden ofthe method is small The fault verification method is suitable for all types of fault,and component values can also be determined after fault location Tolerance effectsare, however, of concern in this method because fault-free components are assumed

to take their nominal values The fault verification method has attracted considerable

attention, with the k-fault diagnosis approach [18–39] being widely investigated This chapter systematically introduces k-fault diagnosis theory and methods for

both linear and non-linear circuits as well as the derivative class-fault diagnosisapproach We also give a general overview of recent research in fault diagnosis ofanalogue circuits Throughout the chapter, a unified discussion is adopted based onthe fault incremental circuit concept In Section 1.2, we introduce the fault incremen-

tal circuit of linear circuits and discuss various k-fault diagnosis methods including

branch-, node- and cutset-fault diagnoses and various practical issues such as nent value determination and testability analysis and design A class-fault diagnosistheory without structural restrictions for fault location is introduced in Section 1.3,which comprises both algebraic and topological classification methods In Section 1.4,the fault incremental circuit of non-linear circuits is constructed and a series of linear

compo-methods and special considerations of non-linear circuit fault diagnosis are discussed.

We also introduce some of the latest advances in fault diagnosis of analogue circuits

in Section 1.5 A summary of the chapter is given in Section 1.6

The k-fault diagnosis methods [18–39] have been widely investigated because of

various advantages such as the need for only a limited number of test nodes and use

of linear fault diagnosis equations It is also practical to assume a limited number of

simultaneous faults The k-fault diagnosis theory is very systematic and is based on

circuit analysis and circuit design methods

1.2.1 Fault incremental circuit

Consider a linear circuit, which contains b branches and n nodes Assume that the

circuit does not contain controlled sources and multi-terminal devices The branchequation in the nominal state can be written as

Note thatX bcan be used to judge whether a branch or component is faulty or not

by verifying if the corresponding element inX bis non-zero

Equation (1.4) can be considered to be the branch equation of a circuit with thebranch current vector beingI b, the branch voltage vector beingV band the branch

admittance matrix being Y b.X bcan be viewed as excitation sources due to faults theso-called fault compensation sources We call this circuit a fault incremental circuit.Assuming that the nominal circuit and faulty circuit have the same normal or testinput signals, the subtraction of the inputs of the two circuits will be equal to zero,that is, an open circuit for a current source and a short-circuit for a voltage source

in the fault incremental circuit Also, note that the fault incremental circuit has thesame topology as the nominal circuit By applying Kirchhoff’s current law (KCL)

4 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

and Kirchhoff’s voltage law to the fault incremental circuit, we can derive numerousequations useful for fault diagnosis of analogue circuits

For linear controlled sources and multi-terminal devices or subcircuits, we can alsoderive the corresponding branch equations in the fault incremental circuit [32–35]

For example, for a VCCS with i1= g m v2, it can be shown thati1= g m v2+ x1

in the fault incremental circuit, wherex1= g m (v2+ v2) This remains a VCCS

with an incremental current in the controlled branch, an incremental voltage in thecontrolling branch and a fault compensation current source in the controlled branch

For a three-terminal linear device, y-parameters can be used to describe its terminal

characteristics, with one terminal being taken to be common:

delta model is not preferred owing to the existence of loops (will become clear later),use of more branches and consequence of possible additional internal nodes

A fault incremental circuit will become a differential incremental circuit ifX b=

Y b (V b + V b) is replaced byX b = Y b V b The differential incremental circuit

is useful for differential sensitivity and tolerance effects analysis, whereas the faultincremental circuit can be used for large-change sensitivity analysis, fault simulationand fault diagnosis

1.2.2 Branch-fault diagnosis

Branch-fault diagnosis was first published by Biernacki and Bandler [18] and

gener-alised to non-linear circuits by Sun and Lin [32–34] and Sun [35] The k-branch-fault diagnosis method [18–23, 32–35] assumes that there are k-branch faults in the circuit and requires that the number of accessible nodes, m is larger than k As discussed

above, the change of a component’s value with respect to its nominal can be sented by a current source in parallel with the component and if the fault compensationsource current is non-zero, the component is faulty

repre-A branch is said to be faulty if its component is faulty

Consider a linear circuit with b branches and n nodes (excluding the ground node), of which m are accessible and l inaccessible Assume that the nominal circuit

and faulty circuit have the same current input, then the input current to an accessiblenode in the fault incremental circuit is zero On applying KCL to the fault incremental

circuit, that is, A I b = 0 (where A is the node incident matrix) and noting that V b=

ATV n(whereV nis the nodal voltage increment vector), and on substituting it inEquation (1.4) we can derive:

where Z nb = (AY b AT)−1A and X b = Y b (V b + V b ) as given in Equation (1.5).

Dividing Z nb = [Z mbT, Z lbT]TandV n = [V mT, V lT]Taccording to nal (accessible) and internal (inaccessible) nodes, the branch-fault diagnosis equationcan be derived as

and the formula for calculating the internal node voltages is given by

For ease of understanding and derivation, we assume no tolerance initially If there

are only k branches that are faulty and k < m For the k faulty branches corresponding

to the k-column matrix Z mk in Z mb, because only the elementsX kcorresponding to

the k faulty branches in X bare non-zero, Equation (1.7) becomes:

Suppose that rank[Z mk ] = k If rank[Z mk,V m ] = k, Equation (1.9) is consistent.

We can solve the equation to obtain the following solution:

X k = (ZT

mk Z mk )−1ZT

The non-zero elements ofX kin Equation (1.10) indicate the faulty branches By

checking consistency of the equations of different k branches, we can determine the

k faulty branches Because we do not know which k components are faulty, we have

to consider all possible combinations of k out of b branches in the CUT If there are more than one k-branch combinations whose corresponding equations are consistent, the k faulty branches cannot be uniquely determined, as they are not distinguishable from other consistent k-branch combinations.

More generally, the k-fault diagnosis problem is to find the solutions of X b

from the underdetermined equation in Equation (1.7), which contains only k

non-zero elements This further becomes a problem of checking the consistency of aseries of overdetermined equations similar to Equation (1.9) corresponding to all

k-branch combinations A detailed discussion of the problems and methods can be

found in References 18 and 26

After location of the k faulty branches, we can calculate V lusing Equation (1.8),thenV = ATV n, and further we can calculateY from Equation (1.5)

6 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

1.2.3 Testability analysis and design for testability

A general mathematical algebraic theory and algorithms for solving k-fault diagnosis equations that are suitable for all k-fault diagnosis methods such as branch-, node-

and cutset-fault diagnosis have been thoroughly and rigorously studied in Reference

26 Several interesting and useful theorems and algorithms have been proposed In

this section, we focus on topological aspects of k-fault diagnosis This is because

topological testability conditions are more straightforward and useful than algebraicconditions Checking topological conditions is much simpler than verifying algebraicconditions, as the former can be done by inspection only, while the latter requiresnumerical computation Topological conditions can also be used to guide design forbetter testability through selection of test nodes, test input signals and topologicalstructures of the CUT Sun [22] and Sun and He [23] have investigated testability

analysis and design, on the basis of k-branch-fault diagnosis and k-component value identification methods In this section, we discuss topological aspects of k-fault diag-

nosis, including topological conditions, testability analysis and design for testability,mainly based on the results obtained in References 22, 23 and 32–34

Definition 1.1 A circuit is said to be k-branch-fault testable if any k faulty branches can be determined uniquely from test input, accessible node voltages and nominal component values.

As we have discussed in Section 1.2.2, the equation of the k faulty branches is consistent If in the CUT, there are more than one k-branch combinations whose corre-

sponding equations are also consistent, then we will be unable to determine the faultybranches through consistency verification and thus the circuit is not testable There-fore, it is important to investigate testability conditions The following conditions can

be demonstrated

Theorem 1.1 The necessary and almost sufficient condition for k −branch faults to

be testable is that for all (k + 1)-branch combinations, the corresponding equation

coefficient matrices are of full rank, that is, rank [Z m (k+1) ] = k + 1.

So there are two algebraic requirements that are important: rank[Z mk ] = k and

rank[Z m (k+1) ] = k + 1 The first one is for the equation to be solvable, which is

always assumed to be true and the second is for a unique solution In the following,

we will give the topological equivalents of both

Definition 1.2 A cutset is said to be dependent if all accessible nodes and the reference node are in one of the two parts into which the cutset divides the circuit.

A simple dependent cutset is one in which there is only one inaccessible node inone part

Theorem 1.2 The necessary and almost sufficient condition for rank [Z mk ] = k of

all k-branch combinations is that the CUT does not have any loops and dependent cutsets which contain ≤ k branches.

Theorem 1.3 The necessary and almost sufficient condition for k-branch faults to

be testable (rank [Z m (k+1) ] = k + 1 for all (k + 1)-branch combinations) is that the

CUT does not have any loops and dependent cutsets that contain (k + 1) branches When k = 1, the necessary and almost sufficient condition for a single branchfault to be testable becomes that the circuit does not have any two branches in parallel

or forming a dependent cutset

A loop is called the minimum loop if it contains the fewest number of branchesamong all loops A dependent cutset is called the minimum dependent cutset it con-

tains the fewest number of branches among all dependent cutsets Denote lminand

cminas the number of branches in the minimum loop and minimum dependent cutset,respectively Then we have the following theorems

Theorem 1.4 The necessary and almost sufficient condition for k-branch faults to

be testable is k < lmin−1 if lmin≤ cminor k < cmin− 1 if cmin≤ lmin.

It is necessary to find out loops and dependent cutsets to determine lminand cmin

To seek loops is relatively easy, which can be conducted in the CUT, N However,

dependent cutsets are a little difficult to look for, especially for large circuits Thefollowing theorem provides a simple method for this purpose, that is, to find dependent

cutsets in N0, instead of N, equivalently.

Theorem 1.5 Let N0be the circuit obtained by connecting all accessible nodes to the reference node in the original circuit N Then all cutsets in N0are dependent and

N0contains all cutsets in N.

Note that k-branch-fault testability is dependent on both loops and dependent

cut-sets Increasing the number of branches in the minimum loop and minimum dependentcutset may allow more simultaneous branch faults to be testable This is useful when

k is not known.

It is also noted that a non-dependent cutset does not pose any restriction on bility Whether or not a cutset is dependent will depend on the number and position

testa-of accessible nodes Therefore, proper selection testa-of accessible nodes can change the

dependency of a cutset and thus the testability of k-branch faults The greater the

number of nodes accessible the smaller will be the number of dependent cutsets Ifall circuit nodes are accessible, there will be no dependent cutset Testability will

then be completely decided by the condition on loops, that is, k < lmin− 1 ing different accessible nodes may change a dependent cutset to a non-dependentcutset, thus improving testability However, selection of accessible nodes will notchange the conditions on loops Therefore, if testability is decided by loop conditions

Choos-only, for example, when l ≤ c , changing accessible nodes will not improve the

8 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

testability However, since dependency of cutsets is related to the number and tion of accessible nodes, when testability is decided by conditions on cutsets only,

posi-we will want to select accessible nodes to eliminate dependent cutsets or increasethe number of branches in the minimum dependent cutset to improve the testability

To increase the number of branches in the minimum dependent cutset, it is alwaysuseful to choose those nodes containing a smaller number of branches as accessiblenodes, because all branches connected to an inaccessible node constitute a dependentcutset Generally, to choose some node in the part without the reference node of thecircuit that a dependent cutset divides as an accessible node can make the minimumdependent cutset not dependent Finally, the number of accessible nodes must belarger than the number of faulty branches, as is always assumed If possible, havingmore accessible nodes is always useful as in many cases we do not know exactly howmany faults may happen and the number of dependent cutsets may also be reduced

In summary, we need to meet m ≥ k + 1, lmin> k + 1 and cmin> k + 1.

For a more graph-theory-based discussion of testability, readers may refer toReference 23 where detailed testability analysis and design for testability proceduresare given and other equivalent testability conditions are proposed

We can enhance testability of a circuit by using multiple excitations For example,

by checking the invariance of the k component values under two different excitations,

we can identify the k faulty components The CUT can now have (k+1)-branch loopsand dependent cutsets, as in these cases we can still uniquely determine the faultybranches Using multiple excitations, all circuits will be single-fault diagnosable.This will be detailed on the basis of a bilinear method in the next section

1.2.4 Bilinear function and multiple excitation method

The k-branch combination test can be repeated for different excitations To generate

two excitations, the same input signal can be applied to two different accessiblenodes or two input signals with different amplitudes can be applied to the sameaccessible node The real fault indicator vectors obtained from different excitations

should be in agreement Below, a two-excitation method for k-branch-fault location

and component value identification is given

On the basis of the k-branch-fault diagnosis method in Section 1.2.2, assuming that

rank[Z mk ] = k we can derive the following bilinear relation mapping the measured

node voltage space to the component admittance space as [21]:

col(Y k ) = diag[AT

component values under different excitations for a unique identification of the faultybranches and components

If we use two independent current excitations with the same frequency and late col(Y k )s of all k-component combinations under each excitation, as col(Y k )1and col(Y k )2, respectively, and by denoting r k = col(Y k )1−col(Y k )2, we can

calcu-determine the k −faulty branches by checking if r k is equal to zero This methodcan realize the simultaneous determination of the faulty branches and faulty compo-nent values as calculated under any excitation The multiple excitation method can

enhance diagnosability Equivalent faulty k-branch combinations can be eliminated

as for these k-branch combinations, r kis not equal to zero (because component values

of real fault-free k-branch combinations will change with different excitations) Now, the only condition for the unique identification of k faulty components is that rank

[Z mk ] = k or the k branches do not form loops or dependent cutsets Thus, during the checking of different combinations of k components, once a k-component com-

bination is found to have r k = 0, we can stop further checking and this k-component

combination is the faulty one For a.c circuits, multiple test frequencies may also beused, however, component valuesR, L, C rather than their admittances should be

used since admittances are frequency dependent [21] A similar bilinear relation andtwo-excitation method for non-linear circuits [39] will be discussed in Section 1.4.2

1.2.5 Node-fault diagnosis

Node-fault diagnosis was first proposed by Huang et al [24] and generalised to

non-linear circuits by Sun [35, 36] A node is said to be faulty if at least one of the branchesconnected to it is faulty Instead of locating faulty branches in a circuit directly, welocate the faulty nodes It is assumed that the number of faulty nodes is smaller thanthe number of accessible nodes

Similar to the derivation of the branch-fault diagnosis equation, applying KCL tothe fault incremental circuit, we have

where

X n = Y n (V n + V n ) = AY b AT(V n + V n )

Assume that the circuit has m external nodes and l internal nodes Dividing Z nn =[Z mnT,

Z lnT]TandV n = [V mT,V lT]T accordingly, the node-fault diagnosis equationcan be derived from Equation (1.12) as [24, 35, 36]:

and the formula for calculating the internal node voltages is given by

Assume that there are only k faulty nodes and k < m Then checking the consistency

of all possible combinations of the k nodes we can locate the faulty nodes from Equation (1.14) Node-fault diagnosis may require less computation owing to n < b

10 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

and is less restrictive in topological structures than branch-fault diagnosis However,further location of faulty branches and determination of faulty component valuesrequire additional computation and thus additional topological restrictions

After faulty node location, we can easily determine that all branches connected tofault-free nodes are not faulty All possible faulty branches are connected to the faultynodes and the ground However, not every such branch may be faulty After faultynode location and considering that the internal node voltages can be calculated usingEquation (1.15), the faulty branches and faulty component values may be determined

by Equation (1.16) [36]:

However, we should note that if the number of possible faulty branches is larger

than the number of faulty nodes, k then it may not be possible to locate the faulty

branches using this equation This is the case when the possible faulty branchesform loops Otherwise, the node incident matrix corresponding to the possible faultybranches connected to the faulty nodes is left invertible There are topological restric-tions on this method; the requirement of a full column rank requires that the possiblefaulty branches do not form loops A graph method has been proposed for locatingfaulty branches in a faulty circuit with the fault-free nodes and associated branchestaken away [36] A multiple excitation method will be given in the next section whichwill overcome the above limitations

1.2.6 Parameter identification after k-node fault location

This section addresses how to determine the faulty component values after k-node

fault location For branch-fault diagnosis, after fault location we can easily determinethe values of the faulty components,Y k, fromX k = Y k (V k + V k ) as V kcan

be obtained withX kbeing a known excitation The bilinear relation method can also

be used as discussed in Section 1.2.4 Furthermore, the general bilinear relations ofanalogue circuits given in References 7, 8 and 20–22 may also be used to determinethe faulty component values as well

After fault location using node-fault diagnosis, determination of faulty componentvalues is not so simple Below we present a method for this, which has not been

published in the literature Assume that there are only k faulty nodes, the ith faulty node contains m i branches, i = 1, 2, …, k Without loss of generality, for the ith faulty node we derive the component value determination equations The jth branch connected to node i in the fault incremental circuit in Section 1.2.1 can be described as

i j = y j v j + y j (v j + v j )

Applying KCL to node i, we have:

(v1+ v1)y1+ (v2+ v2)y2+ · · · + (v mi + v mi )y mi

= −(y1v1+ y2v2+ · · · + y mi v mi )

Note that after faulty node location, all internal node voltages can be calculated

Thus, all branch voltages can be computed So applying m excitations with the same

frequency, we can obtain the following identification equations:

(v1+ v1) (1) y1+ (v2+ v2) (1) y2+ · · · + (v mi + v mi ) (1) y mi

= −(y1v1(1) + y2v2(1) + · · · + y mi v mi (1) )

(v1+ v1) (2) y1+ (v2+ v2) (2) y2+ · · · + (v mi + v mi ) (2) y mi

= −(y1v1(2) + y2v2(2) + · · · + y mi v mi (2) )

(v1+ v1) (mi) y1+ (v2+ v2) (mi) y2+ · · · + (v mi + v mi ) (mi) y mi

= −(y1v1(mi) + y2v2(mi) + · · · + y mi v mi (mi) )

To solve the equations fory1, y2, …, y mi, the coefficient voltage matrix

must be of full rank This requires application of m iindependent excitations with thesame frequency If we include the frequency in the coefficients and try to determine

R, C, L directly, then multiple test frequencies may also be used to obtain m i

independent equations

If we do the same for all k faulty nodes, we can determine all faulty component

values, as every faulty component must be connected to one of the faulty nodes.However, this method may require too many equations and excitations,

m i andmax{m i}, respectively According to node-fault diagnosis, all branches connected tothe non-faulty nodes are fault free and they are known after faulty node location Onlythose components in the branches between faulty nodes or faulty nodes and groundneed to be determined Thus, the method can be simplified

Assume that only the first h i branches of node i are not connected to fault-free nodes, i = 1, 2, , k Then only h iindependent excitations are required Because

(v1+ v1) (hi) y1+ (v2+ v2) (hi) y2+ · · · + (v hi + v hi ) (hi) y hi

= −(y1v1(hi) + y2v2(hi) + · · · + y mi v mi (hi) )

In the simplest case of h i= 1, we will have:

y1= −(y1v1+ y2v2+ · · · + y mi v mi )/(v1+ v1)

If we do the same simplification for all k faulty nodes, we can determine all faulty

component values, but with the total number of equations reduced by

12 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

solved twice Since once ay j is obtained from one faulty node, it can be used as

a known value for the other faulty node, then the other faulty node should have oneequation less to solve Theoretically, the minimum number of equations needed is thenumber of branches between faulty nodes or the faulty nodes and ground

A faulty node that has a grounded branch is said to be independent because itcontains a branch that is not owned by other faulty nodes Otherwise, it is said to bedependent A dependent node may not need to be dealt with as its branch componentvalues can be obtained by solving other faulty node equations In practice we can usethe following steps to make sure that we solve the minimum number of equations

Supposing that the first h i branches are not connected to the faulty nodes that

have already been dealt with, then only h iindependent excitations are needed for

node i The new equations can be written as

of excitations needed for the node could be smaller than the number of its faultybranches

1.2.7 Cutset-fault diagnosis

Research on multiple-fault diagnosis has been mainly focused on branch- and fault diagnosis, as discussed in the previous sections This section is concerned withcutset-fault diagnosis as proposed and investigated for both linear and non-linearcircuits by Sun [25, 37, 38] Relations of branch-, node- and cutset-fault diagnosismethods are also discussed

node-A branch is said to be measurable if the two nodes to which the branch is nected are accessible The branch voltage of a measurable branch can be obtained

con-by measurement In a linear circuit, assume that a tree has t branches of which p branches are measurable and the other q branches are not measurable, p + q = t We use V b and V t to represent the branch voltage vector and tree branch voltage vector,

respectively V p and V q are the measurable tree branch voltages and unmeasurabletree branch voltages, respectively

Applying KCL to the fault incremental circuit, that is, D I b= 0 and noting that

V b = DTV t , where D is the cutset incident matrix and using Equations (1.4) and

it must correspond to the faulty cutsets

Dividing Z tt = [Z ptT, Z qtT]T and V t = [V pT,V qT]T, the cutset-faultdiagnosis equation can be derived from Equation (1.17) as [25]:

The method proposed for parameter identification for node-fault diagnosis inSection 1.2.6 may also be easily extended to be suitable for the cutset-fault diagnosisbased on dealing with trees, not nodes, owing to similarity between the node- andcutset-fault diagnosis methods

The node-fault diagnosis method can be seen as a special case of the cutset-faultdiagnosis method when a cutset reduces to a node The cutset-fault diagnosis method

is more flexible and less restrictive than the branch- and node-fault diagnosis methods.This is due to the selectability of trees A proper choice of a tree can not only locatethe faulty cutsets uniquely, but can also locate the faulty branches in the faulty cutsets

As in branch- and node-fault diagnosis, only voltage measurements are required incutset-fault diagnosis

14 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

1.2.7.1 Selection of tree

An analogue circuit contains several possible trees, which give us an extra degree

of freedom to consider which tree or trees should be used in order to enhance nosability [25, 28] Different trees correspond to different cutsets and thus differentfaulty cutsets The faulty cutsets for one tree may not be uniquely locatable, but thefaulty cutsets for another tree could be locatable Different trees will also result indifferent branch-cutset relations; the faulty branches may be easier to determine fromthe faulty cutsets of one tree than those of another Interesting illustrations can befound in References 25 and 28

diag-When choosing a tree we should try to use all accessible nodes to make themost measurable tree branches to allow the maximum number of faulty cutsets to bediagnosable for the available accessible nodes For this purpose, it may be useful to

know the relation between the tree voltages and node voltages, that is, V t = A t V n,

where A tis the node incident submatrix corresponding to the tree branches

1.2.7.2 Branch-fault diagnosis equations based on cutset analysis

Branch-fault diagnosis equations are derived on the basis of nodal analysis in tion 1.2.2 Here we derive another set of branch-fault diagnosis equations on thebasis of cutset analysis This has not been investigated in the literature By cut-

Sec-set analysis of the fault incremental circuit we can obtain Z tb X b = V t, where

Z tb = (DY b DT)−1D Dividing Z tb = [Z pbT, Z qbT]T, the branch-fault diagnosisequation can be derived as

and the formula for calculating the internal tree branch voltages is given byV q=

Z qb X b Equation (1.22) may benefit from the selectability of trees

1.2.7.3 Relation of branch-, node- and cutset-fault diagnosis

The three fault vectors are linked byX n = AX b, X t = DX b andX n =

A t X t The matrix A t is invertible and the inversion of it can be obtained using asimple graph algorithm If any ofX b,X nandX t is known, the other two may

be found using the relations Also, the cutset-fault diagnosis method will become thenode-fault diagnosis method when a cutset reduces to a node

1.2.7.4 Loop- and mesh-fault diagnosis

Theoretically, we can also very easily define and derive the loop- and mesh-fault

diagnosis problems, but unfortunately they are not useful practically because for loop faults and k-mesh faults, loop- and mesh-fault diagnosis methods require that

k-m (>k) loop and k-m k-mesh currents should be k-measurable, respectively Measuring

branch currents is not preferred in ICs as it will need breaking the connections (not

in situ) The loop- and mesh-fault diagnosis methods are mentioned here merely for

theoretical completeness of k-fault diagnosis.

1.2.8 Tolerance effects and treatment

In all k-fault diagnosis methods, all non-faulty components are assumed to take on

their nominal values However, in actual circuits, the values of non-faulty nents will randomly fall in the tolerance range due to the existence of tolerance Thereliability of diagnosis results will thus be affected; sometimes this may result in falsefault declaration or real faults missed and thus make fault diagnosis less accurate Thetolerance effect will become more severe when the fault and tolerance ratio is small

compo-To solve this problem, one method is to apply a threshold reflecting tolerance effectsfor compatibility checking Another method is to use some optimization method tosearch for the faults by minimizing an objective error function We can also discounttolerance effects from the actual circuit to have a modified circuit with net changescaused by the faults only This method may need a separate tolerance analysis ofthe CUT by using the differential incremental circuit concept, a special case of thefault incremental circuit, as mentioned in Section 1.2.1 Some detailed discussion oftolerance effects on fault diagnosis may be found in References 4 and 5

Multiple-fault diagnosis has been discussed in Section 1.2 It mainly contains

branch-, node- and cutset-fault diagnosis methods and all k-fault diagnosis methods

can be extended to non-linear circuits as will be discussed in Section 1.4 The mary advantage is the linearity of the methods, even for non-linear circuits However,they have rather strong topological conditions which not only limit their applica-tion, but also make design for testability difficult Some researchers have tried toassuage the topological restrictions by applying multiple excitations This worksonly to some extent, since quite tight topological constraints still exist There istherefore a need for the development of fault diagnosis methods without topolog-

pri-ical limitations This was first realized by Togawa et al [27] who proposed, a

TF-equivalence class approach for the branch-fault diagnosis problem A more eral class-fault diagnosis method was proposed in Reference 28 This method not onlyapplies to branch-fault diagnosis, but is suitable for node- and cutset-fault diagnosisproblems as well References 29 and 30 have studied branch-set-based class-faultdiagnosis from a topological point of view A technique of classifying branch setsdirectly from the circuit graph was presented A method of systematic formation

gen-of the class table similar to a fault dictionary was also given Another cal approach for class-fault diagnosis was presented in Reference 31, with a newtype of class being defined This method guarantees that every class has a full rankbranch set for consistency verification The class-fault diagnosis technique aims atisolating the faulty region or subcircuit, has no topological restrictions and requiresonly modest after-test computation It can be considered as a combination of theSBT and SAT methods After determination of the faulty class, one can also locatethe faulty branch set in the faulty class This section gives a detailed discussion

topologi-of class-fault diagnosis, mainly based on the work by Sun [28–30] and Sun andFidler [31]

16 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

1.3.1 Class-fault diagnosis and general algebraic method

for classification

A general algebraic approach for class-fault diagnosis was proposed in Reference

28 This method is suitable for classifications based on any k-fault diagnosis method

including branch-, node- and cutset-fault diagnosis However, rather than putting theproblem in a too mathematical way, without loss of generality we use the branch-fault diagnosis equation to introduce the algebraic classification method to make thegeneral method sound more ‘physical’

As discussed in Section 1.2.2, k-branch-fault diagnosis involves a number of tions corresponding to different k-branch combinations We use S i = {i1, i2, , i k}

equa-to denote the ith set of k branches If S i contains all k faulty branches in the circuit, it

is called the faulty set If S i is faulty, then Z mki X ki = V m , where Z mki = [z i1 , z i2,

…, z ik ], z ij is the jth column vector of matrix Z mki and X ki = [x i1 , x i2 , …, x ik]T S iissaid to be of full column rank if rank[Z mki ] = k It is assumed that all k-branch sets

are of full column rank We denote:

Z∗

mki = Z mki (Z mkiTZ mki )−1Z mkiT= Z mki Z mki −L (1.23)

From Equations (1.9), (1.10) and (1.23), we know that for the faulty branch set

Z∗

mki V m = V m , which is equivalent to rank[Z mki,V m ] = k.

Definition 1.3 The k-branch set S j is said to be dependent on the k-branch set S i if

Z mki∗Z

mkj = Z mkj

The dependence relation is an equivalence relation We can use this relation to

classify all k-branch sets, that is, if S i and S j are dependent, S i and S j belong tothe same class; otherwise they fall into two different classes It can be proved that

Z∗

mki Z mkj = Z mkjis equivalent to rank[Zmki , z j α ] = k, α = 1, 2, …, k.

Theorem 1.6 Assume that j = i If for j = β1, β2, …, β u , we have Z∗

mki Z mkj = Z mkj

and for all other j, Z∗

mki Z mkj = Z mkj , then k-branch sets S i , S β1 , S β2, , S βu form a class.

Theorem 1.7 Assume j = i1, i2, …, i k If for j = γ1,γ2, , γ e , Z∗

mki z j = z j and for

all other j, Z∗

mki z j = z j , the k-branch sets formed by k + e branches i1, i2, …, i k and

γ1, γ2, …, γ e form a class.

Theorem 1.8 If for some (k + 1) branches, rank [Z m (k+1) ] = k, then all k-branch

sets formed by these (k + 1) branches belong to the same class.

If Z∗

mki V m = V m , the k-branch set S iis said to be consistent It can be proved

that if S i and S jare dependent, they both are consistent or both are inconsistent It can

also be proved that if S i and S j are consistent simultaneously, S i and S jare dependent

A class C i is said to be faulty if it contains the faulty branch set A class C iis said

to be consistent, if the k-branch sets in the class are consistent If S is faulty, it is

consistent and if S i is inconsistent, it is not faulty Thus, the faulty class must bethe consistent class and an inconsistent class is not faulty Owing to the equivalencerelation, if there is one consistent branch set, the class is consistent and if there is oneinconsistent branch set, the class is inconsistent There is only one consistent class andthe faulty class can be uniquely determined Clearly, we can identify the faulty class

by checking only one branch set in each class and once a consistent set/class is found,

we do not need to check any more as the remaining classes are not faulty When thenumber of classes is equal to the number of branch sets, that is, each class contains

only one branch set, the class-fault diagnosis method reduces to the k-branch-fault

diagnosis method

In the above we assume that all k-branch sets are of full column rank In the cases

that there are some branch sets which are not of full column rank, the method can also

be used with some generalization This can be possible by putting all k-branch sets

which are not of full rank together as a class, called the non-full rank class We can findall branch sets with rank[Z mki ] < k by checking determinants det(ZT

mki Z mki ) = 0.

For all full rank branch sets we do classification and identification as normal If anormal full rank class is faulty by consistency checking, the fault diagnosis is com-pleted If none of the full rank classes is faulty, we judge the non-full rank class asthe faulty class

Classification should be conducted from k = 1 to k = m − 1, unless we know the k value Classes are determined for each k value using the method given in the

above A class table similar to a fault dictionary can be formed before test Z∗

mki of

one branch set (any one of the k-branch sets) in each class computable before test

can also be included in the class table for consistency checking to identify the faultyclass after test

The class-fault diagnosis method may be suitable for relatively large-scale circuits

as it targets at a faulty region and a class may actually be a subcircuit In fault diagnosis, the after-test computation level is small because classification can beconducted and the class table can be constructed before test The number of classes issmaller than the number of branch sets and due to the unique identifiability, we can stopchecking once a class is found to be consistent thus the times of consistency checking

class-is at worst equal to the number of classes There class-is also no need for testability designdue to the unique identifiability The method has no restriction; the only assumption

is m > k The method can also be used to classify k-node sets and k-cutset sets [28].

After the determination of the faulty class, we can further determine the k faulty branches If the faulty class contains only one k-branch set, the branch set is the

faulty Otherwise, the two-excitation methods based on the invariance of the faultycomponent values may be used to identify the faulty branch set from others in thefaulty class

The class-fault diagnosis technique is the best combination of the SBT and SATmethods, retaining the advantages of both It uses compatibility verification of linearequations, but the class table is very similar to a fault dictionary It can deal withmultiple soft faults and the after-test computation level is small Topological classi-fication methods to be introduced in the next section can make classification simplerand computation before test smaller

18 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

1.3.2 Class-fault diagnosis and topological technique for classification

On the basis of the algebraic classification theory discussed in the above, we present

a topological classification method First we give some definitions If some of thebranches in a loop also constitute a cutset, we say the loop contains a cutset If some

of the branches in a cutset also constitute a loop, we say the cutset contains a loop

Theorem 1.9 We can find the k-branch sets which are not of full rank topologically

as below [29, 30].

1 When branches i1, i2, …, i k form a loop or dependent cutset, S i is not of full rank.

2 The (k + 1), k-branch sets formed by the (k + 1) branches in a (k + 1)-branch

loop containing a dependent cutset are not of full rank The (k + 1), k-branch

sets formed by the (k + 1) branches in a (k + 1)-branch-dependent cutset

containing a loop are not of full rank.

3 The k-branch sets formed by the (k + 1) branches in a (k + 1)-branch loop

or dependent cutset that shares k branches with another loop containing a dependent cutset are not of full rank The k-branch sets formed by the (k + 1)

branches in a (k + 1)-branch dependent cutset or loop that shares k branches

with another dependent cutset containing a loop are not of full rank.

Theorem 1.10 For all normal full rank k-branch sets we can classify them topologically as below [29, 30]:

1 The (k + 1), k-branch sets in a (k + 1)-branch loop belong to the same class.

The (k + 1), k-branch sets in a (k + 1)-branch dependent cutset belong to the

same class As a special case of the latter, supposing that an inaccessible node has (k + 1) branches, the (k + 1), k-branch sets formed by the (k + 1) branches

connected to the node belong to the same class.

2 When a (k +1)-branch loop or dependent cutset shares k branches with another

(k + 1)-branch loop or dependent cutset, all k-branch sets formed by the

branches in the both belong to the same class.

3 In a (k + 2)-branch loop containing a dependent cutset, all those k-branch sets

that do not form the dependent cutset belong to the same class Similarly, in a (k + 2)-branch dependent cutset containing a loop, all those k-branch sets that

do not form the loop belong to the same class.

To use the topological classification theorems, we need to find all related loops

and dependent cutsets in the CUT in order to find all non-full rank k-branch sets and classify all full rank k-branch sets Dependent cutsets can be found equivalently

in N0, since it has the same dependent cutsets as those in N, as shown in Theorem

1.5 A systematic algorithm for the construction of the complete dictionary-like classtable has been given in References 29 and 30 The faulty class can be identified

by verifying the consistency of any k-branch set in each class, as discussed in the

preceding section If none of the full rank classes is consistent, then the non-full rankclass is the faulty class

1.3.3 t-class-fault diagnosis and topological method for classification

We take a different view of class-fault diagnosis, which may not necessarily be based

on the k-fault diagnosis method We focus on the effects of faults at the output,

V m Two sets of different numbers of faulty branches can cause the sameV m.For example, using the current source shifting theorems [62], in a three-branch loop

of the fault incremental circuit, the effect of the three branches being faulty can

be equivalent to any two branches being faulty as shifting one fault compensationcurrent source to other two branches would not changeV m They can thus be put

into the same class Using the branch-fault diagnosis equation Z mb X b = V m,

this means that for the two-branch set, Z m2 X2 = V m and for the three-branch

set, Z m3 X3 = V m Although Z m3 is not of full rank due to the loop, Z m2 is offull rank So even if there are three faulty branches, by checking the consistency of

Z m2 X2= V mwe can still identify the faulty class Note here that two is not the

number of real faults and the number of faults is k= 3 Generalizing the above simpleconsideration, another topological method of class-fault diagnosis of analogue circuits

is described in Reference 31 This method allows the k faulty-branch set to be not of

full rank, which can not be dealt with in a normal way in the methods presented above

For the two-branch sets, we have Z mi X i = Z mj X j = V m Note that i and

j can be equal, for example, i = j = k, which is the case of class-fault diagnosis

in Sections 1.3.1 and 1.3.2 and they can also be different, which is a new case To

reflect the difference we use the phrase t-dependence to define the relation, where

t will become clear later It is evident that this dependence relationship is also an

equivalence relation So we can classify branch sets in a circuit by combining alldependent branch sets into a class Obviously each concerned branch set can lie inone and only one class A branch set is a class itself only if it is not dependent onother branch sets A topological classification theorem is given below

Theorem 1.11 [31] The (t + 1)-branch set and (t + 1), t-branch sets formed by the

(t + 1) branches in a (t + 1)-branch loop belong to the same class The (t + 1)-branch

set and (t + 1), t-branch sets formed by the (t + 1) branches in a (t +

1)-branch-dependent cutset belong to the same class As a special case of the latter, supposing that an inaccessible node has (t + 1) branches connected to it, the (t + 1)-branch set

and (t + 1), t-branch sets formed by the (t + 1) branches belong to the same class.

Note thatX b can be looked upon as a fault excitation current source vector.Therefore, the above theorem can be easily proved by means of the theorems ofcurrent source and voltage source shift [62] On the basis of the above theorem some

20 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

more complicated classification theorems may be developed by making full use ofthe transitive property of the dependence relation

1.3.3.2 Classification technique

We discuss how to use Theorem 1.11 to classify branch sets of a circuit For any

t-branch set, 1 ≤ t ≤ m −1, where m is the number of accessible nodes, find all other

j-branch sets, j ≥ t, which are dependent on the t-branch set Then put these j-branch sets in the class in which the t-branch set stays In this way the t-branch set is the

smallest in the sense that it has the smallest number of branches compared with otherbranch sets in the same class In order to do classification more efficiently and makethe class table more regular, it may be beneficial to take the following measures:

1 Branches in a set are arranged in the order of small numbers to large ones

2 Branch sets in a class are ranked according to the number of branches contained

in the sets, from small to large If two sets have the same number of branches,the set with the smaller branch numbers should be put before the other one

3 Class order numbers, beginning with 1, are determined by branch order numbers

of the first set in each class, from small to large

4 The whole classification process may start from t = 1 and end at t = m−1, that

is, first find out all classes whose smallest branch sets have only one branch,then those of which the smallest sets have two branches, and so on

1.3.3.3 Identification of the faulty class

From the classification technique given above we can see that there is at least one

t-branch set in each class and the first set in a class is definitely a t-branch set From

that we also know that the submatrices Z mt of Z mb corresponding to t-branch sets are of

full column rank Thus, the faulty class can be identified by verifying the consistency

of the corresponding equation Z mt X t = V m of the first (or any) t-branch set in each class The whole identification process should start from t = 1 and end with

t = m−1 In most cases, once consistency is satisfied for some t-branch set, the class

in which it lies is the faulty class and no further verification is needed

In a mathematical sense, a class is the maximum class, meaning that its branchsets are not dependent with the sets of other classes Thus, there is only one consistent

class and this class is the faulty class Therefore, for t < m, the faulty class is uniquely

identifiable without any other conditions

1.3.3.4 Location of the faulty branch set

After determining the faulty class we can also further distinguish the faulty branch

set Assume that there are k simultaneously faulty branches in the circuit The

k faulty-branch set must be in the faulty class If the faulty class contains only one

branch set (it must be a t-branch set), then the branch set must be faulty Thus, we have k = t (note that k is the number of faulty branches) Otherwise, branch sets in the faulty class may be divided into two parts; one contains all t-branch sets, the other accommodates all j-branch sets, j ≥ t + 1 Note that Z mt corresponding to a t-branch

set is of full column rank, whereas Z mj corresponding to a j-branch set, j ≥ t + 1, is

not of full column rank [29, 30] It is known that parameter values of the faulty branchset are independent of excitations Thus, by changing excitations and verifying the

invariance of all parameter values in each t-branch set we can determine the faulty set if it is a t-branch set and know that k = t and we can be sure that the faulty set

is a j-branch set, j ≥ t + 1 and k > t if all t-branch sets are variant If further there

is only one j-branch set in the second part of the faulty class (in this event, we have

j = t +1), then it can be definitely deduced that this set is the faulty set and k = t +1.

It should be pointed out that in the latter two cases, unlike k in other

multiple-fault diagnosis methods in Section 1.2 and the class-multiple-fault diagnosis method in Sections

1.3.1 and 1.3.2, here t is no longer the number of faulty branches of the circuit The approach only requires t < m, not k < m as do others When k ≥ m, other methods

will fail, but this method is still valid as long as t < m (this case is probable owing

to the fact that t ≤ k) This implies that the method needs fewer accessible nodes (m = t +1, not k +1) or in other words, it may diagnose more simultaneous faults In

addition, the method also applies to the situation that Z mk is not of full column rank(usually because faulty branches form loops or dependent cutsets)

Analogue circuit fault diagnosis has proved to be a very difficult problem Faultdiagnosis of non-linear circuits is even more difficult due to the challenge in faultmodelling and the complexity of non-linear circuits There has been less work onfault diagnosis of non-linear circuits than that of linear circuits in the literature Aspractical circuits are always non-linear; devices such as diodes, transistors, and so

on, are non-linear, development of efficient methods for fault diagnosis of non-linearcircuits become particularly important Sun and co-workers [32–39] have conductedextensive research into fault diagnosis of non-linear circuits and in References 32–39they have proposed a series of linear methods This section summarizes some of theresults

1.4.1 Fault modelling and fault incremental circuits

Fault modelling is a difficult task For linear circuits, component value deviationfrom their nominal value is used to judge whether or not a circuit has faults Param-eter identification methods were developed to try to calculate all component values

to determine such deviations Subsequently, modelling faults by equivalent sation current sources was proposed In this method, the component value change isequivalently described by a fault excitation source If the fault source current is notequal to zero, the corresponding component is faulty Here the real component valuesare not the target, but the incremental current sources caused by faults which are used

compen-as an indicator/verifier This modelling method hcompen-as resulted in a large range of faultverification methods For non-linear circuits, fault modelling by component valuedeviation is possible, but is not a convenient or preferred choice, as in many cases

22 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

there is no direct single value which can represent the state of a non-linear componentlike a linear one A non-linear component often contains several parameters and anyparameter-based method may result in too many non-linear equations Fortunately,the fault compensation source method can be easily extended to non-linear circuits.Any two-terminal non-linear component can be represented by a single compensa-tion source no matter how many parameters are in the characterization function Theresulting diagnosis equations are accurately (not approximately) linear, although thecircuit is non-linear, thus reduced computation, time and memory This is obviously

an attractive feature

In the fault modelling of non-linear circuits [32–35], the key problem is that achange in the operation point of a non-linear component could be caused by either afault in itself or by faults in other components The fault model must be able to tellthe real fault from the fake ones Whether or not a non-linear component is faultyshould be decided by whether the actual operating point of the component falls on tothe nominal characteristic curve, so as to distinguish it from the fake fault due to theoperation point movement of the non-linear component caused by the faults in othercomponents

Consider a nominal non-linear resistive component of the characteristic of

If the non-linear component is not faulty, the actual branch current and voltage due

to faults in the circuit will satisfy:

that is, the actual operation point remains on the nominal non-linear curve, although

moved from the nominal point (i, v ); otherwise, the component is faulty since the real

operation point shifts away from the nominal non-linear curve, which means that thenon-linear characteristic has changed

Introducing

we can then usex to determine whether or not the non-linear component is faulty If

x is not equal to zero, the component is faulty, otherwise it is not faulty according to

Equation (1.25) Using Equations (1.26) and (1.24), we can writei = g(v + v) − g(v) + x and further:

Equation (1.27) can be seen as a branch equation wherei and v are the branch

current and voltage, respectively; y is the branch admittance and x is a current source.

Suppose that the circuit has c non-linear components and all non-linear components

are two-terminal voltage controlled non-linear resistors and have the characteristic

i = g(v) For all non-linear components, we can write:

Equation (1.29) can be treated as the branch equation corresponding to the

non-linear branches in the fault incremental circuit where Y c is the branch admittancematrix with individual element given by Equation (1.28),I c, the branch current vec-tor,V cthe branch voltage vector andX cthe current source vector with individualelement given by equation (1.26)

Suppose that the CUT has b linear resistor branches, the branch equation of the

linear branches in the fault incremental circuit was derived in Section 1.2.1 and isrewritten with new equation numbers for convenience:

Assume that the circuit to be considered has a branches, of which b branches are linear and c non-linear, a = b + c The components are numbered in the order of

linear to non-linear elements The branch equation of the fault incremental circuit can

be written by combining Equations (1.30) and (1.29) as

whereI a=[I bT,I cT]T,V a=[V bT,V cT]T,X a= [X bT,X cT]Tand Y a=diag{Yb , Y c}

Note that the fault incremental circuit is linear, although the nominal and faultycircuits are non-linear This will make fault diagnosis of non-linear circuits much sim-pler, in the same complexity of linear circuits Also note that during the derivation,

no approximation is made So the linearization method is accurate The traditionallinearization method uses the differential conductance at the nominal operation point,

∂g(v)/∂v, causing an inaccuracy in the calculated x and thus an inaccuracy in the

fault diagnosis Similar to fault diagnosis of linear circuits based on the fault mental circuit, we can derive branch-, node- and cutset-fault diagnosis equations ofnon-linear circuits based on the formulated fault incremental circuit

incre-Non-linear controlled sources and three-terminal devices can also be modelled

For example, for a non-linear VCCS with i1= g m (v2), we have i1= y m v2+ x1

in the fault incremental circuit, where y m = [g m (v2+v2)−g m (v2)]/v2andx1=

i1+ i1− g m (v2+ v2) This remains a VCCC with the incremental current of the

controlled branch, incremental voltage of the controlling branch and a compensationcurrent source in the controlled branch

Suppose that a three-terminal non-linear device, with one terminal as common,has the following functions:

i1= g1(v1, v2)

i2= g2(v1, v2)

24 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

We can derive the corresponding branch equations in a T model in the faultincremental circuit, given by

preferred because of loops and more branches

1.4.2 Fault location and identification

Assume that a non-linear resistive circuit has n nodes (excluding the reference node),

m of which are accessible Also assume that all non-linear branches are measurable

so that Y ccan be calculated onceV cis measured Using the fault incremental circuit

we can derive the branch-fault diagnosis equation as [32, 33, 35]:

and the formula for calculating the internal node voltages is given by

where [Z maT, Z laT]T= Z na = (AY a AT)−1A and [ V mT,V lT]T= V n

According to the k-branch-fault diagnosis theory, solving X afrom Equation

(1.33) we can locate the k faulty branches; the non-zero elements in X bindicate thefaulty linear branches and non-zero elements inX cdetermine the faulty non-linearbranches Owing to the introduction of the linear fault incremental circuit, the whole

theory and methods of k-branch-fault diagnosis of linear circuits, including both the

algebraic and topological techniques discussed in Section 1.2, are directly applicable

to the non-linear circuit fault diagnosis It is noted that the branch-fault diagnosis tion can also be formulated based on the cutset analysis as discussed in Section 1.2.7.Also, as for linear circuits, using the fault incremental circuit of non-linear circuits,

equa-we can derive the node- [35, 36] and cutset-fault diagnosis equations for non-linearcircuits [37, 38], which are the same as those for linear circuits in Section 1.2 in form.Now, a node and a cutset may contain some non-linear components A faulty nodeand a faulty cutset could thus be caused by either faulty linear branches or faultynon-linear branches or both After determiningX n andX t, we can locate the

faulty nodes and cutsets by non-zero elements inX nandX trespectively Furtherdetermination of the faulty branches (linear or non-linear) can be conducted based on

X n = AX aandX t = DX afor node- and cutset-fault diagnosis respectively

In the above we have assumed that all non-linear branches are measurable Thus,non-linear components are connected among accessible nodes and ground and are inthe chosen tree as measurable tree branches This may limit the number of non-linearcomponents and when choosing test nodes we need to select those nodes connected

by non-linear components This may not be a serious problem, since in practical tronic circuits and systems, linear components are dominant; there are usually only avery few non-linear components in an analogue circuit It is noted that the coefficients

elec-of all diagnosis equations are determined after test as calculation elec-of Y ccan only beobtained afterV cis measured However, this is a rather simple computation Also,partitioning the node admittance matrix or the cutset admittance matrix according toaccessible and inaccessible nodes or tree branches, only the block of the dimension of

m ×m or p×p corresponding to the accessible nodes or tree branches is related to Y c

All the other three blocks can be obtained before test because they do not contain Y c

Using block-based matrix manipulation, the contribution of the m × m or p × p block

can be moved to the right-hand side to be with the incremental accessible node or treebranch voltage vector for after-test computation and thus the main coefficient matrix

in the left-hand side of the diagnosis equations can still be computed before test [35]

In the next section, we will further discuss other ways of dealing with non-linearcomponents

1.4.2.1 Bilinear function for k-fault parameter identification

For non-linear circuit fault diagnosis we focus on fault location by compensationcurrent sources rather than parameter identification, as for non-linear components,defining deviation in branch admittances is not possible or would not provide anyuseful further information about the faulty state or nature We can, however, continue

to use the deviation model for linear components Equation (1.31) to determine thevalues of the faulty linear components

Generally, we can determine the values of the faulty linear components using themethods similar to those used for linear circuits after branch-, node- and cutset-faultdiagnosis, treatingX c as known current sources Here we mention that bilinearrelations between linear component value increments and accessible node voltageincrements can also be established for non-linear circuits This allows us to determinethe values of faulty linear components and develop a two-excitation method with

enhanced diagnosability Suppose that there are k1faulty linear components and k2

faulty non-linear components, k1+k2= k On the basis of the branch-fault diagnosis

method and equations derived using the nodal analysis method, for non-linear circuits,

we can also derive a bilinear relation given by Reference 39:

col(Y k1 ) = {diag[A k1T(V n + T nm V m )]}−1W k1k Z mk −L V m (1.35)

where W k1k =[U k1k1 , O k1k2 ] and U k1k1 is a unity matrix of dimension of k1× k1and

O k1k2 is a zero matrix of k1×k2 The meanings of the other symbols including Z mk −L

and T are the same as those in Section 1.2.4

26 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

Similar to the linear circuits in Section 1.2.4, the bilinear relation inEquation (1.35) can be used to calculate the faulty linear component values Also,

a two-excitation method can be developed for fault location based on the bilinear

relation If the calculated k1 linear component values are the same under the two

independent excitations, the corresponding k branches including the k2non-linearcomponents are faulty Multiple excitations can be achieved by applying the samecurrent source to different test nodes or different current sources to the same test node.According to the above discussion it is also clear that class-fault diagnosis methods

in Section 1.3 are also directly applicable to non-linear circuits based on the faultincremental circuit

1.4.3 Alternative fault incremental circuits and fault diagnosis

The fundamental issues of fault diagnosis of non-linear circuits have been discussedabove Now we address some alternative, possibly more useful, solutions for differentsituations of non-linear circuit fault diagnosis

1.4.3.1 Alternative fault models of non-linear components [33, 34]

To lift the requirement that all non-linear components are measurable, we can do someequivalent transformations to the non-linear branches For a non-linear component

i = g(v), as modelled in Section 1.4.1, the corresponding branch equation in the

fault incremental circuit is given by Equation (1.27) If we add to and subtract from

Equation (1.27) the same item yv, the equation remains the same That is

Equation (1.38) has the same form as Equation (1.27) So, the corresponding

branch in the fault incremental circuit has yas the branch admittance andxas thecompensation current source

Two points are interesting One is that y can be any value and can thus be setarbitrarily before test If we use Equation (1.38) for all non-linear components, theadmittance matrix of the fault incremental circuit will be known before test and soare all diagnosis equation coefficients The other is thatxmay not be zero even for

a fault-free non-linear component unless yis chosen to be equal to y However, if wecan determinex,x may be determined from Equation (1.37) after y is calculated.

The true fault state of the non-linear component can still be found

1.4.3.2 Quasi-fault incremental circuit and fault diagnosis [33, 34, 36]

We consider two cases here The first case is that we use the alternative model forall non-linear branches, irrespective of whether or not a non-linear component is

measurable On the basis of Equations (1.38) and (1.37) we can write the branchequation for all non-linear branches as

Because Y c can be chosen before test, diagnosis equation coefficients can beobtained before test This can reduce computation after test and is good for onlinetest Because all non-linear branches will be in the faulty branch set and any node

or cutset that contains a non-linear component will behave as a faulty one whether

or not the non-linear component is faulty, the number of possible faulty branches,nodes and cutsets for branch-, node- and cutset-fault diagnosis will increase Thismay require more test nodes for a circuit that contains more non-linear components

In the search of faults, only the k-branch sets that contain all non-linear components,

k-node sets containing all nodes connected by non-linear components and k-cutset

sets containing all cutsets with non-linear components need to be considered

1.4.3.3 Mixed-fault incremental circuit and fault diagnosis [37–39]

The second case is that for measurable non-linear components we still use the originalmodel Equation (1.27), while for unmeasurable non-linear components we use the

alternative model of Equation (1.38) Assuming that there are c1 measurable

non-linear branches and c2unmeasurable non-linear branches, c1+ c2= c, then we have

the corresponding branch equations of the respective non-linear branches in the faultincremental circuit as