Bài giảng Thiết kế logic số (VLSI design): Chương 4.3 - Trịnh Quang Kiên

Quy trình thiết kế trên FPGAISE Intergrated Software Enviroment... Quy trình thiết kế trên FPGADesign and implement a simple unit permitting to speed up encryption with RC5-similar ciph

Thiết kế logic số

(VLSI design)

Bộ môn KT Xung, số, VXL

06/2010

Quy trình thiết kế trên FPGA

ISE (Intergrated Software Enviroment)

Quy trình thiết kế trên FPGA

Design and implement a simple unit permitting to

speed up encryption with RC5-similar cipher with

fixed key set on 8031 microcontroller Unlike in

the experiment 5, this time your unit has to be able

to perform an encryption algorithm by itself,

executing 32 rounds…

Library IEEE;

use ieee.std_logic_1164 all ;

use ieee.std_logic_unsigned all ;

entity RC5_core is

port (

clock, reset, encr_decr: in std_logic;

data_input: in std_logic_vector( 31 downto 0 );

data_output: out std_logic_vector( 31 downto 0

out_full: in std_logic;

key_input: in std_logic_vector( 31 downto 0 );

key_read: out std_logic;

);

end AES_core;

Specification (Lab Experiments)

VHDL description (Your Source Files)

Functional simulation

Post-synthesis simulation Synthesis

Quy trình thiết kế trên FPGA

Implementation

Configuration

Timing simulation

On chip testing

VHDL and Schematic

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity compare_module is

Port (value : in std_logic_vector (3 downto 0);

res : out std_logic);

end compare_module;

architecture Behavioral of compare_module is

signal std : std_logic_vector (4 downto 0);

begin val <= '0' & value;

process (val, std) begin

HDL

Create Technology schematic (optional)

Create RTL schematic (optional)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity compare_module is

Port (value : in std_logic_vector (3 downto 0);

res : out std_logic);

end compare_module;

architecture Behavioral of compare_module is

signal std : std_logic_vector (4 downto 0);

LED1 : out STD_LOGIC;

LED2 : out STD_LOGIC;

);

end sp3_led;

architecture Structure of sp3_led is

signal SW8_IBUF_31 : STD_LOGIC;

Synthesis – Technology Schematic

Synthesis – RTL Schematic

Synthesis – UCF file

# IO location defination

NET "HIGH_voltage" LOC = P102;

NET "LOW_voltage" LOC = P100;

NET "voltage[0]" LOC = P160;

NET "voltage[1]" LOC = P161;

NET "voltage[2]" LOC = P162;

NET "voltage[3]" LOC = P163;

# Timing constraint

INST "LOW_voltage" TNM = "OUT_REG";

INST "HIGH_voltage" TNM = "OUT_REG";

NET "voltage[0]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP

Implementation

Mapping

Post-map simulation model

Post-map static Timing

Place & Route

Post-place-route static timing

Post-place-route simulation model

Electronic Design

Interchange Format

Circuit netlist Timing Constraints

Synthesis

Mapping

Chương III FPGA

Place & Route

FPGA Verification

Verification Function Timing On-circut

testing

Giao thức truyền tin nối tiếp

IDLE START DATA PARITY STOP IDLE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 115

14 13

SAMPLE RX

Máy trạng thái khối UART

IDLE

START FRAME DETECTOR RECEIVE

DATA

CNT16 = 8 and RX = 1

RX = 0, Rx_Reg = 1

CNT16 = 8 and RX = 0 CNT_BIT = 8

Sơ đồ khối UART

CNT RESET ENABLE

CNT RESET ENABLE

Khối giao tiếp VGA

Tín hiệu quét VGA

Sơ đồ khối VGA

HORIZONTAL COUNTER

VERTICAL COUNTER

DCM_BLOCK (optional)

CHARACTER_

ROM (optional)

DATA_RAM (optional)

RGB GENERATOR

HS

VS

R G B

DCM_CLK CLK_IN