Three phase scvd based boost inverter with low common mode voltage for transformerless photovoltaic grid connected system doctor of philosophy major electrical engineering

Modified Three-Phase SCVD Based Boost Inverter with Constant Common-Mode Voltage for Photovoltaic Application ..... a Space vector in output of three phase inverter; b Switching pattern

Doctoral Dissertation

A Three-Phase SCVD Based Boost Inverter with Low Common Mode Voltage for Transformerless

Photovoltaic Grid-Connected System

Department of Electrical Engineering Graduate School, Chonnam National University

Tran Tan Tai

August 2020

A Three-Phase SCVD Based Boost Inverter with Low Common Mode Voltage for Transformerless

Photovoltaic Grid-Connected System

Department of Electrical Engineering Graduate School of Chonnam National University

Tran Tan Tai

Supervised by Professor Joon-Ho Choi

A dissertation submitted in partial fulfillment of the requirements for the Doctor ofPhilosophy in Electrical Engineering

Committee in Charge:

Prof Young-Cheol Lim

Prof In-Seon Yeo

Assit Prof Dong-Hee Kim

Dr Minh-Khai Nguyen

Prof Joon-Ho Choi

August 2020

Contents

Contents i

List of Figures iii

List of Tables vii

List of Abbreviations viii

Abstract ix

Chapter 1 Introduction 1

1.1 Research Background 1

1.1.1 Modulation-Based Methods 4

1.1.2 Topology-Based Methods 11

1.2 Research Focus 15

1.3 Research Contributions 15

1.4 Organization of the Dissertation 16

Chapter 2 Proposed Three-Phase SCVD Based Boost Inverter 18

2.1 Introduction 18

2.2 Proposed Topology 19

2.2.1 Common-Mode Leakage Current Model 19

2.2.2 Operation Principles 21

2.3 SVM Control Techniques for Proposed Topology 27

2.3.1 DPWM technique for Proposed Topology 27

2.3.2 Zero-Even PWM (ZEPWM) Technique for Proposed Topology 29

2.3.3 Near State PWM (NSPWM) Technique for Proposed Topology 31

2.4 Summary 31

Chapter 3 Modified Three-Phase SCVD Based Boost Inverter with Constant Common-Mode Voltage for Photovoltaic Application 34

3.1 Introduction 34

3.2 Proposed Topology 34

3.3 PWM Control Strategy for Introduced Topology 41

3.4 Comparison Between the Proposed Inverters and Existing Topologies 42

Chapter 4 Simulation and Experimental Verifications 45

4.1 Three-Phase SCVD Based Boost Inverter 45

4.1.1 Simulation Verifications 45

4.1.2 Experimental Verifications 58

4.2 Modified Three-Phase SCVD Based Boost Inverter 71

4.2.1 Simulation Verifications 71

4.2.2 Experimental Verifications 75

Chapter 5 Conclusions 81

References 82

Abstract by Korean 91

Acknowledgement 92

List of Figures

Fig 1.1 Conventional VSIs topology (a) Equivalent circuit; (b) Voltage vectors in the

conventional VSIs 3

Fig 1.2 CM model of conventional VSIs topology 4

Fig 1.3 Voltage vectors and the area definition (a) Type A areas (b) Type B areas 6

Fig 1.4 Demonstration of the voltage vectors and the reference vector for ASZPWM1 in area A1 7

Fig 1.5 Demonstration of the voltage vectors and the reference vector for NSPWM in area B2 8

Fig 1.6 Demonstration of the voltage vectors and the reference vector for RSPWM3 in area B1 9

Fig 1.7 Four-leg topology for transformerless PV systems 10

Fig 1.8 Transformerless H7 grid-connected inverter topology 11

Fig 1.9 Transformerless voltage-clamping topology 12

Fig 1.10 Transformerless H-8 grid-connected inverter topologies (a) type 1 in [67]; (b) type 2 in [69] 13

Fig 1.11 Three-phase zero-voltage state rectifier topology for operating transformerless photovoltaic (PV) systems 14

Fig 2.1 Proposed three-phase SCVD based boost inverter 18

Fig 2.2 Common-mode model of introduced three-phase SCVD based boost inverter (a) Simplified common-mode model and (b) Simplified equivalent 19

Fig 2.3 Configuration of the introduced SCVD based boost inverter for state 0 and state 1 (a) State 0 (000) and (b) State 1 (100) 23

Fig 2.4 Configuration of the introduced SCVD based boost inverter for state 2 and state 3 (a) State 2 (110) and (b) State 3 (010) 24

Fig 2.5 Configuration of the introduced SCVD based boost inverter for state 4 and

state 5 (a) State 4 (011) and (b) State 5 (001) 25

Fig 2.6 Configuration of the introduced SCVD based boost inverter for state 6 and state 7 (a) State 6 (101); (b) State 7 (111) 26

Fig 2.7 DPWM technique for introduced SCVD based boost inverter (a) Space vector in output of three phase inverter; (b) Switching pattern in sector 1; (c) CMV of the conventional VSIs compared to the introduced SCVD based boost inverter under DPWM technique 28

Fig 2.8 ZEPWM technique for introduced SCVD based boost inverter (a) Space vector in output of three phase inverter; (b) Switching pattern and CMV of introduced SCVD based boost inverter in sector 1 30

Fig 2.9 NSPWM technique for introduced SCVD based boost inverter (a) Space vector in output of three phase inverter; (b) Switching pattern and CMV of introduced SCVD based boost inverter in sector 1 32

Fig 3.1 Modified three-phase SCVD based boost inverter 35

Fig 3.2 Configuration of the introduced mSCVD based boost inverter for state 0 and state 1 (a) State 0 (000) and (b) State 1 (100) 36

Fig 3.3 Configuration of the introduced mSCVD based boost inverter for state 2 and state 3 (a) State 2 (110) and (b) State 3 (010) 37

Fig 3.4 Configuration of the introduced mSCVD based boost inverter for state 4 and state 5 (a) State 4 (011) and (b) State 5 (001) 38

Fig 3.5 Configuration of the introduced mSCVD based boost inverter for state 6 and state 7 (a) State 6 (101); (b) State 7 (111) 39

Fig 3.6 Block diagram of the PWM control generation module 42

Fig 4.1 V g , V PN , V AB and load currents under DPWM technique 46

Fig 4.2 FFT of V AB and load current under DPWM technique 46

Fig 4.3 V g , V PN , V AB and load currents under ZEPWM technique 47

Fig 4.4 FFT of V and load current under ZEPWM technique 47

Fig 4.5 V g , V PN , V AB and load currents under NSPWM technique 48

Fig 4.6 FFT of V AB and load current under NSPWM technique 48

Fig 4.7 V Ca , V Cb , V DSa and V DSb under DPWM strategy 49

Fig 4.8 V Ca , V Cb , V DSa and V DSb under ZEPWM strategy 50

Fig 4.9 V Ca , V Cb , V DSa and V DSb under NSPWM strategy 51

Fig 4.10 Phase-A voltage and simulated CMV under DPWM technique 52

Fig 4.11 Phase-A voltage and simulated CMV under ZEPWM technique 53

Fig 4.12 Phase-A voltage and simulated CMV under NSPWM technique 54

Fig 4.13 FFT of simulated CMV (a) DPWM technique, (b) ZEPWM technique, and (c) NSPWM technique 55

Fig 4.14 Grid voltage, grid current and simulated CMC for the conventional VSIs with DPWM technique 56

Fig 4.15 Grid voltage, grid current and simulated CMC for the introduced SCVD based boost inverter with DPWM technique 56

Fig 4.16 Grid voltage, grid current and simulated CMC for introduced SCVD based boost inverter with NSPWM technique 57

Fig 4.17 Grid voltage, grid current and simulated CMC for introduced SCVD based boost inverter with ZEPWM technique 57

Fig 4.18 Prototype photo of the introduced SCVD based boost inverter 59

Fig 4.19 V g , V PN , V AB and FFT of V AB under DPWM technique 60

Fig 4.20 Load currents and their FFT under DPWM technique 60

Fig 4.21 V g , V PN , V AB and FFT of VAB under ZEPWM technique 61

Fig 4.22 Load currents and their FFT under ZEPWM technique 61

Fig 4.23 V g , V PN , V AB and FFT of V AB under NSPWM technique 62

Fig 4.24 Load currents and their FFT under NSPWM technique 62

Fig 4.25 V Ca , V Cb , V DSa and V DSb under DPWM technique 64

Fig 4.26 V , V , V and V under ZEPWM technique 65

Fig 4.27 V Ca , V Cb , V DSa and V DSb under NSPWM technique 66

Fig 4.28 Phase-A voltage and CMV under DPWM technique 67

Fig 4.29 Phase-A voltage and CMV under ZEPWM technique 68

Fig 4.30 Phase-A voltage and CMV under NSPWM technique 69

Fig 4.31 FFT of CMV under various PWM (a) DPWM, (b) ZEPWM, and (c) NSPWM 70

Fig 4.32 V g , V PN , V AB and load currents of the introduced mSCVD based boost inverter 72

Fig 4.33 FFT of V AB and i a of the introduced mSCVD based boost inverter 72

Fig 4.34 Voltage across additional switches (a)-(b) From top to bottom: V DSa , V DSb, V DSc and V DSd 73

Fig 4.35 Waveforms capacitor voltage of introduced mSCVD based boost inverter From top to bottom: V Ca , V Cb and V Cc 74

Fig 4.36 Phase-A voltage, simulated CMV, and simulated CMC of introduced mSCVD based boost inverter 74

Fig 4.37 Prototype photo of the introduced mSCVD based boost inverter 75

Fig 4.38 V PN , V AB and V g of the introduced mSCVD based boost inverter 76

Fig 4.39 Load currents and their FFT of the introduced mSCVD based boost inverter 76

Fig 4.40 Experimental waveforms of additional switches From top to bottom: (a)-(b) V DSd , V DSc , V DSb , and V DSa 77

Fig 4.41 Experimental waveforms of capacitor voltages From top to bottom: V Ca , V Cb, and V Cc 78

Fig 4.42 Phase-A voltage and CMV of the introduced mSCVD based boost inverter 78

Fig 4.43 Measured efficiency comparison between the SCVD based boost inverter with the mSCVD based boost inverter 79

List of Tables

Table 1.1 The corresponding CMV value under eight switching states 2

Table 2.1 State of each of common-mode voltage and semiconductor devices of

proposed SCVD based boost inverter for different switching states 21

Table 3.1 State of each of common-mode voltage and semiconductor device of

introduced mSCVD based boost inverter for different switching states 35

Table 3.2 Comparison of the introduced configurations and existing topologies for the

same dc-bus voltage (V PN) 43

Table 4.1 Simulation and Experimental Parameters of introduced SCVD based boost

inverter 45

Table 4.2 Simulation and Experimental Parameters of introduced mSCVD based boost

inverter 71

List of Abbreviations

PV photovoltaic

VSIs voltage source inverters

EMI electromagnetic interference

EMC electromagnetic compatibility

CM common-mode

CMV common-mode voltage

CMC common-mode current

PWM pulse width modulation

THD total harmonic distortion

SVM space vector modulation

A Three-Phase SCVD Based Boost Inverter with Low Common Mode Voltage for Transformerless Photovoltaic Grid-

Connected System

Tran Tan Tai

Department of Electrical Engineering Graduate School of Chonnam National University (Supervised by Professor Joon-Ho Choi)

(Abstract)

This study deals with a new type of inverter called a three-phase SCVD based boost inverter The introduced structure is a combination of an SCVD network and the three-phase bridge to restrict the common-mode voltage Therefore, the introduced inverter can produce

a high output voltage from the low input voltage The DC-bus voltage of the introduced solution stands at twice of the input voltage Moreover, the variation in common-mode voltage can o be restricted within one-sixth of DC-bus voltage Modeling, circuit analysis, operating principles, and a comparison between the introduced SCVD based boost inverter with the other VSIs are performed To confirm the performance improvements of the introduced SCVD based boost inverter, a preliminary prototype of the introduced SCVD based boost inverter is built in the laboratory and the simulation studies based on PLECS environment and experimental studies are performed Besides that, a modified SCVD based boost inverter is also introduced to step up the DC-bus voltage to triple of input voltage instead of twice of input voltage like that in the proposed SCVD based boost inverter Furthermore, a common-mode voltage of the modified SCVD based boost inverter is

canceled through switching the four extra active-switches based on the Boolean logic function As a result, common-mode voltage is maintained as constant at the value of 0 V during all time Moreover, the voltage stress across additional semiconductor devices is standing at one-third of DC-bus voltage The simulation studies based on PLECS environment prove the effectiveness of the modified SCVD based boost inverter Finally, to validate the performance, operating principle, and feasibility of the modified SCVD based boost inverter, the experimental studies based on the laboratory prototype with a DSP F280049C are carried out.

Chapter 1 Introduction

1.1 Research Background

Perhaps no subject in the contemporary society is as attractive as the matter of energy crisis With the strong development of societies, the demand for electricity consumption is significantly rising Besides that, fossil energy resources such as natural gas, coal, and oil are increasingly depleted Therefore, the use of renewable energy sources is an effective way Renewable energy has a number of merits i.e its cheaper and pollution-free Solar energy is among the most popular sources of renewable energy However, Solar energy is different output characteristics, intermittent in nature, and often non-dispatchable Because of these, the grid-connected photovoltaic (PV) inverters execute the major role on the combination of renewable energy sources into distribution grids [1] and guarantee the requirements of the grid connections such as frequency, voltage, harmonic minimization, reactive and active power control The grid-connected PV inverters [2] can be sorted into the grid-connected PV inverters with galvanic isolation [3]-[6] and the grid-connected PV inverters without galvanic isolation [7]-[16]

For topologies using galvanic isolation at the grid side, the output DC voltage of solar cells is inverted into AC voltage and then delivered into the grid through the ac low-frequency transformer (LFT) and the output filter The LFT is heavy and big As a result, PV system becomes very bulky For topologies using galvanic isolation at the dc side, a high-frequency transformer (HFT) is used However, the HFT needs an extra power stage As a result, PV system becomes more complex as well as the system efficiency is reduced Transformerless grid-connected PV inverters receive increasingly more attractive in both academic and industry fields because of low cost, small weight/size, high efficiency, less complexity, and easy to install But removing the transformer makes power grid and the PV array has a direct electrical connection Because of the stray capacitance between PV array

and the ground of power grid, there will generate common-mode current if voltage across on the parasitic capacitance changes This current flows through the stray capacitor, which causes a lot of unwelcome problems such as serious EMI and insecurity, higher current harmonics, higher losses and the low reliability of the PV inverter systems [7]-[23] The CMC is greatly affected by the parasitic capacitance value The value of stray capacitance is determined by many elements such as PV panel, weather conditions, distance between cells, EMC filter

For this reason, to avoid the adverse effects, the common-mode current should be smaller than the VDE standard of 300 mA [24]-[25] Therefore, the common-mode current reduction of transformerless grid-connected PV inverters has become a hot issue these days The common-mode current (CMC) can be reduced by separating PV array away from the power grid during certain time intervals or limiting high frequency and amplitude of CMV

To restrict CMC according to the VDE standard, numerous interesting solutions have been proposed In general, these solutions can be fallen into two categories, namely the topology-based method and the modulation-based method

Table 1.1

THE CORRESPONDING CMV UNDER EIGHT SWITCHING STATES

Switching State Bridge States V CMV

Zero states State 0 000 0

State 7 111 V PN

odd states

State 1 100 V PN/3 State 3 010 V PN/3 State 5 001 V PN/3

even states

State 2 110 2V PN/3 State 4 011 2V PN/3 State 6 101 2V PN/3

where V PN is the DC-bus voltage across the H-bridge circuit

common-mode (CM) current, i CM is generated by high frequency voltage across on the parasitic capacitance between the earth ground and PV array The space-vector sectors are partitioned into two type regions as indicated in Fig 1.3 The CMV is calculated as follows:

3

AN BN CN

CM O

V V V

V V    (1.1)

where V AN , V BN , and V CN are three-phase voltages as indicated in Fig 1.1 and the point “N”

represents the negative terminal of the input source

As shown in Fig 1.1(b), there are eight switching states in the conventional VSIs Because of this, the CMV will be varied in case of different switching states As indicated in Table 1.1, the value of CMV changes from VPN/3 to 2VPN/3 during active states while the value of CMV is VPN or 0 in zero states As a result, the value of CMV changes from 0 to

VPN According to Table 1.1, by ignoring state 0 (000) and state 7 (111), the CMV can be reduced As discussed in [26]–[31], the active zero-state PWM methods (AZSPWM) utilizes

a group of the four active vectors to produce the reference vector In AZSPWM methods,

vectors V0 and V7 were ignored and compensated by two opposing active-vectors with the

equal time as the internal time of vectors V0 and V7 The choice of two opposite active vectors is determined by the location of the output voltage vector AZSPWM methods utilized with two near opposing active vectors are called AZSPWM1 and AZSPWM2 Besides that, AZSPWM method utilized a set of the two active vectors and their two opposite vectors is defined AZSPWM3 As a result, The CMV changes from VPN/3 to 2VPN/3 Like for instance, AZSPWM1 method in type A1 region as illustrated in Fig 1.4,

two zero vectors (V0 and V7) were replaced by the active vectors pairs of V3 and V6 As a

result, the two active vectors V1 and V2 are combined with two opposite vectors of V3 and V6

to produce the reference vector The optimal sequence of this case in type A1 region is

V3→V2→V1→V6→V1→V2→V3 Unlike AZSPWM1 method, the optimal sequence for AZSPWM2 method is V6→ V2→ V1→V3→V1→V2→V6 in type A1 region For AZSPWM3

method, the vectors V1 and V2 are complemented with the active zero pairs of V1 and V4 So,

only three active vectors V1 V2, and V4 are considered to produce the reference vector with

AZSPWM3 method The optimal sequence for AZSPWM3 method is V1→V2→V4→V2→V1

in type A1 region

Fig 1.3 Voltage vectors and the area definition (a) Type A areas (b) Type B areas

Fig 1.4 Demonstration of the voltage vectors and the reference vector

for ASZPWM1 in area A1

The linearity modulation range of AZSPWM1, AZSPWM2, and AZSPWM3 methods are similar to that of the conventional space vector PWM (SVPWM) method and conventional discontinuous PWM (DPWM) method However, the output current ripple under AZSPWM methods is high

Another fact to take into account is that the AZSPWM2 and AZSPWM3 methods will force simultaneous switching in different phase-legs while The AZSPWM1 method did not require simultaneous switchings Unlike the AZSPWM strategies, the NSPWM methods as discussed in [32]-[33] utilized a set of three neighbor active vectors to produce the reference vector For example, NSPWM method in type B2 region as demonstrated in Fig 1.5, the active vector states nearest to the reference voltage vector are utilized to synthesize the reference voltage vector As a result, the two active vectors V1 and V2 are accompanied

by the active vector of V3 to produce the reference vector The optimal sequence of this case

in type B2 region is V3→V2→V1→V2→V3 Similar to the active zero-state PWM, the value

of CMV under NSPWM method changes from VPN/3 to 2VPN/3 Furthermore, the output current ripple under NSPWM methods was lower than that of the active zero-state PWM methods Compared to the active zero-state PWM methods, the switching losses of inverter under NSPWM method are decreased significantly However, the linearity modulation range

of NSPWM strategy is limited from 0.66 to 1 The modulation index is defined as follows:

V3→V1→V1→V5→V1→V1→V3 The optimal sequence in type B2 region is

V4→V2→V6→V2→V4 The CMV with the RSPWM1 and RSPWM2 methods kept constant

at 2V PN /3 when utilizing a group of three odd active vectors (or V PN/3 when utilizing a group

of three even active vectors ) while CMV kept constant every 60o with the RSPWM3 method The linearity modulation range of the RSPWM1 and RSPWM2 methods is limited in range

of 0 to 0.57 while the linearity modulation range of RSPWM3 method is limited in range of

0 to 0.66 However, because of simultaneous switching in different phase-legs and low voltage utilization, and the application of RSPWM methods is restricted The Tri-State PWM

(TSPWM) method as discussed in [36] used a set of three vectors to synthesize the reference vector to restrict the amplitude of the CMV to VPN/3 in every switching period The TSPWM method is the same as NSPWM methods when the TSPWM method operated with modulation index in range of 0.66 to 1 In order to reduce both frequency and amplitude of CMV, Hybrid SVM methods were introduced in [37] With proposed Hybrid SVM methods, the frequency of CMV was triple of fundamental frequency while the amplitude of CMV was dropped to VPN/3 The voltage linearity of hybrid SVM methods is similar to voltage linearity of the conventional SVPWM and DPWM methods However, hybrid SVPWM methods have high switching loss and complexity With a third harmonic injection sinusoidal PWM (THISPWM) method as introduced in [38], both low-frequency and high-frequency CMV is reduced Besides that, the bus voltage utilization is the same as that in SVPWM method, the peak values of high-frequency CMV However, the THISPWM method has complex algorithm and CMV was only dropped to VPN/3

Fig 1.7 Four-leg topology for transformerless PV systems

In [52]-[62], three-phase four-leg inverters, where a fourth-leg is inserted into traditional H-