Bsi bs en 60747 16 10 2004

SEMICONDUCTOR DEVICES – Part 16-10: Technology Approval Schedule TA S f or monol thic microwa e integrated circ its 1.1 Sco e This TAS sp cifies the terms, def i ition , s mb ls, q al ty

Sem iconductor

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ICS 3 2 0

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Sum m ary of pag es

This d ocument comprises a f ont cov er, an inside font cov er,the EN title p g e,

p ges 2 to 5 , an inside b ck cov er and a b ck cov er

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document was last is ued

Am endm ents is ued sinc publ cation

EUR OPÄISCHE NORM September 2004

Euro e n Committee for Elec trot ec hnical Stan ardization

Comité Euro é n de Normalsat ion Electrotec niq e

Euro äis hes Komitee für Elek trot ec hnisc he Normu g

C ent ra l S e c ret a ria t: ru d St a s sa rt 3 5, B - 10 5 0 Brus se ls

© 2 0 CENELEC - A ll rig ts of e ploitat io in a y form a d b a y me n re erv ed wo dwid for CENELEC memb rs

ICS 31.2 0

En ls version

Semiconductor dev ices

Part 16-10: T echnology Approval Schedule (TAS)

for monol thic microwav e integrated circuits

(IEC 60747-16-10:2004)

Disposit ifs à semic onduct eurs

Part ie 16-10: Format -cadre

pour agrément de t echnologie (TA S)

pour circ uit s intégrés monolt hiques

(CEI 60747-16-10:2004)

Halbleit erbauelement e

Tei 16-10: Prüfplan für die

Tec hnik anerk ennung

(Tec nology A pprov al Sc edule - TAS)

für monolt hische int egriert e

Mik rowelensc halt k reise

(IEC 60747-16-10:2004)

T his Euro e n St an ard was a prov ed b CENELEC o 2 0 -0 -01 CENELEC memb rs are b u d to

comply with the CEN/CENELEC Int ern l Reg latio s whic h s p late the con itio s for givin this Euro e n

St an ard the status of a n tio al stan ard witho t a y alterat io

Up-to-d t e lsts a d biblo ra hical refere c es conc ernin suc h n t io al stan ards ma b o tain d o

a plcatio to the Ce t ral Secretariat or to a y CENELEC memb r

This Euro e n Stan ard e ists in thre ofic ial versio s (En lsh, Fre c h, Germa ) A v rsio in a y other

la g a e ma e b t ra slat io u d r the resp nsibi ty of a CENELEC memb r into it s own la g a e a d

n tifie to the Ce t ral Secretariat h s t he same st atus as the oficial v rsio s

CENELEC memb rs are the n tio al ele t rotec hnic al c ommit t ees of Austria, Belgium, Cy rus, Cz ec h

Rep blc, De mark, Estonia, Finla d, Fra ce, Germa y, Gre ce, Hu g ry, Icela d, Irela d, Italy, L tvia,

Lithu nia, L x mb urg, Malta, Netherla ds, Norwa , Pola d, Port ug l, Slovakia, Slo e ia, Sp in, Swe e ,

Switz erla d a d United Kin d m

The t ex t of doc ment 4 E/25 /FDIS, fut ure edit ion 1 of IEC 6 7 7-16-10, pre ared by SC 4 E,

Dis ret e semicon u t or devices, of IEC TC 4 , Semicon u t or devices, w as s bmit t ed t o t he

IEC-CENELEC p ralel v ote an was a prov ed by CENELEC as EN 6 7 7-16-10 on 2 0 -0 -01

The folowin dat es w ere fix ed:

– lat est date by whic the EN has t o b implement ed

at nat ional level by publcat ion of an identical

nat ional st an ard or by en orsement

– lat est date by whic the national st an ar ds conflct in

Anne ZA has b en ad ed by CENELEC

_ _

Endorsement notice

The t ex t of t he Int ernat ional St an ard IEC 6 7 7-16-10:2 0 w as a proved by CENELEC as a

Euro e n Stan ard w it hout an modificat ion

_ _

CONTENTS

INTRODUCTION 5

1 General 6

1.1 Sco e 6

1.2 Normative doc ments 6

1.3 Units, s mb ls an terminolog 7

1.4 Stan ard an prefer ed values .7

1.5 Definition 7

2 Definition of the comp nent tec nolog 9

2.1 Sco e 9

2.2 Des ription of activities an f low c arts .10 2.3 Tec nical a stract 10 2.4 Req irements for control of s bcontractors .13 3 Comp nent desig of MMICs 15 3.1 Sco e .15 3.2 Des ription of activities an f low c arts .15 3.3 Interaces .16 3.4 Val dation an control of the proces es .18 4 Mas man f acture .2

4.1 Sco e .2

4.2 Des ription of activities an f low c arts .2

4.3 Val dation an control of the proces es .2

4.4 Subcontractors, ven ors an internal s p l ers 2

5 Wafer f abrication of MMICs .2

5.1 Sco e .2

5.2 Des ription of activities an f low c arts .21

5.3 Eq ipment .2

5.4 Materials 2

5.5 Re-work 2

5.6 Val dation method an control of the proces es .2

5.7 Inter elation hip 2

6 Wafer pro in of MMICs 2

6.1 Sco e .2

6.2 Des ription of activities an f low c arts .2

6.3 Eq ipment .2

6.4 Test proced res 2

6.5 Inter elation hip 2

7 Bac -side proces f or bare c ip del very 2

7.1 Sco e .2

7.2 Des ription of activity an flow c arts .2

7.3 Eq ipment .3

7.4 Materials 3

7.5 Val dation method an control of the proces es .3

7.6 Inter elation hip 3

7.7 Val dity of rele se .31

8.1 Sco e .3

8.2 Des ription of activities an f low c arts .3

8.3 Materials, in p ction an han l n 3

8.4 Eq ipment .3

8.5 Re-work 3

8.6 Val dation an control of the proces es .3

8.7 Inter elation hips 3

9 Testing of MMICs .3

9.1 Sco e .3

9.2 Des ription of activities an f low c arts .3

9.3 Eq ipment .3

9.4 Test proced res 3

9.5 Interaces .3

9.6 Val dation an control of the proces es .4

9.7 Proces b u dary verification .4

9.8 Prod ct verification 4

10 Proces c aracterization 4

10.1 Identification of proces c aracteristic 4

10.2 Des ription of activities .4

10.3 Characterization proced res 4

1 Pac agin an s ip in 5

1 1 Des ription of activities an f low c arts .5

1 2 Interaces .51

1 3 Val dity of rele se .51

12 With rawal of Tec nolog Ap roval .5

Fig re 1 – Example flow c art of desig /man facture/est .14 Fig re 2 – Example flow c art of a desig 19 Fig re 3 – Tec nolog flow c art of the proces 2

Fig re 4 – Example flow c art for a wafer pro in 2

Fig re 5 – Example flow c art for a b c -side proces for b re c ip del very .3

Fig re 6 – Example f low c art for an as embly .3

Fig re 7 – Example f low c ar f or a testin 4

Fig re 8 – Typical f low c art for p c agin an s ip in 5

The req irements f or Tec nolog Ap roval for man f acturers of electronic an elec

tro-mec anical comp nents are given in QC 0 10 2-3, Clau e 6 The proced res f or a proval

defined in that clau e req ire the man f acturer to have avaia le an a pro riate Tec nology

Ap roval Sc ed le (TAS)

This s hed le def i es how the prin iples an req irements of QC 0 10 2-3, Clau e 6 are

a pl ed to monol thic microwave integrated circ its

SEMICONDUCTOR DEVICES –

Part 16-10: Technology Approval Schedule (TA S)

f or monol thic microwa e integrated circ its

1.1 Sco e

This TAS sp cifies the terms, def i ition , s mb ls, q al ty s stem, test, as es ment an

verif i ation method an other req irements relevant to the desig , man f acture an s p ly

of monol thic microwave integrated circ its in complan e with the general req irements of the

IECQ-CECC Sy tem f or electronic comp nents of as es ed q alty

1.2 Normativ doc me ts

The f ol owin ref eren ed doc ments are in isp n a le for the a pl cation of this doc ment

For dated ref eren es, only the edition cited a pl es For u dated referen es, the latest edition

of the referen ed doc ment (in ludin an amen ments) a pl es

IEC 6 0 7 (al p rts): L t ter symb ls to b used in el ectric l tec n log

IEC 6 0 0: Intern t ion l E le trot ec nic l Vo a ul ary

IEC 6 0 8 (al parts): E nviro me tal t esti ng

IEC 6 191-2: Mec a ic l st and ard isation ofsemic nd uct or d evic s – Part 2: Dime sions

IEC 6 617-DB

1

(al p rts): Gra hic l symb ls for diagrams

IEC 6 7 7-1: Semic nd uctor devic s – Discrete d evic s a d integrated circ its – Part 1:

Ge eral

IEC 6 7 7-16-1: Semic nd uctor devic s – Part 16-1: Microwa e int egrated circ its –

Amplifiers

IEC 6 7 7-16-2: Semic nd uctor devic s – Part 16-2: Microwa e int egrated circ its –

Fre u n y presc l ers

IEC 6 7 7-16-3: Semic nd uctor devic s – Part 16-3: Microwa e int egrated circ its –

Fre u n y c n erters

IEC 6 7 7-16-4: Semic nd uctor devic s – Part 16-4: Microwa e int egrated circ its –

Switch s

2

IEC 6 7 8-1: Semic nd uctor d evic s – I nt egrated circ its – P art 1: Ge eral

ISO 10 0: SI u its a d re omme d ations for the use of t heir mul tiples a d c rt ain other u its

———————

1

“DB” refers to th IEC o -ln d ta a e

2 To b p bls e

1.3 Units, s mbols a d terminology

Units, gra hical s mb ls, leter s mb ls an terminolog s al , whenever p s ible, b taken

f rom the f olowin doc ments:

IEC 6 0 7: L tter symb ls to b used in el ectric l tec n l og

IEC 6 0 0: Intern t ion l ele trot ec nic l v c b l ary

IEC 6 617-DB: Gra hic l symbols for d iagrams

ISO 10 0: SI u its a d re omme d ations for the use of t heir mul tiples a d c rt ain other u its

An other u its, s mb ls an terminolog sp cific to the s o e of this TAS s al b taken f rom

the relevant IEC or ISO doc ments l sted u der Normative doc ments

1.4 Sta dard a d pref er e v lue

Tec nolog Ap roval al ows the c stomization of the comp nent or proces to s it e c

c stomer The con entional con e t of prefer ed values may th s have lmited a pl cation

However, when international y recognized pref er ed values a ply these s ould b u ed, e.g

voltage, temp rature an dimen ion Ref eren e s al b made to the a pro riate IEC or ISO

For the purp ses of this doc ment, the fol owin definition a ply

1.5.1 Ge eral terms for monol thic microwa e inte rate circ its

microcirc it in whic a n mb r of circ it elements are in e ara ly as ociated an electrical y

intercon ected s c that f or the purp se of sp cification an testin an commerce an

maintenan e, it is con idered in ivisible

NOT 1 For this d f i itio , a circ it eleme t d e n t h v a e v lo e or e tern l c n e tio a d is n t

s e if i d or s ld a a s p rate item

NOT 2 Wh re n mis n ersta din is p s ible, th term "inte rate micro irc it" ma b a bre iate to

"inte rate circ it"

NOT 3 Furth r q alfyin terms ma b u e to d s rib th te h iq e u e in th ma ufa ture of a s e ific

inte rate micro irc it Ex mple to th u e of q alfyin terms: s mic n u tor mo olthic inte rate circ it;

s mic n u tor multi-c ip inte rate circ it; thin f ilm inte rate circ it; thic fim inte rate circ it; h brid inte rate

1.5.1.5

micro-a s mbly

microcirc it con istin of variou comp nents an /or integrated microcirc its whic are

con tru ted se arately an whic can b tested b f ore b in as embled an p c aged

NOT 1 For this d finitio , a c mp n nt h s e tern l c n e tio s a d p s ibly a e v lo e a wel a d it als

c n b s e ifie a d s ld a a s p rate item

NOT 2 Furth r q alfyin terms ma b u e to d s rib th form of th c mp n nts a d/or th a s mbly

te h iq e u e in th c n tru tio of a s e ific micr o-a s mbly Ex mple of u e of q alfyin terms:

s mic n u tor multi-c ip micro-a s mbly; dis rete c mp n nt micro-a s mbly

1.5.2 List of abbre iations

– BICMOS: Bip lar an Complementary Metal Oxide Si con

– Dye Penetrant (ZYGLO): Se l test

– ISO 9 0 : ISO International Qualty Rules

– MESFET: Metal Semicon u tor Field Ef fect Tran istor

– MMIC: Monol thic Microwave Integrated Circ its

– MODFET: Mod lation Do ed Field Eff ect Tran istor

– OS: Op ratin Sy tem

– POST CAP: In p ction after En a s lation

NOT P M a d PM h v th s me me nin ; h we er, P M is th term u e in th folowin s b la s s

1.5.3 Definition rele a t to the s ope of the TAS

Se QC 0 10 2-3, Clau e 6 for definition sp cific to Tec nolog Ap roval

2 Def inition of the component te hnology

2.1 Sco e

The Tec nolog Ap roval for the declared ran e or f ami y of comp nents s al in lu e their

desig an man facturin proces es an their interaces The overal management of these

interf aces by the Control Site s al b in lu ed These proces es an inter aces s al b

More detai ed req irements for the l sted proces es an interf aces to b in lu ed within the

Tec nolog Ap roval are given in the relevant clau es of this TAS The proces es are l sted

b low with the identification of the MAIN TECHNICAL PROCESS:

• Proces c aracterization

• Integrated circ it desig – This is a MAIN TECHNICAL PROCESS

2.2 De cription of a tivitie a d flow c arts

2.2.1 De cription of a tivitie

Al the activities (proces es) s al b identified with the relevant f low c arts in lu ed This

inf ormation may in lu e dif f erent proces es f or dif f erent typ s of comp nents but covered by

the same tec nolog Where a pl ca le, these s ould ad res al the proces es l sted in 2.1

The desig an man facturin c cle of integrated circ its may in olve one or more q al f ied

comp n or f aci ty han in dif f erent tas s within the “l f e c cle” of an MMIC

Desig , develo ment or sp cification of an MMIC is p rormed to the sp cif i req irements of

a c stomer, whic may b an external c stomer (s c as f or an a plcation-sp cific MMIC), or

an internal de artment

The prime contractor is that organization whic u dertakes the resp n ibi ty for the

management of al tas s prior to the s p ly of an MMIC to the sp cified req irements

2.2.2 Flow c arts

The f low c art in Fig re 1 is an example s owin s c o eration , where the sp cif i stages

are exp cted to b defined, referen in the relevant internal doc mentation

2.3 Te h ic l abstra t

2.3.1 TADD abstra t (not f or publ c tion)

The Tec nology Ap roval tec nical a stract s al b declared by the tec nolog a proval

declaration doc ment (TADD)

For e c tec nology declared the fol owin s al b identified:

• Des ription of desig to ls u ed e.g CAD s stems, sof tware;

• Des ription of wafer fa rication proces es in lu in f eature size, tec nolog , typ s an

n mb r of intercon ects

• Des ription/l st of prod cts an /or fami y of prod cts

– e.g low noise ampl f iers; p wer ampl fiers; switc es;

• Des ription of p c agin typ s/materials an ran e of pin ou ts

– e.g c ip form: ceramic, DIL 8, 16 pin;

• Des ription of test eq ipment, i.e typ of test eq ipment an s o e

An example of a Tec nolog Ap roval tec nical a stract is given in 2.3.3

2.3.2 QC 0 10 5 abstra t

The information to b publ s ed within QC 0 10 5:2 0 , Register of Firms, Prod cts an

Services a proved u der the IECQ-CECC Sy tem, in lu ing ISO 9 0 , may b b sed on the

inf ormation given to satisfy the Tec nolog Ap roval tec nical a stract of 2.3.1 Inf ormation

marked with an asteris ( *” may b omited in the publ s ed “Abstract of Tec nolog

Ap roval” if eq ested by Control Site

2.3.3 Ex mple of a Te hnology Approv l te hnic l abstra t

TECHNOLOGY DESCRIPTION: MONOLITHIC MICROWAVE INTEGRATED CICUIT

Ma uf acture [Co trol Site] N ame a d l oc tion

IEC Ref ere c : QC 210 21 – TAS for Mon l ithic Microwave Integrated Circuits

Certif ic te Numb r: Refere c of the l oc l SI

TADD Ge eric: Co trol Site’s Do ume t Refere c

(Cro s refere c s to ot her TADD s a ex ist in the Ge eric Sp cification

wh re a pl ica l e)

LIBRARY/DE IGN

Ma uf acturer’s n me of th lbrary:

Inf ormatio o th lbrary (wh re a plc ble):

Purp se: [ ] Microwa e Desig [ ] Digital Desig [ ] Oth rs

Ty es: [ ] Sta d rd Cels [ ] Eleme t Cel s

WAF R FABRICATION:

Waf er Fa ric tio Pro es Name: (e.g “AMES0.5” etc.)

Waf er Fa ric tio Pro es Ty e: (e.g FE T/Bipolar etc.)

Pro u tio Fami es: (e.g L w N oise/H igh PowerCo trol etc.)

Detais:

Ma imum Interc n e t L v ls:* (Triple/Doubl e/Singl e L vel/Metal etc.)*

Tra smis io l n stru ture: (e.g microstrip/c pla ar wa e uid etc.)

Metal Comp sitio s:* (Al / i/Al /Cu etc.)*

Pas iv tio Material:* ( ,2 µm Compre sive N it ride etc.)*

Su strate Material:* (e.g GaAs)*

Numb r of masks:* (e.g 8)*

ASS MBLY:

Pa k g ty es: (e.g Thin Pl astic Quad Fl at Pa k, 7 ,6 mm Sma Outl ine (SO) etc.)

Detais:

Ma imum Die Size: (e.g TPQF P – 9 x 9 mm: SO3 0 – 2,3 mm x 2,3 mm)

Pa k g materials: (e.g Ceramic/Epox y/P l astic etc.)

He d r/L a f rame:* (e.g Co p rAl l oy 42 etc.)*

Pin/L a Finish: (e.g Gol d/Sol der Dipp d et c.)

Die Ata hme t:* (e.g Sil ico -Gol d Eutectic etc.)*

Bo d Wire Ata hme t:* (e.g Aluminium, U l tra o ic etc.)*

ENVIRONMENTAL/RELIABILITY LIMIT :

En ura c Test Perf orma c : (e.g > x ye r at 5 °C or > 1 0 0 h at 12 °C)

Ac elerate Damp He t Se erity: (e.g > x ye r at 5 °C/6 % RH or 1 0 0 h at 8 °C/8 % RH)

Temp rature Cy ln Extremes: (e.g –6 °C / +15 °C)

2.4 Re uireme ts for control of s bcontra tors

Where a tec nical proces as def i ed in 2.1 is s bcontracted, the proced res an criteria

employed to demon trate control s al b sp cified This may b ac ieved either by the

demon tration of conf orman e to the req irements of the a pro riate PAS (Publ cly Avai a le

Sp cification) in the IECQ-CECC 2 0 0 series, or by demon tratin that the proces es have

b en satisf actori y p rormed in ac ordan e with criteria def i ed or ref eren ed f rom the TADD

Su h criteria s al b ca a le of demon tratin compl an e with the declaration of rel a i ty

an en ironmental p rf orman e

The fol owin items s al b sp cif ied:

• Re son for s bcontractin

• Inter elation hip doc mentation

NOT De ig , ma k ma uf acture, wafer fa ric tio , wafer pro e, a s mbly, te tin , p c a in a d s ip in ma

b s b o tra te pro id d th t th c ntrol site h s th c p bi ty for at le st o e of th MAIN T CH ICAL

PR CE S S a d fin d in 6.2.1.3 of QC 0 10 2-3

NOT This is a e ample of a p c a e d vic

Figure 1 – Ex mple flow c art of de ign/ma uf acture/te t

3 Component design of MMICs

3.1 Sco e

Desig information relevant to the tec nolog for whic a proval is sou ht s al b in lu ed in

the TADD

This s al in lu e desig of the semicon u tor proces in orp ratin modification an

publ cation of the proces p rameters an related proces desig rules in the f orm of writen

an computer f iles s ita le for u e in CAD to ls at either internal c stomers or in e en ent

desig centres

Proces c aracterization an circ it desig are, in general, se arate thou h inter related

tas s, an so their interaces with the proces desig tas s al b sp cified in detai, in lu in

management resp n ibi ties, tran f er sp cification , req irements an del vera les

The IC desig centre is resp n ible f or the desig of integrated circ its in ac ordan e with

c stomer requests as defined by prod ct or other sp cification , general y by tran lation fom

received data into IC sp cification , then desig an simulation phases f ol owed by

prod ction of data, sp cif i ation , an computer fi es (or eq ivalent req ired f or man

-f acturin This s al general y employ data fom the proces desig tas

Activities may in lu e mas makin an writin prod ct test programmes or test data s ita le

f or develo ment into test programmes by a test centre or tas

3.2 De cription of a tivitie a d flow c arts

3.2.1 De cription of a tivitie

The activities of desig for integrated circ its s al b declared, in lu in flow c arts s owin

al activities, critical ste s, c ec p ints an q al ty in icators, ref eren in the relevant

internal doc mentation These s al in lu e any or al of items a) to e) b low, as a pro riate:

a) Fe sibi ty

The avai a i ty of eq ipment an of the desig /man facturin ca acity to cover the

req ired prod ction lot q antities s al b verif ied

b) Proc s de ign

i) Ph sical c aracteristic (req ired f or circ it desig )

i ) Electrical c aracteristic

e) Conv rsion or a aptation of e istin de igns

An activities not so des rib d s al b stated with ref eren e to the relevant

doc mentation an interf ace controls The inf ormation to b lsted, where a pl ca le,

i ) CAD data an to ls f or e c typ of comp nent e.g hardware, software an cel

l braries general y p rt of the desig kit;

iv) verif i ation an valdation proced res;

v) p c age selection or desig proced res;

vi) test programmes (e.g test des ription lang age, test p rameters, etc.)

– man f acturin (mas man facture an /or f abrication),

– management of software config ration an l brary updates,

– upward comp tibi ty,

– doc mentation,

– trace bi ty,

– u age lmits (model, ac urac ),

– u age of verification to ls (DRC, ERC, LVS),

– as embly (in lu in p c age s p l ers),

– prototypin (if a pl ca le),

– c aracterization an test (in lu in eq ipment an sp cif i ation ),

– an other req irements

3.3.2 Cu tomer/u er

The desig centre defines its p l c related to the in olvement of the c stomer d rin the

variou desig ste s:

• Sp cif i ation

− writin the tec nical ne d sp cification

• Desig reviews

− f un tional simulation,

− test oriented simulation ,

− place an electromag etic simulation

• Prototypin (if a plca le)

− c aracterization an evaluation of prototyp s

The desig centre is resp n ible for the a pl cation of the desig an f abrication rules related

to the identified tec nolog It is also resp n ible f or the cor ect test methodology to f ulfi the

req irements of the tec nical ne d sp cif i ation

3.3.3 Interfa e with te t c ntre

An identification an des ription of the interf ace b twe n the desig centre (resp n ible for

the implementation of testa i ty in ide the circ it an test element group generation) an the

entity re l sin , control n an ru nin the tester an the test programme s al b made

A des ription s al b given of the methodolog con ernin :

– evaluation an tests on c aracterization of prototyp s (if a pl ca le);

– evaluation an tests on waf ers (pro in );

– evaluation an control of finis ed prod cts;

– evaluation an tests to in estigate f ai ures mec anisms

3.3.4 Ve dor sof tware c pabi ty

a) Sof tware tran p ren y/p rta i ty

This s bclau e outl nes the ste s to b taken to en ure that a piece of sof tware is

tran p rent an p rta le

b) Definition

Porta i ty

The software is a pl ca le to dif ferent proces es, e.g several MMIC proces es Porta i ty

can b to dif f erent levels, e.g a piece of software can b u ed

– f or 0,5 µm proces es only,

– or for al 0,2 µm an 0,5 µm proces es,

– or f or al MMIC proces es f rom a sp cific man facturer, etc

Tran p ren y

The degre to whic the sof tware han les the detai s of the c ip desig without detai ed

k owled e f rom the u er, e.g

– Software with lt le tran p ren y is that c r ently u ed f or ful c stom desig where the

sof tware is merely a to l f or layout simulation etc an the desig er makes al the

decision

This le d to several is ues to b ad res ed primari y by the software ven or To identify

the degre of tran p ren y/p rta i ty, at ention is p id to the f ol owin p ints:

i) If ven ors claim their software to b p rta le some sort of b n hmarkin mu t be

car ied out

i ) The q al fication level of p rson el u ed as MMIC desig ers wi vary ac ordin to

level of tran p ren y/p rta i ty, e.g they may b ed cated in, say, MMIC desig

tec niq es, but ne d no k owled e of a p rtic lar proces ; or, with a hig er level of

desig software, they ne d k ow nothin a out microwave elements at al

i )The config ration of the design on the computer also ne d to b tran p rent to the

u er, i.e the sof tware ven or s ould take resp n ibi ty f or the config ration control

iv)Software ven or sets up an fu d a s stem (e.g a u er group) to en ure that al u er

pro lems are identif ied an cor ected

v) A version of desig software may b c an ed p rt way throu h a desig , req irin the

tran fer of fi es or cels prod ced u in one version to another version In s c a case,

the desig er s al make a record of the fi e/cel name th s tran f er ed, givin the

name of the fi e ju t prior to tran fer, the name ju t af ter tran fer an the date of

tran f er This wi en ure trace bi ty in the case of er ors d e to sof tware bu s

a p arin at a later date

3.3.5 Subcontra tors, v ndors a d internal s ppl ers

Desig may b s bcontracted in ac ordan e with 2.4

3.4 Val dations a d control of the proc s e

3.4.2 Val dation of simulation re ults a ainst te h ic l ne ds spe if ic tion

The methodolog to cover the tec nical ne d sp cification s al b def i ed The fol owin

p ints s ould b covered:

– sta i ty in al f req en y ran e (with a large sig al simulation);

– sta i ty in al p wer s p l es f or pulsed o eratin con ition ;

– proces variation an sen itivity analy is;

– a pl cation of Monte Carlo method to yield f orecastin ;

– thermal analy is f or p wer devices;

– ef f ect of b n in – decoupln ca acitors - p c agin ;

– reverse model n (if a pl ca le)

3.4.3 La out v rific tion

L yout verification s al comprehen sp cific desig rules that are proces oriented an are

u ed f or one sp cific desig an an ad itional desig related inf ormation that is not defined

in the data s e t (if a pl ca le) s c as:

• Ge metric definition an ph sical l mits

• Electrical

− layout vers s s hematic,

− electromag etic simulation (in lu in proximity ef f ects b twe n microwave elements),

− reverse model n

• Rela i ty, in lu in electromigration/c r ent den ity an thermal con ideration

3.4.4 Val dation proc dure

The proced re for val dation an control of the desig s al b defined

Where a pl ca le, an inf ormation req ired f rom proces in or testin d rin the desig

val dation stage s al b identified when it is req ired to avoid pro lems d rin prod ction

proces in or testin , or whic may aff ect rel a i ty

Before in orp ration into the desig s stem, an new software s al b c ec ed an valdated

Proced res s al b identified whic cover:

– testa i ty;

– desig rules to minimize f ai ure mec anisms (electromigration, ESD);

– adeq ac of test programmes;

– adeq ac of test evaluation

4 Mask manuf acture

4.1 Sco e

This clau e def i es the req irements for the man facture of mas s u ed to define circ it

elements d rin waf er fa rication an gives req irements f or the val dation of proces es an

s bcontractors

4.2 De cription of a tivitie a d flow c arts

Mas man facture may b solely owned by the MMIC wafer f abrication comp n or by an

in e en ent comp n In either case the activity req irements, control, proces c ec p ints

an q al ty in icators s al b tre ted identical y

The req irements for the mas man facturer s al b declared, s owin management an

control of hardware/software

Typical y this would in lu e:

– desig rules;

– CAD data an rules;

– identification proced res

4.3 Val dation a d control of the proc s e

The method of control an val dation of f i is ed mas s or their man f acturin proces es s al

b def i ed to en ure that the f i is ed mas s comply with the original desig an proc rement

req irements:

– name an ad res ;

– pro f of a proval of the mas man f acturin proces f or the certified wafer fa proces ;

– name of the TRB contact within the mas man facturer;

– identification of the proces sp cification of the mas man facturer;

– a s mmary of the inter ace b twe n the desig centre an the mas man facturer, l stin

doc ments, to ls etc del vered by the desig centre, the methodolog u ed to val date the

work done by the mas man f acturer an the resp n ibi ties of e c p rty

4.4 Subcontra tors, v n ors a d internal s p l ers

Mas man f acture may b s bcontracted in ac ordan e with 2.4

5 Waf er f abric tion of MMICs

5.1 Sco e

This clau e des rib s the activities, eq ipment an re-work rules f or the waf er f abrication of

monol thic microwave integrated circ its an gives req irements for the val dation an control

of proces es an s bcontractors

The wafer f abrication activities in lu e the ph sical re l zation of monol thic microwave

integrated circ its on semicon u tor s bstrates by me n of the neces ary to ls, method ,

o eration an their management, p rormed in-hou e by a q alfied tas of f aci ty or by a

se arate q al fied fou dry

The waf er fa rication faci ty may either

a) receive an employ s ita le mas s an /or CAD data fom a q alfied tas or faci ty, or

b) receive the data f om the desig tas an employ an internal or external mas maker

For either case, it is resp n ible for the management of the interaces, the proces materials

an eq ipment an the del very of wafers to its c stomers

Waf er f abrication inf ormation relevant to the tec nolog for whic a proval is sou ht s al b

in lu ed in the TADD

5.2 De cription of a tivitie a d flow c arts

5.2.1 Ge eral re uireme ts

The critical o eration to b monitored s al b determined b sed on exp rien e an

k owled e of the proces The data comin f rom the proces l ne s al b analy ed u in

ac e ted SPC method to determine their ef f ectivenes in control n the proces If the

ef fectivenes of the critical o eration is f ou d not to adeq ate, it is neces ary to c an e the

me s rement con ition or to ac uire another data A waf er f abrication monitorin s stem may

u e variou test stru tures, me s rement method an tec niq es

A TQM (Total Qual ty Management methodolog s al b employed in whic the waf er

f abrication centre is resp n ible for its own qual ty, has set up the organization an resources

to manage it (in lu in TRB) an is a le to re ort its ef f ectivenes to the Sup rvisin

In p ctorate (SI) (either directly or via the Control Site)

5.2.2 De cription of a tivitie a d flow c arts

The activities of wafer f abrication for monol thic microwave integrated circ its s al b

declared, in lu in flow c arts s owin al activities, critical proces ste s, p rameters,

proces c ec p ints an q al ty in icators, u ed f or the val dation an control of the proces

an s bcontractors The major criteria u ed to des rib the tec nolog s al b identified

Examples of critical o eration in lu e:

En ironment

Wafer materials prep ration

– in omin ac e tan e/QC;

– s bstrate (f ront side, b c -side, size, orientation);

– e itaxial wafer (material, do ant, VPE, MBE, MOCVD)

Wafer proces in tec niq es (e c layer)

Proces monitors an ac e tan e

Doc mentation s al b referen ed to define or control the main pro erties of the tec nolog ,

i.e

– f abrication location;

– b sic tec nolog (MESFET, HEMT, MODFET, HBT, etc.);

– mono or multi level intercon ection;

– isolation method (mesa etc in , ion implantation, etc.);

– nature of the gate (Al, WSi, WN, Ti, etc.);

– nature of the dielectric (SiO, SiN, etc.);

– nature of the bip lar emiter (wal ed, nonwal ed);

– new man facturin tec niq es;

The control of these proces es s al f oc s up n those p rameters, whic are critical for the

q al ty as uran e of the prod cts in term of p rf orman e, yield an re rod cibi ty (ca a i ty),

an rel a i ty For example, the f ol owin s al b detai ed:

– Bre k own voltage

– Thres old voltage

Example of a typical f low c art: se Fig re 3

5.2.3 Qu ntitativ phy ic l a d ele tric l l mits

The c aracteristic l mits u ed in e c ste of the flow c art s al b defined for the

prod ction proces an clas ified when neces ary as

– original – where the proces es are not yet u ed to make prod cts u der as es ed q al ty;

– distin uis ed – where the proces es are alre d u ed to prod ce q alfied prod cts with

lower p rf ormin or con trainin l mits

5.3 Eq ipme t

The eq ipment for the man facturin of the stan ard evaluation comp nent the tec nolog

c aracterization vehicle the p rametric monitor an the finis ed prod cts s al b sp cif ied

in lu in a des ription of the fol owin c aracteristic p rameters:

– General c aracteristic (man f acturer, date of man facturin , inten ed purp se)

– Fu ctional req irements (electrical p wer con umption, co l n req irements, he tin

req irements, en ironmental req irements)

– In tal ation proced re (p rts des ription, mou tin des ription, intercon ection s heme

des ription)

– Commis ionin into o eration

– Sp cif i ation for req ired material

– Rel a i ty (minimum-typical-maximum values, deratin exp cted lfetime, MTBF)

Maintenan e programmes f or the eq ipment s al b defined (in lu in detai ed, in tru tion

on maintenan e proced res, lst of tools req ired f or maintenan e, p riodicity of maintenan e)

The whole, or es ential p rts, of the eq ipment s al b cal brated p riodical y in order to

maintain ac urac The cal bration s stem an the a pl ed cal bration method s al b

defined, in lu in :

– f ormal cal bration proced re;

– s ort cal bration proced re to monitorin eq ipment;

– cal bration resp n ibi ty;

– cal bration req irements (l st of cal bration to ls, eq ipment, meters an gau es);

– cal bration p riodicity

5.4 Materials

Control an val dation of materials u ed for fa rication of waf ers s al b def i ed, in lu in :

– f olow-up, s p l er’s q otes, multiple sourcin p l c ;

– materials in p ction (method , to ls, res lts analy is an u e);

– materials management an stoc s (store, trace bi ty, lmited l fe time prod cts)

5.5 Re-work

Re-work s al only b al owed where it can b demon trated that it do s not influen e the

q al ty an rel a i ty of the prod ct The doc mentation s al sp cify al p rmited rework

proces es/stages together with the criteria f or their u e, p rf orman e and satisf actory

completion

No rework may b p r ormed prior to its a proval as a p rmit ed rework o eration The

re son for the rework s al b recorded in the lot history, together with al the detais of the

rework p r ormed, the res lts of the rework an the con eq en es of the rework on further

man facturin stages The criteria for p rmit in rework s al b ful y doc mented in the

TADD

Re air is not al owed in the wafer f abrication proces For wafer fa rication, re air is

redef i ed as “An o eration whic is p rormed to cor ect non onf orman e or er or an whic

res lts in the finis ed wafer havin an fe ture, c aracteristic, or material whic is dif ferent to

that of a wafer man factured to the sp cified a proved proces ”

5.6 Val dation methods a d control of the proc s e

The proced res u ed for val dation an control of the proces es s al b declared Proced re

f or control n an val datin proces es u in statistical method b sed on exp rimental data

an k owled e of the proces es s al b declared

The direct resp n ibi ty of the TRB in the control of q al ty al ows control of on oin minor

c an es of tec niq es an tec nologies for as embly an p c agin without req irin

recertification In the wafer fa rication centre, the TRB is either comp sed of the p rson el

managin its activities or they are re resented in a TRB at a hig er level

5.6.1 Ac epta c pla f or wafer

The TRB s al cre te an demon trate the eff ectivenes of a plan b sed on electrical

me s rements of PCM If a pl ca le, vis al criteria s al also b u ed This plan may b a

waf er by-wafer or lot-by-lot ac e tan e plan, but s al cor esp n to the prod ction groupin

of variou typ s of lots:

– smal lots;

– large lots;

– sp cial lots

PCM data s al b recorded an avai a le d rin au its

5.6.2 SPC/Statistic l proc s control programme, ap l c bi ity

A wafer fa rication data analy is s stem s al b u ed by the man facturer to monitor

proces critical p ints and manage yield an rel a i ty This s stem s al b contained within

the overal q al fy plan des rib d within the TADD The monitorin s stem may u e variou

test stru tures, me s rement method an tec niq es The critical o eration to b

monitored are determined by the man facturer on the b sis of its exp rien e an k owled e

of its proces The data comin f rom the proces l ne are analy ed ac ordin to s ita le SPC

method to determine their eff ectivenes in control n the proces es

[SPC g idan e is given in CECC 0 016: Basic req irements for the u e of Statistical Proces

Control (SPC) in the CECC Sy tem, avai a le f om the IECQ-CECC Secretariat

5.6.3 Proc s capabi ty d monstration (i e statistic l c pabi ity)

Durin the certification phase, the man f acturer s al prod ce circ its, ru test an

b n hmark in order to demon trate its a i ty to evaluate the proces ca a i ty in terms of

q al ty, rel a i ty an efective ca a i ty to ru prod ction Summaries of these tests are

s bmit ed to the SI d rin the valdation au it These tests are car ied out in order to

esta l s a contin ou ca a i ty monitorin a art fom the initial demon tration The TRB

determines when these tests s al b done after the initial certification

5.6.4 Te hnolog v l d tion

The tec nology flow c art of the proces , whic is des rib d in 5.2.2, is au ited as a whole to

verify conf orman e Critical o eration in 5.2.2 s ould b des rib d in this f low c art For an

example of a typical flow c art, se Fig re 3

[Critical p ints are given in the g idan e doc ment CECC 0 8 9: Question aire for au itin

IC an ASIC man f acturin l nes, avai a le f om the IECQ-CECC Secretariat, whic may b

u ed as a g ide f or the tec nical val dation au it

5.6.5 Te t v hicle

The wafer fa rication proces is monitored an controled by a stan ard evaluation circ it

(SEC), a tec nology c aracterization vehicle (TCV) an a proces control monitor (PCM) The

f abrication f low c art le din to f i is ed prod cts s al b esta l s ed with cle r l mits for

e c f abrication ste These l mits s al b sp cified

Wafer f abrication may b s bcontracted in ac ordan e with 2.4

Subcontractor ar an ements f or the initial desig phase s al b defined to cover the f olowin

to ic :

– desig reviews;

– avai a i ty of proces desig rules in lu in p rmis ible varia le of the ph sical an

electrical c aracteristic ;

– notif i ation of proces c an es that could af f ect desig , ph sical an electrical

c aracteristic an p rf orman e;

– desig an ac e ta i ty of PCMs an SECs;

– the man ers in the circ its have to b del vered for the prototypin phase, an then for f ul

prod ction (if a plca le);

– where a pl ca le, a l st of doc ments an to ls to b tran fer ed to the wafer fa ricator,

an the l st of fol ow-up, control an test doc ments that s al b del vered with the

circ its an alow trace bi ty

In-ln insp ctio ac cordin to

ma ufa turin inst ruc t io s

S C c ont rol o crit ic l proc es

p ramet ers, a c ordin t o a d fin d

c nt rol pla

In-ln insp ctio ac cordin to

ma ufa turin inst ruc t io s

Ele t ric al pre-t est a c ordin t o t ype

sp cific tio

In-ln insp ctio ac cordin to

ma ufa turin inst ruc t io s

Acc pt an e v erific at io a c rdin to

q alt y sp cific at io

In-ln insp ctio ac cordin to

ma ufa turin inst ruc t io s

A cc ordin t o st ore pro e ure of

difuse wafers

IE C 8 8/0

6 Waf er probing of MMICs

6.1 Sco e

Wafer pro in management an control formation relevant to the tec nolog for whic

a proval is sou ht s al b declared

6.2 De cription of a tivitie a d flow c arts

The activities of pro in of integrated circ its, s owin q al ty in icators, s al b declared

Examples of s c activities in lu e:

– atmospheric an cle nl nes control;

– was in an wafer control;

– control an pre aration of pro e card

For examples of a typical f low c art, se Fig re 4

6.3 Eq ipme t

Information on the test eq ipment u ed, an the inten ed ran e s al b provided

Maintenan e an cal bration programmes f or the eq ipment s al b in lu ed The information

s ould cover:

– test eq ipment verification;

– device complexity (analog e, digital an mixed);

– typ s of me s rements (DC, RF, d namic, static, p rametric);

– temp rature test eq ipment (e.g hot c u k);

– registration an control of typ sp cific j g , to ls an fixtures

6.4 Te t proc dure

The req irements f or detai n proced res f or the han l n , control an u e of test

programmes s al b declared, in lu in an relevant inf ormation not previou ly provided (i.e

val dation an compl an e proced res)

– c aracterization an test (in lu in eq ipment an sp cification );

– an other req irements

6.5.2 Subcontra ting