IEC 60721-3-3 1994 Classification of environmental conditions - Part 3: Classification of groups of environmental parameters and their severities - Section 3: Stationary use at weatherpr
General
General letter symbols are defined in Clause 4 of IEC 60747-1:2006.
Additional subscripts/symbols
p = parasitic t = terminal isol = isolation m = mount
List letter symbols
Voltages and currents
Peak case non-rupture current (for diode and thyristor devices) I RSMC
Peak case non-rupture current (for IGBT and MOSFET devices) I CNR
Mechanical symbols
Mounting torque for screws to heat sink M s
Mounting torque for terminal screws M t
Maximum acceleration in all 3 axis (x, y, z) a
Flatness of the case (base-plate) e c
Flatness of the cooling surface (heat sink) e s
Roughness of the case (base plate) R Zc
Roughness of the cooling surface (heat sink) R Zs
Thickness of thermal interface material (case - sink) d (c-s)
Other symbols
Total maximum power dissipation per switch at T c = 25 °C P tot
Parasitic inductance, effective between terminals and chips (to be specified) L p
Parasitic capacitance between terminals and cooling surface (case, base plate, ground)
Lead resistance between terminal x and related switch x’ r xx ’
Number of power load cycles until failure of a percentage p of a population of devices
5 Essential ratings (limiting values) and characteristics
General
Isolated power semiconductor devices must be classified as either case rated or heat-sink rated Their ratings and characteristics should be provided at a standard temperature of 25 °C or another designated elevated temperature For specifications regarding multiple devices with a shared encapsulation, refer to section 5.12 of IEC 60747-1:2006.
Ratings (limiting values)
Isolation voltage (V isol )
The maximum root mean square (r.m.s.) or direct current (d.c.) value between the main terminals and high voltage control terminals on one side, and the low voltage control terminals (when applicable) and the base plate on the opposite side, must be maintained for a specified duration.
Peak case non-rupture current (I RSMC or I CNR ) (where appropriate)
Maximum value for each main terminal that does not cause the bursting of the case or emission of plasma and particles
Terminal current (I tRMS ) (where appropriate),
Maximum r m s value of the current through the main terminal under specified conditions at minimum mounting torque M t and maximum allowed terminal temperature (T tmax = T stg or
Total power dissipation (P tot )
Maximum value per switch at T c = 25 °C (or T s = 25 °C), when T vj = T vjmax , at d.c load.
Temperatures
Maximum solder temperature T sold during solder process over a specified solder processing time t sold
Minimum and maximum storage temperature
Mechanical ratings
5.2.6.1 Mounting torque of screws to heat sink ( M s )
Minimum mounting torque that shall be applied to the fixing screws to the heat sink
5.2.6.2 Mounting torque of screws to terminals ( M t )
Minimum mounting torque that shall be applied to screwed terminals
Minimum mounting force for pressure mounted devices, fixed by clips, that shall be applied to the isolated pressure contact device
Maximum value along each axis (x, y, z)
5.2.6.6 Flatness of the heatsink surface ( e S ) (where appropriate)
Maximum deviation from flatness for the heatsink surface over the whole mounting area
5.2.6.7 Roughness of the heatsink surface ( R ZS ) (where appropriate)
Maximum roughness of the heatsink surface over the whole mounting area
Climatic ratings (where appropriate)
Limiting values of environmental parameters for the final application as follows
– speed and pressure of air
– irradiation by sun and other heat sources
– biological issues shall be described in classes as specified in IEC 60721-3-3:1994, Table 1.
Characteristics
Mechanical characteristics
Minimum value of distance along surface of the insulating material of the device between terminals of different potential and to base plate
NOTE 1 IEC 60112 (details to comparative tracking index “CTI”) and IEC 60664-1:2007 Subclause 5.2 apply
NOTE 2 Air gaps between plastic surface and grounded metal or between terminals of opposite polarity smaller than 1,0 mm (for pollution degree 2), or 1,5 mm (pollution degree 3) shorten the countable creepage distance considerably (details see 60664-1:2007, examples) This is essential, if dust, moisture or dirt starts to cover the surface and increases the leakage current over surface, which might start burning the plastic encapsulation material
Minimum value of distance through air between terminals of different potential of the isolated device and to base plate
NOTE For details, see IEC 60664-1:2007, (Subclause 4.6 and Subclause 5.1) which shows typical examples of various shapes of clearance distances
Maximum value excluding accessories (mounting hardware)
5.3.1.4 Flatness of the base plate ( e C ) (where appropriate)
Maximum and minimum allowed deviation from flatness for the base plate and its direction (convex or concave).
Parasitic inductance (L p )
Maximum or typical value between the main terminals of each main current path.
Parasitic capacitances (C p )
Maximum value of parasitic capacitance between the specified main terminal(s) and the cooling surface.
Partial discharge inception voltage (V iM or V i(RMS) ) (where appropriate)
Minimum peak value V iM or r.m.s value V i(RMS) between the isolated terminals and the base plate (details, see IEC 60270).
Partial discharge extinction voltage (V eM or V e(RMS) ) (where appropriate)
Minimum peak value V eM or r.m.s value V e(RMS) between the isolated terminals and the base plate (for details, see IEC 60270).
Thermal resistances
5.3.6.1 Thermal resistance junction to case for case rated devices ( R th(j-c)X )
Maximum value of thermal resistance junction to a specified reference point at the case (base plate) per switch “X” (for example of the diode (D), thyristor (T), IGBT (I) or MOSFET (M)).
5.3.6.2 Thermal resistance case to heat sink ( R th(c-s) ) (where appropriate)
The maximum thermal resistance value between the case and the heat sink of a rated device, known as a "module," is determined when the case is installed following the manufacturer's mounting guidelines.
5.3.6.3 Thermal resistance case to heat sink per switch ( R th(c-s)X ) (where appropriate)
The maximum thermal resistance value between the case and the heat sink of switch "X" (such as diode (D), thyristor (T), IGBT (I), or MOSFET (M)) is specified for isolated case-rated devices ("modules") This value is applicable when the case is installed following the manufacturer's mounting guidelines.
5.3.6.4 Thermal resistance junction to heat sink for heat sink rated devices ( R th(j-s)X )
The maximum or typical thermal resistance from the junction to a specified point at the heat sink for switch "X" (such as a diode, thyristor, IGBT, or MOSFET) is determined when the device is installed following the manufacturer's mounting guidelines.
5.3.6.5 Thermal resistance junction to sensor ( R th(j-r)) (where appropriate)
Value of thermal resistance junction to an integrated temperature sensor, when the device is mounted according to the manufacturer’s mounting instructions.
NOTE The position of this thermal resistance should be shown in the thermal resistance equivalent circuit.
Transient thermal impedance (Z th )
Thermal impedance varies with the time elapsed following a step change in power dissipation, as outlined in Subclause 5.3.6 This relationship can be specified in several ways.
Verification of isolation voltage rating between terminals and base plate (V isol )
Proof of the ability of the isolated power device to withstand the rated isolation voltage
Figure 1 – Basic circuit diagram for isolation breakdown withstand voltage test (“high pot test”) with V isol
G = voltage source with high impedance, capable to supply V isol
A = ammeter or current probe for I isol
The voltage source G provides the isolation voltage \$V_{isol}\$ as either alternating current (a.c.) or direct current (d.c.), featuring a high internal impedance to minimize the risk of breakthrough current during a breakdown of the device under test (DUT).
All primary and high voltage control terminals are interconnected and linked to the high potential output terminal H of the voltage source G The base plate of the Device Under Test (DUT), along with its metallized cooling surface and all low voltage terminals, is grounded at potential E An ammeter or current probe A is utilized to measure the isolation leakage current.
When Switch S is closed, the voltage is gradually increased to the designated level and held steady for a predetermined duration It is crucial that the current displayed on ammeter A does not surpass the specified limit Following this, the voltage is decreased to zero.
Specified in IEC 60664-1:2007 ã Ambient or case temperature ã V isol ã I isol as maximum test limit ã Test time t, if less than 60 s
Methods of measurement
Partial discharge inception and extinction voltages (V i ) (V e )
Between high potential terminals and base plate (where appropriate) See IEC 60270 and IEC 60664-1:2007.
Parasitic inductance (L p )
To measure the parasitic inductance between two main terminals
Figure 2 – Circuit diagram for measurement of parasitic inductances ( L p )
DUT = device under test T1+T2, for example IGBT (Single or Dual – shown – or branch of a three phas e arrangement), fast diode or MOSFET device
C = main capacitor bank as reservoir
L L = load inductance, at least 100 times the parasitic inductance
L p1 … L pn = portions of parasitic inductance L p
G = voltage s ource to charge the c apacitor
T 1 = DUT, top switch (shown as IGBT in Figure 2)
T 2 = DUT, bottom switch (shown as IGBT in Figure 2), optional
T 3 = auxiliary IGBT switch i DUT di DUT /dt
The circuit depicted in Figure 2 features a DC supply G for charging reservoir C, along with an auxiliary switch T 3 and a gate drive unit for T 3 The device under test (DUT) is integrated into the test setup with its gate control terminals shorted A dual-channel oscilloscope measures the voltage V CE between the main terminals "C 1" and "E 2," while a current probe detects the current I DUT flowing through the diode path of the DUT, both connected to the oscilloscope This measurement technique employs a reduced voltage V CC and the di/dt of the diodes during switch-off, allowing for voltage sensing at the external main terminals It is applicable for both single switch devices and half-bridge circuit devices (DUAL modules).
The pulsed current method employs auxiliary transistor T3 to control the load current to inductor LL by switching it on and off When T3 is off, the current circulates through the diodes of the device under test (DUT) Upon T3's activation, the current through the diodes decreases at an almost linear rate, represented as di DUT/dt This interval (t1 – t2) results in a voltage step, V step, across the DUT due to the internal parasitic inductance during the current decline The parasitic inductance of the main current path can be calculated from this behavior.
NOTE Use low inductance (sheeted) bus baring and low inductance current probe.
Parasitic capacitance terminal to case (C p )
To measure the parasitic capacitance C p between specified main terminal(s) and the case (base plate)
Figure 4 – Circuit diagram for measurement of parasitic capacitance ( C p )
To measure the capacitance, first mount the device to a grounded heat sink following the manufacturer's instructions Connect the current source connector "I1" of the capacitance meter to the specified terminal and "I2" to the ground (base plate) of the device under test (DUT) Next, attach the voltage sensing connector of the capacitance meter to test points "V1" and "V2," ensuring it is grounded Set the capacitance meter (CM) to the specified frequency, and the capacitance \( C_p \) can then be read from the CM For measuring the total coupling capacitance \( C_p \), connect all main terminals together and follow the same measurement procedure.
– Specified conditions ã Measurement frequency f of the CM
Thermal characteristics
6.2.4.1 General description of measuring methods
To measure thermal characteristics between the switch and the cooling system
– Reference points for temperature measurement and description
The measurement of thermal resistance and impedance for isolated devices should follow the same methods as those used for non-isolated devices This process is detailed in the relevant standards for diodes (IEC 60747-2), thyristors (IEC 60747-6), bipolar transistors (IEC 60747-7), FETs (IEC 60747-8), and IGBTs (IEC 60747-9).
Thermal interface material Isolation layer
T j1…n = junction temperature of chip 1 to n
T c1…n = case temperature under chip 1 to n
T s1 n = heatsink temperature under chip 1 to n
T sX = heatsink temperature at a specified surface point
Figure 5 – Cross-section of an isolated power device with reference points for temperature measurement of T c and T s
T_c is measured using a temperature measuring instrument from below through a small hole in the heat sink and any thermal interface material beneath the switch (chip) T_s is recorded from the hottest accessible point above the switch (chip) or from below through a specified sack hole that ends 2 (+/-1) mm below the heat sink surface, as defined in the type test feature T_j is determined using indirect methods outlined in the relevant documentation.
The thermal resistance R th(j-s) and R th(c-s) is influenced by various mechanical factors, including the type and thickness of the thermal interface material, which should be detailed in the manufacturer's mounting instructions (typically ranging from 30 to 50 mm) Additionally, the maximum flatness deviation of both the device's base plate and the heat sink, along with the mounting torque of the fixing screws, must adhere to the specified mounting guidelines.
6.2.4.2 Thermal resistance junction to case per switch R th(j-c)
T j is the virtual junction temperature of the switch;
T c is the temperature of the case (base plate) under the switch (chip);
P is the power dissipation of a switch (see Figure 5)
6.2.4.3 Thermal resistance case to heat sink per switch (X) R th(c-s)X or per device
X is the D (Diode), I (IGBT); M (MOSFET)
T c is the temperature taken at the specified point of the case (as above) under the chip
T s is the temperature of the heat sink, taken at the reference point for testing T s specified
PX is the complete power dissipation of the switch
P is the power dissipation of the complete device
– Specified conditions ã Mounting according manufacturer’s instructions ã Thermal conductivity of the thermal interface material ã Reference points for thermal measurement
NOTE See Annex B for Measuring method of the thickness of thermal interface material
6.2.4.4 Thermal resistance junction to heat sink per switch R th(j-s) (for heat sink rated devices)
T j is the virtual junction temperature of the switch;
T sn is taken at the specified reference point n at the heatsink (see Figure 5);
P is the power dissipation of the switch
– Specified conditions ã Mounting according manufacturer’s instructions ã Thermal conductivity of the thermal interface material ã Reference points for thermal measurement
These are based on former Subclause 6.2.4.2 to 6.2.4.4 Individual documents of the non- insulated devices apply
Z th(j-s) = (|T j (0)- T s (0)| - |T j (t)- T s (t)|)/P (7) – Specified conditions ã Mounting according manufacturer’s instructions ã Thermal conductivity of the thermal interface material ã Reference points for thermal measurement
General requirements
In addition to the following subclauses, the requirements applicable to the non-isolated devices as given in the other relevant parts of IEC 60747 apply.
List of endurance tests
Subclause Environmental Testing – designation Short form Normative references
7.2.1 High temperature revers e bias or high temperature blocking HTRB IEC 60749-5
7.2.2 High humidity and high temperature reverse bias or high humidity and high temperature blocking H 3 TRB IEC 60749-5
7.2.3 Power cycling (load) capability IEC 60749-34
7.2.4 High temperature storage HTS IEC 60749-6
7.2.5 Low temperature storage LTS IEC 60068-2-481
7.2.7 Resistance to solder heat IEC 60749-15
Acceptance defining criteria
Table 2 – Acceptance defining characteristics for endurance and reliability tests
Type tests and routine tests
Type tests
When determining mandatory tests for isolated power semiconductor devices, it is essential to take into account the experience gained from similar components, including switches and packages.
Type tests are conducted on new products using a sample approach to establish their electrical, thermal, mechanical, and climatic ratings, which are essential for the data sheet These tests help define the limits for future routine assessments Additionally, periodic retesting of samples from ongoing production or deliveries is necessary to ensure that the product quality consistently meets established standards.
The minimum type tests to be carried out are as follows:
New isolated power semiconductor devices should undergo the type tests listed in Table 3, marked with “X” (X = mandatory) Some of the type tests are destructive
Table 3 – Minimum type and routine tests for isolated power semiconductor devices
Subclause Type test Routine test Destructive
Isolation voltage test V is ol
Peak case non-rupture current I RSMC ; I CNR
5.2.6.4 outline dimensions, creepage, clearance flatness of base-plate or of cooling surface thermal resistances R th transient thermal impedance Z th parasitic inductance L p parasitic capacitance C p partial discharge voltages terminal pull out forc e
5.2.7 thermal cycling power cycling (load) mechanical tests climatic characteristics classification
Tests for isolation voltage, partial discharge voltage, creepage, and clearance distance must adhere to the relevant standards applicable to any final equipment utilizing isolated power semiconductor devices, such as IEC 60950 for safety in information technology and IEC 61287 for rolling stock Type tests are required only for devices with specified maximum values, while routine tests apply to devices with specified maximum or minimum values Refer to Table 1 for normative references regarding these tests.
Routine tests
The routine tests should be carried out on the current production or deliveries normally on a
The ratings and characteristics outlined in the data sheet must be verified for each criterion or specimen Routine tests may involve grouping isolated devices as specified in Table 3, which lists the minimum routine tests required Additional routine tests are conducted according to other sections of IEC 60747 relevant to the specific switch.
Test method of peak case non-rupture current 2
The isolated power device, which includes bipolar transistors, IGBTs, or MOSFETs as switches, is tested to demonstrate its capability to endure the rated peak case non-rupture current (I CNR) without resulting in case rupture, plasma beam emission, or the ejection of large particles This process is classified as a destructive test.
NOTE 1 Case rupture is caused by inside arc or vapour pressure, when the supplied energy or current from outer source exceeds the specified limit The arc or vapour pressure is induced in a package (encapsulation) of failed power devices by being supplied with stored energy or current from an outer circuit power source Critical current or energy for packages after the device failure should be issued as an item of the package environmental properties, and in addition the semiconductor and also other electrical parts should avoid an explosion by accident
Figure A.1 – Circuit diagram for test of peak case non-rupture current I CNR
A = Ammeter to measure the device current which can be I CNR , if the case just did not burst, monitored by a current probe having low inductance
C = line capacitor bank, chargeable to full voltage
D 1 = inverse diode of T 1 , high side
D 2 = inverse diode of T 2 , low side
G 1 = DC supply voltage source V CC , which can be switched off from mains under all conditions
GU1 = gate drive unit of T 1
GU2 = gate drive unit of T 2
L s = parasitic inductance of the circuit (40 nH to 250 nH )
R c = discharge resistor for protection purposes
R s = fuse resistor, mostly set to zero
S 1 = auxiliary switch (IGBT), high side
S 2 = auxiliary switch (IGBT), low side
T 1 = high side IGBT switch = device under test (DUT)
The system features a two-quadrant converter equipped with two identical isolated IGBT devices Auxiliary switches, S1 and S2, which can also be IGBT devices, are utilized to control the load current and simulate a short circuit failure Additionally, T1 and T2 are identical isolated IGBT devices, functioning either as a single switch or in a half-bridge configuration as dual switches.
First, close switch S 2 , turn on T 1 , the load current increases as defined by load inductance
When the load current exceeds the safe operating area (SOA) for turning off transistor T1, an attempt is made to turn it off Initially, the turn-off process reduces the current in T1, with some of it being redirected to diode D2 However, T1 experiences a turn-off failure, causing D2 to carry a significant amount of current at that moment This failure results in D2 being forced to turn off at an extremely high di/dt, which exceeds its SOA, leading to its failure as well.
When T1 is activated and reaches a significant load current, T2 is subsequently turned on, leading to its failure due to exposure to full voltage and current This results in T1 entering desaturation and also failing, causing a top-bottom shoot-through that creates a short circuit between the positive and negative bus bars This discharges the capacitor bank and generates an arc in the devices, producing gases from the surrounding plastic gel until the capacitor bank's energy is depleted Such failures can occur naturally due to cosmic rays or thermal overload, but can also be artificially induced by manipulating the device.
The tests are conducted until a stored energy value in the capacitor bank and peak current are identified that do not exceed the limits necessary to damage the case Key parameters such as peak current (\$I_C = I_{CNR}\$), voltage (\$V_{CC}\$), maximum capacitance (\$C_{max}\$), and energy (\$E_C = \frac{1}{2} C V_{CC}^2\$) are closely monitored throughout the process.
The CNR (Case Non-Rupture) is defined as the percentage value, such as 10% equating to 2 out of 20 tested devices, indicating that the case did not burst or split while preventing the ejection of internal particles This measurement is based on a minimum sample size of 10 devices and is crucial for post-test evaluations and criteria.
The DUT undergoes a visual inspection to check for visible cracks and signs of plasma resulting from internal arcing It is essential that there are no indications of particles being expelled, nor any evidence of external melting or combustion.
NOTE 2 The ejection of particles is unavoidable for energies higher than about 10 kJ W hat can be achieved by good design is that no massive parts are ejected, which can cause severe consequential damage
The specified conditions for the analysis include the case or virtual junction temperature, with values set at T_c = 25 °C and T_vj = 25 °C or 125 °C Key parameters also encompass the supply voltage (V_CC), the capacitance of the capacitor bank (C), and the stored energy within the capacitor bank (E_C) Additionally, the parasitic inductance during a short circuit (L_SC) and the load current (I_L) are critical factors The gate voltage during the on and off states (V_GEon and V_GEoff), along with the gate resistance in both states (R_Gon and R_Goff), are also essential Finally, the percentage of tested devices that did not burst compared to the total number of tested devices is a significant metric for evaluation.
NOTE 3 Lit.: S Gekenides, et al.: Explosion Tests on IGBT High voltage Modules, ISPSD ’99 Toronto
Measuring method of the thickness of thermal compound paste
The measuring gauge is a tool made from stainless steel or a suitable plastic that is resistant to the fluid material being tested It features outer teeth that create a baseline, while the inner teeth are progressively shortened to establish varying distances from this baseline These distances can be easily read on a scale marked on the instrument A typical example of this measuring gauge is illustrated in Figure B.1.
Figure B.1 – Example of a measuring gauge for a layer of thermal compound paste of a thickness between 5 mm and 150 mm Measuring method
After applying the layer, press the measuring comb onto the substrate with the teeth positioned vertically to prevent slipping Remove the comb and identify the shortest tooth that still contacts the fluid layer The layer's thickness is determined by the average of the last touching tooth and the first non-touching tooth To obtain representative values for the covered area, perform at least two additional measurements at different locations on the surface using the same method.
IEC 60112, Method for the determination of the proof and the comparative tracking indices of solid insulating materials
IEC 61287-1:2005, Railway applications – Power converters installed on board rolling stock – Part 1: Characteristics and test methods
Lit.: S Gekenides, et al.: Explosion Tests on IGBT High voltage Modules, ISPSD ’99 Toronto