Bsi bs en 16602 70 12 2016

145 Annex C informat ive Example of capabi ity l st of PID.. 146 Annex D informat ive Track cur ent rat ing comput at ion met hodology.. 162 Annex F informat ive Prevent ion of resin st

Space product assurance —

T is British Standard is th UK impleme tatio of EN

16 02-70-12:2016

T e UK par icipation in it pre aration was e t us e to T ch ical

Commit e A CE/6 , Space sys ems an o erations

A ls of organiz tio s re rese te on this commit e can b

o taine o re u s to it secretary

T is pu lcatio d es not p rp r to includ al th n ces ary

prov isio s of a co t act User are resp nsible for it cor ect

ap l catio

© T he British Stan ards Ins itutio 2016

P bl sh d by BSI Stan ards Limite 2016

ISBN 978 0 58 93136 9

ICS 31.18 ; 4 14

C mpla ce w ith a British St and rd ca not conf er immu ity f rom

le al o l g tions

T is British Standard w as p blsh d u d r th auth rity of th

Standards P lcy an St ate y Commit e o 31 Octo er 2016

A me dme t / orr ige d is u d since publcation

NORME EUROPÉENNE

As uranc prod it des projet spatiau - R èg les de

c nc ption des circuit imprimés

R aumfahr prod kticheru g - Desig nreg eln für

Leiterplaten

This E rope n Stan ard was ap roved b C N on 2 May 2016

C Nan C NE E member are bou d to c mply with the C N/C NE E Internal R eg ulations which sip late the c n itions for

g ivin this E rope n Stan ard the satus of a national san ard without an alteration Up-to-date lss an biblog rap ic l

referenc s c nc rnin such national san ards may be obtained on ap lc tion to the C N-C NE E Manag ement Centre or to

an C Nan C NE E member

This E rope n Stan ard ex iss in thre oficial ver ions (E g lish, French, German) A ver ion in an other lang uag e made b

tanslation u der the responsibi ty of a C N an C NE E member into it own lang uag e an notified to the C N-C NE E

Manag ement Cente has the same satus as the oficial ver ions

C Nan C NE E member are the national san ards bodies an national ele tote h ic l c mmite s of Ausria, Belg ium,

B lg aria, Cro tia, Cyprus, Cz ch Rep blc, Denmark, Esonia, Finlan , Former Yug oslav R ep blc of Ma edonia, Franc , Germany,

Gre c , Hu g ary, Ic lan , Irelan , Italy , Latvia, Lith ania, L x embourg , Malta, Netherlan s, Norway, Polan , Porug al, R omania,

Slovakia, Slov enia, Spain, Sweden, Sw itz rlan , Turkey an United King dom

C N-C NE E Manag ement C ntre:

A ven e Marnix 1 , B-1 0 Brus els

Table of content s

European foreword 12

Int roduct ion 13

1 Scope 14

2 Normat ive references 15

3 Terms, definit ions and abbreviat ed t erms 16

3.1 Terms from ot her st an ard 16

3.2 Terms sp c ific to the present st andard 16

3.3 Abbrev iat ed terms 2

4 Principles 26

4.1 Qualfied PCBs 2

4.2 Manufac t urin toleranc es 2

4.3 R ela i t y of desig 2

5 Design review and MRR 28

5.1 Overv iew 2

5.2 Doc ument at ion 2

6 General design and product ion requirement s 30

6.1 R ela i t y of desig 3

6.2 Choic e of materials an buid-up 3

6.2.1 Ov erview 3

6.2.2 Mat erial selec t ion 3

6.3 Selec tion of t he PCB man fac t urer 3

6.4 Trac ea i t y an mark in 3

7 R igid PCBs 34

7.1 PCB buid-up 3

7.1.1 General 3

7.1.2 Cop er st yles 3

7.1.3 Dielec t ric thick nes 3

7.2 PCB dimen ion 3

7.3 Thick nes of PCB 3

7.3.1 General 3

7.3.2 Poly imide PCB 4

7.3.3 Epox y PCB 4

7.3.4 Numb r of c op er layers in PCB 4

7.3.5 Asp c t rat io of v ias 4

7.4 Track widt h an sp c in 41

7.4.1 General 41

7.4.2 Man fac t urin t oleranc es for widt h and sp c in 41

7.4.3 Ext ernal layers 4

7.4.4 Normal pit c h t rack s on internal layers 4

7.4.5 Fine pit c h t rack s on internal layers 4

7.4.6 R out in t o AAD foot print on internal layers 45

7.5 Pad desig 4

7.5.1 Non-u ct ional p d remov al 4

7.5.2 Pad dimen ion 4

7.5.3 Non-c irc ular ext ernal p ds 4

7.6 Co p r planes in ri id PCB 4

7.7 Design c on iderations for t he prev ent ion of slv er an p ela le 50

7.8 PCB s rfac e finis 50

7.8.1 Metal z at ion 50

7.8.2 Solder mas 51

8 Flex PCBs 52

8.1 Overv iew 52

8.2 Dynamic a plc at ion 52

8.3 PCB buid-up 52

8.3.1 General 52

8.3.2 Dielec tric materials 52

8.3.3 Cop er c laddin 53

8.3.4 Cop er planes in flex PCB 53

8.4 Track desig 54

8.5 Throu h holes 5

8.5.1 Ann lar rin 5

8.5.2 V ias an pad 56

8.5.3 Te r dro p d for flex PCB 56

8.6 Ben in radius 57

8.6.1 Overv iew 57

8.6.2 General 57

8.7 Sc ulpt ured flex PCB 58

8.7.1 Overv iew 58

8.7.2 General 58

8.7.3 Co p r foi dimen ion for buid-up 58

8.7.4 Connec t ion fin er 59

8.7.5 Throu h-holes 6

8.7.6 Bending radiu 61

9 R igid- flex PCBs 62

9.1 Overv iew 6

9.2 General 6

9.3 Buid-up 6

9.4 Cov er layer 6

9.5 Interfac e of rigid p rt an flexible p rt 6

9.6 Pad 6

10 Thermal rules and heat sinks 65

10.1 Overv iew 65

10.2 General req irement s 65

10.3 Sp c ific req irement s for ext ernal heat sink 65

10.3.1 Ov erview 65

10.3.2 Con truction of t he int erfac e b t ween PCB an he t sin 65

10.3.3 Dimen ional requirement s 6

10.4 Sp c ific req irement s for int ernal he t sin 6

10.4.1 General 6

10.4.2 Cu t hick nes an t ype 6

10.4.3 CIC an Molybden m in erts 6

10.4.4 Dimen ional requirement s 6

11 HDI PCBs 71

1 1 Overv iew 71

1 2 Ju tific at ion 71

1 3 Mic rov ia t ec hnolog 71

1 4 Mic rov ias 7

1 4.1 Buid-up of mic rovia layers 7

1 4.2 Design of mic rovias 7

1 4.3 Pad desig for mic rov ia 7

1 4.4 Ann lar rin for microv ias 75

1 5 Core PCB for HDI 75

1 5.1 General buid-up 75

1 5.2 Ann lar rin on vias for fine pit c h fo t print 7

1 5.3 Track widt h an sp c in on external layers 7

1 5.4 Track widt h an sp c in on int ernal layers for imp danc e c ont rol an routin t o AAD 7

1 5.5 Track widt h an sp c in on int ernal layers for diferential p ir routin w it hin t he fo t print of 1,0 mm pit c h AAD 7

1 5.6 Asp c t rat io of v ias for fo t print of AAD wit h 1 mm pit c h 7

12 PCBs for high f equency appl cat ions 81

12.1 Mat erial selec t ion 81

12.2 Buid-up of R F PCB 81

12.3 Emb d ed fim resist ors 81

12.4 Thick nes of R F PCB 8

12.5 Track widt h an sp c ing 8

12.5.1 External layers 8

12.5.2 Int ernal L yers 8

12.6 Pad desig 8

12.6.1 Pad dimen ion 8

12.6.2 Non-u ct ional p d 8

12.7 Surfac e finis 8

12.8 Profied layers an v ias 8

13 Elect rical requirement s for PCB design 86

13.1 Overv iew 8

13.2 General 8

13.3 PCB dryin 8

13.4 Elec t ric al c haract erist ic s 8

13.5 Float in met al 8

13.6 Curent ratin 8

13.6.1 Overv iew 8

13.6.2 R eq irement s for t emp rat ure inc rement 8

13.6.3 R eq irement s for t he model IPC-2152 for c urent ratin 8

13.6.4 Amen ment s to the model from IPC-2152 9

13.7 Provision t o prevent o en c irc uit aiure on crit ical track s 91

13.7.1 Ov erview 91

13.7.2 R out in 9

13.8 V olt age rat in 9

13.8.1 Ov erv iew 9

13.8.2 General requirement s 9

13.8.3 Spac in on flex an rigid-lex laminat e 9

13.8.4 Conformal c oat in 95

13.9 Double in ulat ion desig rules for crit ic al track s 9

13.9.1 Ov erv iew 9

13.9.2 Crit ic al nets 9

13.9.3 Prev ention of s ort c ircuit 9

13.10 Ins lat ion dist anc e of c ombined requirement s on rigid PCB 101

13.1 Cont roled imp danc e t rac k s 10

13.1 1 Definit ion spec ific to c ont roled imp danc e 10

13.1 2 General rules 10

13.1 3 Mic rost rip an striplne 10

13.1 4 Line imp danc e t ermination for en -t o-en c onfig rat ion 10

13.1 5 Line imp danc e terminat ion for mult idro c onfig ration 10

13.12 Digit al PCB 10

13.12.1 Ov erview 10

13.12.2 Zone management an rout in 10

13.12.3 Crit ic alt y of digit al sig als 10

13.13 Analog PCB 1 0

13.13.1 Ov erv iew 1 0

13.13.2 Crit ic alt y of analog signals 1 0

13.13.3 R out in an s ieldin 1 1

13.14 Mixed analog-digit al PCB 1 2

14 Design for assembly 113

14.1 Overv iew 1 3

14.2 General 1 3

14.3 Plac ement req irement s 1 4

14.3.1 Con uc tiv e p t t ern 1 4

14.3.2 Components 1 5

14.3.3 Component p d 1 7

14.3.4 Fan out of SMT p d 1 8

14.3.5 Fan out of PTH 12

14.4 Sp c ific req irement s for fu ed t in-le d finis 121

14.5 Dimen ional req irement s for SMT fo t print 121

14.5.1 Overv iew 121

14.5.2 General 12

14.5.3 Bip lar c omp nents 12

14.5.4 SOIC c omp nent s 12

14.5.5 J-le ded c omp nents 125

14.5.6 LCC c omponent s 12

14.5.7 Flat p ck c omp nent s 12

14.5.8 AAD c omponent s 12

15 Design of t est coupon 130

15.1 Desig rules for t est c oup n 13

15.2 Test c oupon design 13

Annex A (normat ive) PCB definit ion dossier - DR D 133

A.1 DR D ident ific ation 13

A.1.1 R eq irement ident ific ation an sourc e doc ument 13

A.1.2 Purp se an o ject ive 13

A.2 Expec t ed resp n e 13

A.2.1 Sc op an c ontent 13

A.2.2 Sp c ial remark s 13

A.2.3 Example fig res 13

Annex B (normat ive) PCB manufact uring dossier – DR D 144

B.1 DR D identific at ion 14

B.1.1 R eq irement ident ific ation an sourc e doc ument 14

B.1.2 Purp se an o ject ive 14

B.2 Expec t ed resp n e 14

B.2.1 Sc op an c ontent 14

B.2.2 Sp c ial remark s 145

Annex C (informat ive) Example of capabi ity l st of PID 146

Annex D (informat ive) Track cur ent rat ing comput at ion met hodology 148

D.1 Int rod c tion of t he t hree models 14

D.1.1 Ov erview 14

D.1.2 Formula for t he t hre models 14

D.1.3 Example of c urent rat in 150

D.2 Track c urent rating c omputation b sed on IPC-2152 150

D.3 Track c urent rating c omputation b sed on CNES/ QFT/ IN.01 3 154

D.4 Track c urent rating c omputation b sed on IPC-2 21A 158

Annex E (informat ive) Ex ample of calculat ion of PTH pad dimensions 162

Annex F (informat ive) Prevent ion of resin st arvat ion and crack s 164

F.1 Prevent ion of resin crack s 16

F.2 Prevent ion of resin st arvation 16

Annex G (informat ive) Example of MRR check list 166

Bibl ography 170

Figures

Figure 3-1: Simplfied buid-up of HDI PCB 2

Figure 3-2: Project ed p ak -to-p ak in ulat ion dist anc e 2

Figure 7-1: Example of aut omat ed fine pit c h rout ing an p s ible improvement s 45

Figure 7-2: Comp rison b t ween c irc ular an o lon p d s owin ann lar rin an the c ent re of t he hole misregist ered wit h t he c entre of the p d 4

Figure 7-3: Grid c op er plane wit h o enin s 4

Figure 7-4: Example of p elable (left ) an slv er (rig t ) 50

Figure 8-1: Cle ranc e of t rack s on flex PCBs 54

Figure 8-2: Track s on flex, definin t erminat ion an b n in z ones 5

Figure 8-3: Te rdro reinforc ement of terminal p d in flex PCB 56

Fig re 8-4: Ben in radiu of as embled flex 57

Fig re 8-5: Sc ulpt ured flex c irc uit 58

Fig re 8-6: Buid-up of sc ulpt ured flex c irc uit 59

Fig re 8-7: Con ect ion fin er of sc ulpt ured flex c irc uit 6

Fig re 8-8 Side view of a c omponent hole for sc ulpt ured flex 61

Fig re 9-1 Example of a buid-up of a 6 layer symmet ric rigid-lex 6

Fig re 10-1: L y out of he t sin and PCB 6

Fig re 10-2: dri in holes an slot s in int ernal he t sin 7

Fig re 10-3: Angle of int ersec t ion of overla pin holes 7

Fig re 11-1: Buid-up of HDI PCBs wit h stag ered (left ) an st acked (rig t ) mic rovia 7

Fig re 11-2: Dimple on a mic rovia 7

Fig re 11-3: Te r drop p d desig 7

Fig re 11-4: Example of rout in two diferent ial p ir t racks betwe n vias in a fo t pri t of an AAD wit h 1,2 mm pit c h 7

Fig re 11-5: Example of rout in t wo diferential p ir t racks b t ween v ias in a fo t print of an AAD wit h 1 mm pitc h 8

Fig re 13-1: Cros sec t ion of PCB with in ulat ion distanc es 8

Fig re 13-2: Example of double in ulat ion by inc re sin dist anc e in X ,Y an by not

s p rimp sin cop er on adjac ent layers 10

Figure 13-3: Example of double in ulat ion by inc re sin distanc es in X ,Y an by u in

two in ulat ors in Z direct ion 10

Figure 13-4: Ed e c oupled diferent ial st riplnes 10

Fig re 14-1: I ust rat ion of s rfac e pat t ern to adjacent s rou din s 1 5

Fig re 14-2: I ust rat ion of c omp nent plac in on PCB w.r.t adjac ent s rrou din 1 6

Fig re 14-3: I u t rat ion of p d plac in on PCB wit h respec t t o adjac ent s rou din s 1 8

Fig re 14-4: Fan out rom SMT p d t o v ia 1 9

Fig re 14-5: Example of p int symmet ric AAD fo t prin 12

Fig re 14-6: Track widt h (I

crat io to PTH p d (D) diamet er 12

Fig re 14-7: Track len t h (Lc) b t ween solderin p d of PTH (D

1) an v ia pad (D

3 121

Fig re 14-8: lu tration of bip lar c omponent pad 12

Fig re 14-9: I ustrat ion of SOIC c omp nent p d 12

Fig re 14-10: I u t rat ion of J-le ded c omp nent p d 125

Fig re 14-1 : I u t rat ion of LCC c omp nent p d 12

Figure 14-12: I u t rat ion of FP an QFP c omp nent pad 12

Figure 14-13: I u t rat ion of AAD c omp nent p d 12

: Example of PCB mec hanic al layout 13

Figure A-1

: Example of a dri in drawin 14

Figure A-2

: Example of a ta le in ic atin as-designed plated hole diamet ers 141Fig re A-3

: Example of buid-up dat a 14

sc ale 151

: IPC-2152: Track widt h [ mm] v s c ros sec tional area [mm

2

] 151Fig re D-3

: IPC-2152: Curent rat in b sed on Figure D-2, ran e 0-25 A 152 Fig re D-4

: IPC-2152: Curent ratin b sed on Fig re D-2, ran e 0-10 A 152 Figure D-5

: IPC-2152: Curent rat in b sed on Fig re D-2, ran e 0-5 A 153 Figure D-6

: IPC-2152: Curent rat in b sed on Fig re D-2, ran e 0-2 A 153 Figure D-7

: CNES/ QFT/IN.01 3: Curent ratin [ A] v s c ros sec t ional are [ mm

2

] in Fig re D-8

double log sc ale 15

: CNES/ QFT/IN.01 3: Track widt h [ mm] vs c ros sect ional are [ mm

2

] 15Fig re D-9

: CNES/ QFT/ IN.0113: Curent ratin based on Fig re D-8, ran e 0-25 A 156 Fig re D-10

: CNES/ QFT/ IN.0113: Current rat in based on Fig re D-8, ran e 0-10 A 156 Fig re D-1

: CNES/ QFT/ IN.0113: Curent rat in b sed on Fig re D-8, ran e 0-5 A 157 Fig re D-12

: CNES/ QFT/ IN.0113: Curent rat in b sed on Fig re D-8, ran e 0-2 A 157 Fig re D-13

: IPC-2 21A: Curent rat in [A] vs c ros sect ional are [ mm

2

] in double log Fig re D-14

sc ale 159

: IPC-2 21A: Track widt h [ mm] v s c ros sectional are [ mm

2

] 159 Fig re D-15

: IPC-2 21A: Curent ratin b sed on Figure D-14, ran e 0-25 A 16

Fig re D-16

: IPC-2 21A: Curent rat in b sed on Figure D-14, ran e 0-10 A 16Figure D-17

: IPC-2 21A: Curent rat in b sed on Figure D-14, ran e 0-5 A 161Figure D-18

: IPC-2 21A: Curent rat in b sed on Figure D-14, ran e 0-2 A 161Figure D-19

: PCB man fac tu n t oleranc es for regist ration an an ular rin for HDI Figure E-1

Ta le 6-1: Charact eristic s of some example dielec t ric mat erials for laminat es 3

Ta le 7-1: As-desig ed v ers s as-man factured cop er foi t hick nes 3

Ta le 7-2: Example of worst c ase as-man fac t ured in ulat ion distanc e for laminat e

wit h double-sided c opp r c lad in 3

Ta le 7-3: Toleranc e on track width and sp c in of int ernal an ext ernal layers 4

Ta le 7-4: Minimum as-man fact ured track width an sp c in for ext ernal layers as a

fu c tion of c op er thick nes 4

Ta le 7-5: Minimum as-man fact ured track width an sp c in for int ernal layers as a

fu c tion of c op er thick nes 4

Ta le 8-1: Minimum as-man fact ured dimen ion of sc ulpt ured flex c ond c t or 59

Ta le 12-1: Minimum sp c in an widt h as-desig ed for R F element s on external

layers 8

Ta le 13-1: L gen of t erms 8

Ta le 13-2: Curent overlo d lmits 8

Ta le 13-3: Minimum in ulation dist anc e as func t ion of v oltage on as-man fac t ured

PCB for rigid laminat e 9

Ta le 13-4: Minimum in ulat ion dist anc e as func tion of v olt age on as-man fac t ured

PCB for flex laminate 95

Ta le 13-5: Minimum double in ulat ion dist anc e as fu ct ion of v oltage on

as-man factured PCB for rigid laminat e 9

Ta le 13-6: Minimum double in ulation dist anc e as fu ction of v olt age on

as-man fact ured PCB for flex laminate 9

Ta le 13-7: Minimum in ulat ion distanc es on rigid PCB as fu ction of al combined

requirements (part 1 of4) 10

Ta le 14-1: Minimum dist anc e as-manufactured of t he s rfac e p t t ern to the adjac ent

s rrou din s 1 4

Ta le 14-2: Minimum dist anc e as-manufactured of c omp nent s t o adjac ent

s rrou din s 1 6

Ta le 14-3: Minimum dist anc e as-manufactured t o c omp nent p d 1 7

Ta le 14-4: Minimum trac k len t h t o c omp nent p d 12

Ta le 14-5 L gen for dimen ion of c omponent s an foot print 12

Ta le 14-6 As-man fact ured p d siz es for bip lar c omp nent s 12

Ta le 14-7: As-man fac t ured pad siz es for SOIC c omp nent s 12

Ta le 14-8: As-man fac t ured pad siz es for J-le ded c omp nent s 125

Ta le 14-9: As-man fac t ured pad siz es for LCC comp nents 12

Ta le 14-10: As-man fac t ured pad siz es for FP an QFP c omp nents 12

Ta le 14-1 : As-designed p d diamet er for AAD c omp nent s 12

: Example of t ec hnic al c ap bi t ies of PCB man fac t urer as sp c ified in t he

Ta le C-1

PID 14

European foreword

Th is documen t (EN 16 0 -7 0-12:2 16) h as be n prepared b Techn ical Commit t ee

CEN-CENELEC/ TC 5 “ pa ce”, th e sec et ariat of wh ich is h eld b DIN

Th is Euro e n St an da rd (EN 16 0 -7 0-12:2 16) origin at es f rom ECS -Q-ST-70-12C

Th is Euro e n St an dard sh al be giv en th e st atus of a n at ion al st an dard, eit h er b publ cat ion of an

iden t ical t ext or b en dor emen t , at h e lat est b Apri 2 17 , an d con flictin g n at ion al st an dards shal be

wit h drawn at t h e lat est b Apri 2 17

At t en t ion is drawn t o t h e p s ibi t y t hat some of h e elemen t s of th is documen t may be t h e subject of

pat ent righ t s CEN [a n d/ or CENELEC] sh al n ot be held resp n sible for iden t ifyin g an y or al such

pat ent righ t s

Th is documen t ha s be n prepared un der a man dat e giv en t o CEN b t h e Euro e n Commis ion an d

t h e Euro e n Fre Trade As ociat ion

Th is documen t h as be n dev elo ed t o cov er specifica lly space syst ems an d h as th erefore preceden ce

ov er any EN cov erin g th e same s o e but wit h a wider domain of ap lcabi t y (e.g : a rospace)

Ac ordin g t o t h e CEN-CENELEC In t ernal R eg ulat ion s, t h e nat ion al st an dards organ iz t ion s of t h e

folowin g coun t ries are b un d t o implemen t t h is Euro e n St an dard: Aust ria, Belgium, Bulgaria ,

Croat ia, Cy rus, Cz ch Republc, Den mark , Est on ia, Fin lan d, F rmer Y ug oslav Republc of

Macedon ia, Fran ce, German y, Gre ce, Hun ga ry, Icelan d, Irelan d, It aly, La tv ia, Lit h uan ia,

L x mb urg, Malt a, Net herlan ds, Norway, Polan d, Port ug al, Roman ia, Slov ak ia, Slov en ia, Spain ,

Sweden , Swit zerlan d, Turkey an d th e Un it ed K in g dom

PCBs are used f or t h e moun t in g of elect ron ic c omp n en t s t o prod ce PCB

a ssembles t h at perform elect rical f un ct ion s Th e PCBs are subject ed t o t h

ermo-mechan ical st res d rin g as embly such as solderin g of comp n en t s, rework

a n d repair un der n ormal t er est rial c on dit ion s In ad it ion t h e as embled PCBs

a re e p sed t o t h e la un ch an d space env iron men t Th e rela bi t y of t h e cir uit

depen ds on t h e ro ustn es of t h e design , amon g ot h er f act or Moreov er, PCB

design wit h h igh t echn olog ical comple it y en ables t h e use of comple

comp n en t s wit h advan ced f un ct ion alt y

Th is Euro e n St an dard specifies t h e requiremen t s f or t h e sup ler an d PCB

man uf act urer for PCB design

Th is Euro e n St an dard is ap lcable for al t ypes of PCBs, in c lu in g

sequen t ial, rig id an d f le ible PCBs, HDI an d R F PCBs

Th is Euro e n St an dard can be made ap lcable f or ot h er prod ct s combin in g

m echan ical an d elect rical f un ct ion alt y usin g ad it iv e or red ct iv e

man uf act urin g proces es, as used in PCB man ufacturin g Ex mples of such

prod ct s are slp rin gs an d bus bar

Th is Euro e n Stan dard may be taiored f or t h e specific ch aract erist ic an d

con st ra in t s of a spa ce project in con f orman ce wit h ECS -S-ST-0

2

Th e folowin g documen t s, in wh ole or in part , are n ormat iv ely ref eren ced in

t h is documen t a n d a re in dispen sable f or it s ap lcat ion F r dat ed referen ces,

on ly t h e edition c it ed ap les F r un dat ed ref eren ces, t h e lat est edit ion of t h e

ref eren ced documen t ( n clu in g an y amen dmen t s) apples

EN ref erence Ref er ence in te t Tit le

EN 16 0 -0 -01 ECS -S-ST-0 -01 ECS syst em – Glos ary of t erms

EN 16 0 -70-0 ECS -Q-ST-70-0 Space product as uran ce - Th ermal vacu m

out gas in g t est for t h e s re n in g of space mat erials

EN 16 0 -70-0 ECS -Q-ST-70-0 Space product as uran ce - Man ual solderin g of h igh

-relabi t y elect rical con n ect ion s

EN 16 0 -70-10 ECS -Q-ST-70-10 Space product as uran ce - Qualf icat ion of prin t ed

cir uit b ards

EN 16 0 -70-1 ECS -Q-ST-70-1 Space product as uran ce - Procuremen t of prin t ed

cir uit b ards

EN 16 0 -70-3 ECS -Q-ST-70-3 Space product as uran ce -High -relabi t y solderin g

f or surface-moun t an d mix d t ech n olo y

EN 16 0 -2 ECS -E-ST -2 Space en g in eerin g – Elect rical an d elect ron ic

EN 16 0 -2 -0 ECS -E-ST -2 -0 Space en gin eerin g - Spacec aft chargin g

IPC-215 , Aug ust 2 0

St an dard f or det ermin in g c ur en t car ying capa cit y in

prin t ed b a rd desig n

IPC-4101D, Apr il 2 14

Specificat ion for base mat erials f or rig id an d

mult ilayer prin t ed b ards

IPC-4 6 A, Apri 2 0 Met al f oi f or prin t ed wiring ap lca t ion s

3

a F r t h e purp ses of t h is documen t, th e t erms a nd defin ition s f rom

ECS -S-ST-0 -01 ap ly, an d in part icular f or t h e f olowin g t erms:

1 sup ler

NOTE In th e con t ext of th is Euro e n Stan dard t h e

sup ler is also resp n sible f or t h e design of t h e

PCB

3.2.1 annular ring

rin g of c op er pad sur oun din g t h e dri ed h ole

NOTE Th e me suremen t of ann ular rin g is dif feren t

on in t ern al an d e tern al layer S e

Subclause 6.3.1 from ECS -Q-ST-7 0-1

surf ace moun t pack age wherein t h e solder t erm in at ion s a re formed in a grid on

t h e b t t om of t h e packa ge

NOTE BGA an d CGA are specif ic t ypes of AAD

3.2.3 artwork

g raph ical represen t at ion of in div id al layer

NOTE Ex mples of art work a re: con duct iv e layer ,

solder mask , sik s re n , select iv e f in ish es, h eat

sin k

3.2.4 as- designe

st at e of t h e PCB in t h e design phase

NOTE Th is t ypica lly ref er t o dimen sion s as ociat ed

wit h t h e design ed PCB, wh ich does n ot t ak e

in t o ac oun t man uf act uring t oleran ces

3.2.5 as-ma ufa tured

st at e of t h e PCB aft er man uf act urin g

NOTE Th is t ypicaly refer t o dimen sion s me sured

on t h e man uf act ured PCB, t h e f in al pr od ct

Th e dimen sion s are me suremen t s th at in clu e

man ufact urin g t olera n ces

3.2.6 as- ma ufa ture hole

h ole in a s-man uf act ured PCB aft er al proces st eps

NOTE In case of a plat ed through -h ole, an

as-man uf act ured h ole in clu es plat in g an d surf ace

PCB wit h al it s elect r on ic an d mechan ical comp n en t s moun t ed, hav in g

un derg n e al t h e man uf acturin g o erat ion s

NOTE Ex mples of man uf acturin g o erat ion s are

wirin g, solder in g, wire-b n din g, gluin g,

s rewin g, p t t in g an d con f ormal coat in g

3.2.9 as embly house

company perf ormin g as embly of PCB

3.2.10 back - dri e hole

v ia wit h part of it s met al sat ion remov ed on on e side b dept h con t roled

mechan ical dri in g wit h a larger diamet er dri

t ype of v ia e p sed on ly on on e side of t h e PCB

NOTE On e met h od t o man uf act ure a bln d v ia can be

b dept h con t roled dri ing A secon d met h od

can be b seq uen t ial la minat ion of min imum 2

h alf -st acks

t ype of v ia con n ect in g in t ern al layer wit h out bein g e p sed on eit h er surf ace

3.2.17 column grid ar a (CGA)

surf ace moun t packag e wherein t h e column s f or t ermin at ion s are formed in a

g rid on t h e b t t om of a pack age

NOTE CGA is a specific t ype of AAD

3.2.18 conductiv e la er

elect ricaly c on duct iv e parts of a PCB on t h e same layer

NOTE Th e con duct iv e layer can con t ain t rack s, pla n es

or pads

3.2.19 conductor

con duct iv e elemen t s wit h in t h e PCB

NOTE Elemen t s wit h in t h e con duct iv e layer an d v ias

are con duct or

3.2.20 crit ic l net

con duct iv e cir uit wit h a specific f un ct ion alt y t h at req uires red n dan t

solu on s t o av oid los of f un ct ion alt y in case of an y c edible sin g le faiure

NOTE Red n da nt solu on s can be double in sulat ion ,

in cre sed co per c os sect ion , mult iple v ias

3.2.21 crit ic l t ra k

t rack th at is part of a c it ica l n et

3.2.22 double insulation

bar ier bet we n t rack s or elemen t s of an elect ron ic c ir uit t h at prov ides

in sulat ion of t rack s or elemen ts of an elect ron ic c irc uit in case of an y c edible

sin g le f aiure

3.2.2 dri e hole

h ole aft er dri in g a n d bef ore plat in g

NOTE In case of a pla t ed t h rough -h ole, dri ed h ole

e clu es plat in g an d surf a ce f in ish

3.2.24 ele tric l field

v olt ag e per in sulat ion dist an ce betwe n two con duct or

NOTE Th is is a simpl fied represen t at ion of elect rical

f ield a pplcable for PCB design

3.2.25 fine pitc

spacin g of t racks or pads t hat is more den se t han f or n ormal pit ch

NOTE Th e e act perimet er of f in e pit ch on e t ernal

an d in t ernal layer is des ribed in

NOTE Term “t h ermal drain ” is syn on ymous wit h t h e

word “h eat sin k ”

3.2.29 high de sity interconnect (HDI)

t ech n olo y on PCB relat ed t o t h e pat t ern t hat alows a smaler pit ch in t h e

foot pr in t on t h e surf ace pat t ern an d a h igh er den sit y of in t ern al sign al rou n g

t h an f or con v en t ion al PCBs

NOTE 1 Th e e act perimet er of HDI t ech n olo y is

des ribed in Clause 1

NOTE 2 Th is t echn olog y can be req uired f or as embly of

AAD

NOTE 3 An e ample of HDI buid-up is sh own in

Fig ure 3-1

Fig ur e 3-1: Simpl f ied bui d-up of HDI PCB

3.2.30 high spe d signal

elect ronic f un ct ion alt y t h at req uires specific design precau on s t o main t ain

t ime depen dan t sign al in t egrit y

NOTE Th is is f urt h er specif ied in IPC-2 51 an d

IPC-2141A

3.2.31 hole wal pul a wa

a dh esion defect betwe n co per of t h e h ole wal an d resin

3.2.32 HT E

g rade of co per foi wit h t h e grade desig nat ion “h igh t emperature elon gat ion

elect rodep sit ed”

NOTE Th is is specified in IPC-4 6 A

g rade of co per foi

NOTE Th is grade of co per foi is prod ced b

GOULD Elect ron ic GmbH

3.2.36 laminate

sh eet s of f uly cured, C-st a ge, resin wit h co per clad in g

NOTE Rigid lamin a t e in clu es rein for emen t , f or

e ample b wov en glas f ibres or n on -wov en

aramid fibres

3.2.37 microv ia

bln d v ia man ufactured b laser ablat ion wit h a diamet er smaler t h an

con v en t ion al v ias

NOTE 1 Micr ov ias are req uired for rou n g in t ern al

sign als in HDI PCBs

NOTE 2 Ex mple of mic ov ia con figurat ion is sh own in

Fig ure 3-1

3.2.38 microv ia la ers

layer of con duct iv e pat t ern t hat con tain mic ov ias

NOTE mic ov ia layer are layer 1 a n d 2 an d o p sit e

layer

3.2.39 mi

un it of len gt h eq ual t o 2 ,4 µm

NOTE Th e un it mi is in some cases cust omary in PCB

design an d t h erefore prefer ed ab v e th e SI

un it

3.2.40 no- flow prepre

t ype of prepreg t h at has a red ced f low of resin d ring pres cycle

NOTE Th e t erm “low-low prepr eg” is syn on ymous

wit h th e word “n o-f low prepreg” Th e t erms do

n ot specif y t h e e act amoun t of flow

pad on in t ern al co per layer wit h out elect r ical con n ect ion

3.2.42 non- plat ed hole

h ole in a PCB th at does n ot con tain plat i g or ot h er ty e of con duct iv e

rein f or emen t

3.2.43 normal pitch

st an dard spacin g of t rack s an d pads

NOTE S e “fin e pit ch ”for an ot h er cat eg ry of pit ch

3.2.44 number of lay rs

n umber of layer in a PCB con t ain in g con duct iv e elemen t s

NOTE F r e ample, t h e n umbering con v en on is f rom

t op t o b t t om layer: L1, L2, …,Ln -1, Ln

a re s of ph ot o resist or co per t hat hav e p or adh esion t o un derlyin g subst rat e

because of a t apered shape wit h a nar ow dimen sion on on e en d

3.2.48 plate through- holes (PT H )

met al-pla t ed h oles dri ed t h rough al t h e layer used for as embly of

comp n en t s

3.2.49 printe circ it board (PCB)

prod ct result in g from t h e proces of selectiv ely et ch in g u wan t ed co per f rom

surf aces of co per cla d in sulat in g subst rat es t o form a desired cir uit ry pat t ern

wh ich is met al-plat ed an d laminat ed

NOTE Ex mples of specif ic PCB t ech n olo ies are rigid,

fle ible, rigid-le , double sided, mult ilayer,

sequen t ial, R F an d HDI PCBs

3.2.50 pre re

sh eet s of part ly cured, B-st age, resin wit h rein for emen t

NOTE Ex mples of rein for emen t are wov en glas

fibres an d n on -wov en a ramid fibres

3.2.51 R F eleme ts

con duct iv e patt ern on PCB wit h specif ic RF f un ct ion alt y

NOTE F r e ample filt er , c ombin er , splt t er ,

coupler RF elemen t s do n ot h av e v olt ag e

rat in gs or solder c on n ect ion s

design f eat ure t o be in clu ed in t o t h e PCB def in it ion dos ier an d rev iewed

d rin g t h e PCB design rev iew

3.2.5 proje te pe k - to-pe k insulat ion dista c

wor t -case min imum th ick n es of dielect r ic mat erial t h at in clu es t h ick n es

t oleran ce of t h e lamin at e core an d t h e ma imum roug h n es of co per surf ace

t re t men t

NOTE Fig ure 3-2 specifies h ow t h is is me sured

Fig ure 3-2: Pr oje t ed peak -t o-peak insulat ion dist anc

3.2.55 serial zation

proces of n umberin g of e ch un ique PCB b t he PCB man uf act urer f or

t race bi t y

3.2.56 sl ver

pieces of ph ot o resist or co per t hat h av e p or adh esion t o un derlyin g subst rat e

because of t h e smal surface are

NOTE F r e ample, a surf ace are below 0,01 mm

2

3.2.57 soldering pa

con duct iv e part in t en ded f or solder in g comp n en t s on t h e PCB

3.2.58 spa ing

in sulat ion dist an ce

NOTE Th e t erm “gap” is syn on ymous wit h t h e word

“spacin g ”, but t h is t erm is n ot used in t h e

presen t stan dard

3.2.59 sta k

a ssembly comprisin g of one sequen ce of lamin at ed layer

NOTE Half-st ack iden t if ies t h e sub-as embly

3.2.60 test pa

pad t hat is dedicat ed for elect rica l t est in g on t h e PCB

3.2.61 trac

con duct iv e part rou n g th e elect rical con n ect ion bet we n t h e pa ds

NOTE Th e t erm “ln e” an d t he t erm “con duct iv e

t rack ” a re syn on yms wit h th e word “t rack ”

Abbr eviation Me ning

4

Qualf ied PCBs for space ap lcat ion me t t h e f olowin g con dit ion s:

b PCB is procured in con forman ce wit h req uiremen t s of ECS -Q-ST-7 0-1 ,

c PCB is procured from a PCB man uf acturer th at is q ualf ied in

con f orman ce wit h req uiremen ts of ECS -Q-ST -7 0-10,

d t h e PCB t ech n olo y is qualfied in con forman ce wit h requiremen ts of

ECS -Q-ST-70-10 for t h a t PCB man ufacturer,

e t h e PCB design is in con f orman ce wit h th e req uiremen t s of ECS

-Q-ST-7 0-12, an d

f t h e PCB design , t h e man ufacturin g proces an d mat erials are in

con f orman ce wit h th e PID of t h e PCB man f acturer

PA requiremen t s of space project s use t h is Eur ope n St an dard a s ap lcable

documen t Based on t h eir h erit age, sup ler can pro ose t h e re-use of e ist in g

PCB design s t h at are “recur en t ” an d t hat are n ot in complan ce wit h al design

requiremen t s of t h is Euro e n Stan dard Th e p s ible ac eptabi t y of t h ose

cases is rev iewed b t h e project on case b ca se basis Th e PCB design is

“recur en t ” on ly wh en n o ch an g es are made in t h e art work , rou n g, lay-out ,

buid-up, mat erial select ion

Dimen sion al me surements of PCBs are “ s-design ed” e cept wh en e plcitly

men t ion ed “ s-ma nuf act ured”

Design values are aff ect ed b th e man uf act urin g toleran ces Th e min imum

value on t h e PCB as-man f a ct ured equals t h e design value subt ract ed wit h t h e

man uf act urin g t oleran ce S e definit ion of t erms in Subclause 3.2

Specific design feat ures of PCBs are recorded as Rev iew It ems in t h e PCB

def in ition dos ier Th is is don e wh en th e design f eat ures in clu e a h igh er

t ech n olo ical comple it y t hat can aff ect man uf act urabi t y or (t h ermal

relabi t y Th ese desig n f eat ures are specif icaly ev aluat ed b q ualficat ion prior

t o in clusion in t h e PID

Req uiremen t s in t h is Euro e n Stan dard g en eraly st at e min imum dimen sion s

permit t ed I is g od pract ice t o use min imum dimen sion s on ly wh en n eces ary

t o a ch iev e t h e desired f un ct ion alt y an d t o design wit h marg in wh en p s ible

F r in st an ce, it is recommen ded t o implemen t min imum in sulat ion dist an ce

betwe n t rack s on ly wh en space lmit at ion s prev en t larger in sulat ion dist an ce

I is recommen ded t o implemen t f an out of t rack s wh ich alows for larg er

in sulat ion dist an ces wh ere more spa ce is av a ilable

Th e ro ustn es of t h e PCB ca n be a f f ect ed wh en combin in g mult iple design

feat ures at th e lmit of t h e requiremen t or recorded as Rev iew It em Th e PCB

man uf act urer an d t h e sup ler ev aluat e th is risk d rin g th e design rev iew an d

prov ide f ormal a pprov al d rin g t h e MRR Th e relabi t y of t h e man uf act ured

PCB is ev aluat ed b in spection on represen t at iv e coupon s

5

Th is clause specifies t h e iterat iv e proces of desig n in g a PCB in cola borat ion

wit h t h e PCB man facturer an d specif ies as ociat ed documen ta t ion f or t h e

formal aut h oriz t ion for man uf a ct ure

a Th e sup ler sh al is ue t h e PCB def in ition dos ier in con forman ce wit h

t h e DR D in An n ex A

b Th e sup ler sh al lst design feat ures as Rev iew It ems in con f orman ce

wit h Subclause A.2.1<7> f r om t h e DRD of t h e An n ex A

c Th e sup ler may lst ot h er design f eat ures as Rev iew It ems

d Th e sup ler sh al submit t h e PCB defin ition dos ier t o t h e PCB

man uf act urer f or t h e desig n rev iew

e Th e sup ler sh ould submit t o t h e PCB man uf a cturer t h e draf t PCB

def in ition dos ier or a lst of spec ific R ev iew It ems specified in t h e

requiremen t 5.2b in t h e desig n phase, wh en th ose Rev iew It ems are at t h e

lm it of t h e PID capabi t y

NOTE Ex mples of R ev iew It ems t hat can be on t h e

lm it of PID capabi t y are: dimen sion s, n umber

of layer , ma imum aspect rat io, n umber of

sequen ces, mat erial selection or a c ombin at ion

of t h ese Con sult at ion wit h PCB man uf act urer

at th is e rly desig n st age is recommen ded t o

av oid un n eces ary risk s Mult iple it erat ion s can

be perf ormed t o ach ieve an a gre d PCB

def in ition dos ier

f Th e PCB man uf acturer sh al rev iew t h e PCB defin ition dos ier in clu in g

Rev iew It ems for complan ce wit h t h e PID

g As a result of t h e design rev iew, th e PCB man f acturer may iden t if y t o

t h e sup ler ad it ion al R eview It ems in t h e PCB defin it ion dos ier

NOTE Rev iew It ems can e ist f or PCB desig n s ev en

wit h in t h e capabi it y of t h e PID Th ese Rev iew

It ems an d meth ods t o mit ig at e t h em are

specif ied in t h is Euro ea n St an dard as best

pract ices an d recommen dation s

h Th e PCB man uf acturer shal pr ov ide t h e PCB man fact urin g dos ier in

con f orman ce wit h DR D in t h e An n ex B

i Th e PCB man f acturer sh al is ue t o t h e sup ler a MRR ch eck list , wh ich

is part of t h e PCB m an uf act urin g dos ier, in con f orman ce wit h t h e DRD

in t h e An n ex B

NOTE An e ample of a MR R ch eck list is g iv en in

An n ex G

j Durin g th e MRR , sup ler an d PCB man uf act urer shal ap rov e t h e PCB

man uf act urin g dos ier, t h e PCB def in ition dos ier an d al Rev iew It ems

NOTE Th e ap ro als are recorded in t h e MR R

ch eck list

k Th e MR R shal prov ide auth orisat ion for man uf act ure t o t h e PCB

man uf act urer

6

a Th e sup ler sh al design th e PCB wit h margin

NOTE Th is is also des r ibed in Subclause 4.3

F r t h e select ion of mat erials for PCB a n umber of ph ysical pro ert ies are

imp rt an t , such as Tg, Y oun g’s mod lus, dielect ric con sta n t , CTE, hyg ros o y

Table 6-1 pr ov ides an ov erv iew of some common ly used mat erials an d t h eir

ph ysical pro ert ies Th e CTE of t h e as-man fact ured PCB depen ds on th e t ot al

co per t h ick n es , wh ich has a CTEof ab ut 16 p m/ K

I is imp rt an t t hat f or t h e select ion of t h e t ech n olog y f or t h e PCB design th e

folowin g is t ak en in t o ac oun t :

• CTE mismat ch betwe n dev ices an d PCB,

• moist ure sen sit iv it y of PCB f un ct ion ,

• in t er on n ect ion con st rain t s,

• lay-out con st ra in t s

Rigid-le b ards can be pref er ed t o r ed ce t h e in t er on n ect ion con st ra in t s

Polyimide an d ep xy are th e most common ly used mat erials Polyimide h as an

adv an tage ov er ep xy because it is more t h ermaly st able an d out performs

ep xy in t h ermal cycln g an d as embly At t h e same t ime, p ly imide is more

h ygros o ic t h an ep xy, wh ich af fect s PCB g roun d use an d as embly E oxy is

av aiable wit h diff eren t g las t ran sit ion t emperatures (Tg ) Hig h er glas

t ransit ion t emperature is recommen ded for ep xy because it prov ides bet t er

t h ermal st abi t y Th ermal e pansion of r esin in Z direc t ion below an d ab v e Tg

is t ypicaly h igh er t han e pansion of co per Th eref ore it is ben eficial for

t h ermal en duran ce t o use mat erials wit h low CTE in Z direct ion Flame

ret ardan t s in base mat erials are common ly required f or groun d based

ap lca t ion s but a re n ot n eces ary f or space ba sed PCBs

F r h ig h f requen cy perf orman ce t ypica lly P F based mat erials are used Th ese

mat erials require special la minat ion cycles as adh esion is gen eraly p orer

compared t o p ly imide an d ep xy

IPC-4121 prov ides a comparison of v arious pro erties f or core c on st ruct ion s as

fun ct ion of resin an d g las ty e

6.2.2 Mat erial select ion

a S lection of t h e base laminat e mat erials shal be performed in complan ce

wit h t h e requiremen t s f rom t h e Subclause 5.2.1 of t h e ECS -Q-ST-7 0-1

b Th e mat erial select ion f or al t ypes of PCBs sha ll be in complan ce wit h

t h e requiremen ts f rom t h e clauses 7 1t o7 6 of t h e ECS -Q-ST-7 0-1

NOTE Ex mples of t ypes of PCBs are: sin gle sided,

double sided, mult ilayer, sequen al, rig id,

rigid-le , f le ible, s ulpt ured fle , HDI, R F

c Th e as-man ufactured PCB sh al be in con forman ce wit h t h e out gas in g

requiremen t s of t h e Subclause 5.5.3 f r om t h e ECS -Q-ST-7 -0 or project

specif ic requiremen t s on cle n lin es

NOTE Th e out gas in g requiremen t s are CVCM< ,1%

a n d RML<1,0%

a Th e sup ler sh al procure PCBs from a PCB man ufacturer wit h a

qualficat ion ap rov al f or an iden t ified t ech n olog y in con f orma n ce wit h

t h e requiremen ts from t h e Clause 5 t o Clause 9 of t h e ECS -Q-ST-70-10

b Th e sup ler sh al proc ure t h e PCBs in con forman ce wit h t h e

requiremen t s from t h e Clause 5 t o Clause 7 of t h e ECS -Q-ST-7 -1

a Th e PCB shal be mark ed wit h part n umber an d revision n umber f rom

t h e PCB def in it ion dos ier as giv en b th e sup ler

b Al in div idual PCBs wit hin t h e pan el shal be iden t if ied b a serial

n umber

c Th e serialz t ion of t h e PCB shal be est ablsh ed bef ore t h e start of th e

fabricat ion

d Th e serial n umber shal iden t if y t h e p sit ion of t h e PCB on t h e pan el

e Th e serial n umber met h odolo y sh al be iden t ified in th e PID of t h e PCB

man uf act urer

7

a Th e buid-up of t h e PCB an e ch sub-as embly sh ould be symmet ric

NOTE Th is is don e t o av oid warp an d twist

b Th e sup ler sh al record a symmet ric buid-up as a Rev iew It em in t h e

PCB defin ition dos ier

NOTE Th e buid-up in clu es t h e c op er t h ick n es an d

it s dist r ibu on

c In case Moly den um or CIC layer are used, th ey shal be in clu ed in t h e

buid-up an d recorded as a R ev iew It em in t h e PCB def in ition dos ier

NOTE 1 Specific requiremen t s f or th e buid-up are lst ed

in t h e PCB def in ition dos ier in A.2.1< 5> 3(h )

NOTE 2 On e t ernal layer , co per clad lamin at e

t ypicaly ach iev es bet t er pe l st ren g t h wh ere s

co per foi ach iev es bet t er reg ist rat ion

a Th e t h ick n es of t h e co per cla ddin g on b t h sides of t h e laminat e sh ould

be eq ual e cept on out er layer of t h e PCB or h alf -st ack

NOTE E ual co per t h ick n es is n eeded wh en

lamin at e is et ch ed in same proces st eps, as is

t h e ca se f or in t ern al layer Th e e cept ion on

out er layer is made because e ch side is et ch ed

in diff eren t proces st eps an d because t h in

co per on e t ern al layer dec e ses t h e t otal

t h ick n es af t er plat in g

b In case th e t h ick n es of t h e co per clad in g on t h e laminat e is

asymmet ric, t h is asymmet ric buid-up of t h e PCB sh al be recorded a s a

Rev iew It em in t h e PCB def in ition dos ier

NOTE 17 / 70 co per t h ick n es is more risk y t han 17 / 35

or 3 /7 0 c op er t h ick n es Th e presen ce of fin e

pit ch t rack s in combin at ion wit h a symmet ric

co per f urt h er in cre ses t h e difficult y t o

proces

c Except th e case specified in t h e requiremen t 1 4.1e, t h e e t ernal an d

in t ern al layer shal use basic co per t h ick n es 7 0µm, 3 µm or 17 µm

NOTE 1 Co per layer can be implemen t ed as co per

clad lamin at e or as separat e co per fois

NOTE 2 Req uiremen t 1 4.1e spec if ies mic ov ia layer

on HDI PCBS

d Co per dist r ibu on wit h in a layer sh ould be h omo eneous

NOTE Th is is don e t o en sure ev en pres ure

dist ribu on d r in g lamin at ion , wh ich can

cause f il n g v oids, c ack s or glas compres ion

e Balan cing of co per sh ould be perf ormed b in clu in g d mmy n on

-f un ct ional co per

NOTE Th is is more imp rt an t f or part ial plan es on

t h ick co per layer such as 7 0 µm

f Sign al t rack s sh ould n ot be rout ed on co per plan e layer

g In case t h e t otal as-design ed t h ick n es of co per is ab v e 7 00 µm, t h is

sh al be recorded as a Rev iew It em in t h e PCB def in it ion dos ier

NOTE High layer coun t in combinat ion wit h th ick

co per layer can h av e sign if ican t impact on

man uf act urabi t y a n d lon g-t erm relabi t y

h Co per qualt y “HTE” sh al be used for co per c lad lamin at e

NOTE Ty e HTE can be procured in con f orman ce

wit h IPC-4 6 Ty e E, grade 3

i Co per qualt y “JTC” or “HTE" shal be used f or co per fois

j Th e values f rom th e Table 7 -1 sh ould be used in th e design calcula t ion s

f or co per f oi t h ick n es

NOTE Th e values in dicat ed in Ta ble 7 -1 a re m in imum

as-man f a ctured t h ick n es f or t h e specified a

s-desig n ed f oi t hick n es

Table 7 -1: As-designed versus as-manuf act ured copper f oi t hicknes

As-desig n ed f oi

t hick nes

(µm )

as-manuf act ur ed t hick nes

f or non-plat ed inner layer s

(µm )

Minimum as- manuf a ct ur ed

t hick nes f or plat ed layer s

c In case a sin g le sh eet of glas is used in a glas -rein f or ed lamin at e it

sh al be recorded a s Rev iew It em in t h e PCB def in it ion dos ier

NOTE Two sh eet s of g las rein f or cemen t a re specif ied

t o mit igat e t h e risk of red ced in sulat ion

caused b con taminat ion Th is is also specified

f or lamin at es f or clas 3/ A in ac ordan ce wit h

IPC-6 12 Ap en dix A In case a sin g le

rein f or emen t in lamin at e is used, it is

recommen ded t o implem en t ot h er me n s t o

mit igat e t h e risk of con t amin a t ion in lamin at e

IPC-4121 pr ov ides v arious pro ert ies, such a s

resin -t o-glas rat io, f or core lamin at e

con st ruct ion s

d Th e in sulat ion dist an ce as-desig n ed betwe n two layer in rig id lamin at e

or prepreg in Z direct ion sh ould be in con f orman ce wit h t h e values f rom

Table 13-7

NOTE Th is t able specifies a min imum dist an ce of 10

µm

e Except th e case specif ied in t h e 1 4.1h , t h e in sulat ion dist an ce a

s-man ufact ured bet we n t wo layer in rigid lamin at e or prepreg in Z

direction sh al be in con for man ce wit h t h e values f rom Table 13-7

NOTE 1 Th is t able specifies a min imum project ed pe

k-t o-pe k dist an ce of 7 0 µm

NOTE 2 Req uiremen t 1 4.1h specif ies micr ov ia layer

on HDI PCBs

f Double-sided co per clad laminat e wit h a t h ick n es as-design ed of 4 mi

(∼10 µm) sh al n ot be used un les :

1 t h e v olt age is les t h an 3 V,

2 the c op er foi thic knes on b t h sides of the lam inate is 17 µ m or 3

µ m ,

3 t h e lamin at e bat ch is s re n ed b t h e PCB man ufact urer t o h av e a

n omin al t h ick n es of t h e etch ed lamin a t e of ≥ 3,8 m il,

4 t h e in sulat ion dist an ce as-man ufactured is v erified b t h e PCB

man uf act urer t o be in complan ce wit h requiremen t 7 1.3 , an d

5 it is rec orded as a Rev iew Iem in t h e PCB def in it ion dos ier

NOTE 1 Req uiremen t 7.1.3f.1 is in complan ce wit h t h e

values from Table 13-3

NOTE 2 Th e n omin al t h ick n es of et ch ed lamin at e f rom

t h e req uiremen t 7 1.3f 3 can be re d f rom th e

CoC Howev er, t h is does n ot in dicat e wor t

-case t h ickn es a s men t ion ed in t h e requiremen t

7 1.3 Th eref ore t h e use of 4 mi lamin at e on

t h e lower en d of t h e t oleran ce bet we n 3,5 mi

an d 3,8 mi is proh ibit ed b t h is requiremen t

NOTE 3 Th e precau on s specif ied in t h is requiremen t

are def in ed t o prev en t a wor t -case in sulat ion

value of les t han 7 0 µm d e t o h igh t oleran ces

wit h roug h co per surf ace t re t men t as

2 t h e lamin at e bat ch is s re n ed b t h e PCB man ufact urer t o h av e a

n omin al t h ick n es of t h e etch ed lamin at e of ≥ 4,8 m il,

3 t h e as-man uf act ured in sulat ion dist an ce is v erified b th e PCB

man uf act urer t o be in complan ce wit h requiremen t 7 1.3g.1,

4 it is rec orded a s a R ev iew I em in t h e PCB defin it ion dos ier

NOTE 1 Th e t h ick n es value of t h e requiremen t 7 1.3g.1

is ≥10 µm

NOTE 2 Th is v alue specif ied in t h e requiremen t 7 1.3g.2

can be re d from t h e CoC I does n ot in dicat e

wor t -case t h ick n es as men t ion ed in t h e

requiremen t 7 1.3g.1 Th is proh ibit s t h e use of 5

mi lamin at e on t h e lower en d of t h e t oleran ce

betwe n 4,5 mi an d 4,8 mi

NOTE 3 Precau on s specif ied in th is requiremen t are

def in ed t o prev en t a wor t -case in sulat ion

value of les t h an 10 µm d e t o h igh t oleran ces

wit h rough co per surface t re t men t as

in dict ed in Table 7 -2

h F r in sulat ion dist an ce in Z direct ion of a lamin at e, t h e min imum

project ed pe k -t o-pe k in sulat ion dist an ce specified in th e req uiremen t

7.1.3i sh al be used

i Th e min imum project ed pe k -t o-pe k in sulat ion dist an ce sh al in clu e

t h e t h ick n es t oleran ce of th e lamin at e core an d t h e ma imum rough n es

of co per surface t rea tmen t

NOTE Project ed pe k -t o-pe k insulat ion dist an ce is

specified in Figure 3-1of P C-4101

j I avaiable, lamin at es sh ould be clas D in c on f orman ce wit h

requiremen t s f rom t h e IPC-4101 e cept t h e cases specified in t h e

requiremen t 7 1.3k

NOTE 1 Clas D guaran t ees a min imum project ed pe k

-t o-pe k in sulat ion dist an ce

NOTE 2 Ty icaly used mat erials can be u avaiable in

clas D ev en th ough th is specificat ion e ist s

k In case ot h er lamin at e clas es are used, t h e PCB man uf act urer shal

calcula t e min imum project ed pe k-t o-pe k in sulat ion dist an ce in

con f orman ce wit h req uiremen t 7 1.3i

NOTE An e ample of t h is is sh own in Table 7 -2 f or

clas C lamin at e an d common ly used co per

prof iles

l Th e PCB man f act urer shal defin e lamin at e a n d prepreg st yles an d

amoun t t o ach iev e t h e in sulat ion dist an ces as design ed b th e sup ler in

con f orman ce wit h req uiremen ts of t h e Subclause 13.8

NOTE Th e sup ler is resp n sible t o design in sulat ion

dist an ces required t o me t desig n v olt ages in

con forman ce wit h th e requiremen t 13.8.2c