Z80 is VI XỬ LÝ

Z80 Instruction Set Z80 Instruction Set Structure of Instructions Every instruction consists of an operational Code (OP Code) and if necessary an address part for the operand(s) Z80 OP Code 1 Byte (ex[.]

Z80 Instruction Set

Structure of Instructions

Every instruction consists of an operational Code (OP-Code) and -if necessary- an address part for the operand(s).

Z80: OP-Code 1 Byte (exceptions: in OPs using index registers

the OP-Code is two bytes) the instruction set is not orthogonal

Operand(s)

(A): contents of A, op: binary operation, : transfer, A: address, R: register

Z80 Address Modes (1)

Implied

The instruction has only an OP-Code, the register is "implied"

in the code

Ex: CPL (Complement A): A  ¬ A, OP-Code 2FH

Register Direct

The Instruction has only an OP-Code, both source and destination registers are defined in this code

Ex: LD A,B (Load A with contents of B): A  B, OP-Code 78H

Register Indirect

The instruction has only the OP-Code, the destination register is

defined in this code and a 16Bit register containing the address of

the source operand

Ex: LD A,(HL) (Load A from address contained in HL): A  (HL), 7EH

Z80 Address Modes (2)

Immediate

The instruction contains the value of the operand immediately

eg LD BC,1000H: BC  1000H, Op-Code 01H 00H 10H

eg LD A,1FH: A  1FH, Op-Code 3EH 1FH

Extended (Direct)

The address of the operad is given

as part of the instruction

eg LD A,(1000H): A  (1000H),

OP-Code 3AH 00H 10H

OP-Code

OP-Code m

n m 8-bit operand m 16-bit operand {m,n}

OP-Code n m

n m

operand address

memory

Z80 Address Modes (3)

Relative

The address is relative to PC

(only for Branches!)

eg JR 10H: PC  PC + 10H

Op-Code 18H 0EH

OP-Code offset

PC next OP-Code

e = x + 2 OP-Code (JR)

memory

x = e - 2 next instruction

PC

PC+2

destination address:

(PC + 2) + x = PC + e

0 -126

+129

x: (-128, +127)

e: (-126, +129)

Hint for JR e:

Z80 Address Modes (4)

Indexed

The address of the operand is constructed from the index register

(all instructions with index registers have 2 byte OP-Codes!)

eg LD A,(IX + 10H): A  (IX + 10H,) Code DDH 7EH 10H

OP-Code1 dislpacement d sign extended d

OP-Code2

IX or IY

operand

operand

.

d: signed 8-bit (-128, +127)

Z80 Address Modes (5)

Modified Page Zero

A fixed address correspondence only used for the restart instruction

eg RST 20H: Stack  PC, PCH  00H, PCL  20H,

OP-Code E7H RST p: Opcode 11 t 111 B with:

Bit

Direct addressing of a bit for bit manipulations

eg SET 3,A (Set bit 3 of A to 1): A3  1, OP-Code CBH DFH

(SET b,A: Ab  1, OP-Code CBH 11 b 111B)

Z80 Address Modes (6)

I/O Addressing

Only with special I/O commands (IOREQ = 1, MREQ = 0)

Ex: IN A,(10H): A  (n), OP-Code DBH 10H

Mnemonic Operation S Z H P/V N C 76 543 210 Hex

ADD A,(HL) A  A+(HL)   X  X V 0  10 000 110 86

IN A,(n) A  (n) • • X • X • • • 11 011 011 DB

 n 

# of Bytes # of M Cycles # of T states Comments

Acc to A8  A15

Hint (A7, , A0)  n and (A15, , A8)  A

By loading A before using an I/O instruction the available

space for I/O-addresses can be extended

Sample Line from Instruction Set

Listing

Instruction Classes

• Data Transfer Group

• Arithmetic Group

• Logical and Rotate Group

• Branch Group

• Stack, I/O, and Machine Contol Group

• Exchange, Block Transfer, and Search Group

• Bit Manipulation Group

Data Transfer Group

OP Code

Hex Mnemonic

Symbolic Operation Description

78 LD A,B A  B place a copy of B in A

21 00 07 LD HL,0700H HL  0700H load HL with 0700H

DD 2A 00 07 LD IX,(0700H) IX  (0700H)

load IX with the contents of memory starting at location 0700H *

* Low Address (0700H) = Least Significant Byte (LSB) High Address (0701H) = Most Signifikant Byte (MSB)

Arithmetic Group

OP Code

Hex Mnemonic Operation Symbolic Description

80 ADD A,B A  A + B B is added to A, result in A

09 ADD HL,BC HL  HL + BC BC is added to HL, result in HL

Logic and Rotate Group

OP Code

Hex Mnemonic

Symbolic Operation Description

A0 AND B A  A · B Bitwise AND-operation of A and B,

result in A

BE CP (HL) A - (HL)

the contents of the memory location addressed by HL is subtracted from A, set flags, A unchanged

Branch Group

OP Code

Symbolic Operation Description C3 00 01 JP 0100H PC  0100H control is tranferred to address 0100H

30 (e-2) JR NC,0100H PC  PC + e control is transferred to address in PC + offset e

if Carry-Flag is 0

CD 00 01 CALL 0100H

(SP-1)  PCh * (SP-2)  PCl *

PC  0100H

SP  SP - 2

control is transferred to subroutine at address 0100H, return address is stored on stack, SP is decremented by 2

C9 RET PCh  (SP+1) *PCl  (SP) *

SP  SP + 2

control is transferred to address on top of stack (return address), SP is incremented by 2

* PCh/l: high/low order byte of PC

Stack, I/O, and Machine Control Group

OP Code

Hex Mnemonic

Symbolic Operation Description

C5 PUSH BC (SP-2)  C (SP-1)  B

SP  SP - 2

BC is copied to top of stack, SP is decremented

by 2

C1 POP BC B  (SP+1) C  (SP)

SP  SP + 2

top of stack is copied to

BC, SP is incremented by 2

Exchange, Block Transfer, and

Search Group

OP Code

Hex Mnemonic

Symbolic Operation Description

D9 EXX BC  B'C' DE  D'E'

HL  H'L'

exchange of primary and alternative general purpose registers

ED B8 LDDR

(DE)  (HL)

DE  DE - 1

HL  HL - 1

BC  BC - 1

load location (DE) with location (HL), decrement

DE, HL, and BC, repeat until BC = 0

ED A1 CPI HL  HL + 1 A - (HL)

BC  BC - 1

compare location (HL) with accumulator, increment HL, decrement BC,

set flags, A unchanged

Bit Manipulation Group

OP Code

Hex Mnemonic

Symbolic Operation Description

CB 61 BIT 4,C Z  ¬C4 * test bit 4 of C, set Z flag

CB 74 SET 6,H H6  1 * set bit 6 of H to 1

CB 97 RES 6,H H6  0 * set bit 6 of H to 0

* the Index at the register denotes the bitpostion in that register