proceedings of the 5th international workshop on reconfigurable pdf

Fernando Moraes, Leaulo Soares Indrasiak Monfoed Glesner Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling onthe Power Consumption af FPGA -based

May 17-19, 2010 Karlsruhe, Germany

SNCIT 3

Sách có bàn quyền

Michael Hubner, Loic Lagadec, Oliver Sander, Jũrgen Becker (eds.)

Proceedings of the 5" International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC'10

May 17-19, 2010

Karlsruhe, Germany

Karlsruhe Institute of Technology KIT SCIENTIFIC REPORTS 7551

Proceedings of the

5 International Workshop on

Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC“10

Report-Nr KIT-SR 7551

Umschlagsbild:

‘Wikimedia Commons Fotograf: Meph666

Impressum

Karlsruher Institut fur Technologie (KIT)

KIT Scientific Publishing

StraBe am Forum 2

D-76131 Karlsruhe

wawuw.uyka.de

KIT ~ Universitat des Landes Baden-Worttemberg und nationales

Forschungszentrum in der Helmmottz-Gemeinschatt

ReCoS0C"10 Reconfigurable Communication-centrie Systems on Chip

Mics! ober, Karle osu of Tecnolgy, Kats, Germany

Lote Lage, Users de Breaane cident, LabsSTICC Bes, FRANCE

The fh edition of the Reconfigurable Communication-contrie Systems-on-Chip workshop (ReCoSoC 2010) was held in Karlsahe, Germany fiom May 17th to May 9th, 2010

ReCoSoC is intended to be ä periodic annual meeting to expase and diseuss gathered

‘expertise as well as slate of the art research sround SoC related topies through plenary invited papers and posters Similarly to the event in 2008 and the years before, several keynotes given by internationally renowned speakers as well as special events like © tutorials underline the high quality of the program:

ReCoSoC is a 3-day long event which endeavors to encourage scientific exchanges and collaborations This year again ReCoSoC perpetuates its original principles: thanks to the high sponsoring obtained fiom our partners registration fees will remain low

“The topics of imterestinelude:

~ Embedded Reconfiguzsbility inal is forms

(On-chip communication architeewces

Mulli-Processor Systems-on-Chips

ystem & SoC design methods

Asynehronous design techniques,

Low-power design methods

= Middleware and OS suppor for reconfiguration and communication

[New paradigms of compuation including bio-inspired approaches

We also thank the Intemational Depsrument for offering the providing the Hector Lecture Roam” for Use conference,

Oakland Universiy Universi of Lille ENSSAT Lansion Tallinn Tehnikadliboo!

cba,

Tu Den

TU Darmstadt Fraunhofer OSB University of Ulster Techni

TU Dannstadt Karlsruhe Instiste of Technology University of York

Universite de Bretagne Occidentale Universiti Heidelberg

1 Universit Mnchen

XHinx lạc NUI Gaisay

Ki TEOM.Lyon Eneson University of turk University of Bretzne Occidentale UERGS

LIRMM, Montpelier Universitat de Valen EPEL

esr Insite of Technology LIRMIM, Monipellier

Universiy of Turku

Universiteit Gent LIRMM, Mompeli:

Université de Cery-Pontoise Techlogical Educational Insite of Mesolonghi Universitit Stuttgart

TU Darmsiate

Germany France Netherlands Germany Germany México usa, France France sonia France Netherlands Germany Germany NonhemIrlanf Germany Germany Germany

UK France Germany usa, Ireland Sweden France Sweden Einlaml Fence Brasil Ennec Spain Switesrond Germany France Finland Belgium France France Greece Germany Gernsany

‘Table of Contents

Session 1: Multiprocessor System on Chip

| Selfaaptve communication eotecl allowing fine ting between Mexbiity and

performance in Hemozencous MPSoC systems

om tissu, Gabriel Marchesan Alma, Sameer Varyan, Pasa Beno, Giles

Sau

Instruction Set Simlaior for MPSOCs based on NoCs and MIPS Processors

Leandro Molie André Rodrgues Fernando Moraes, Leaulo Soares Indrasiak

Monfoed Glesner

Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency

Scaling onthe Power Consumption af FPGA -based Muliprocessors

Diana Goshringer donation OBie, Michael Hoole, dusrgsn Becker

Session 2: Design-optimization of Reconfigurable Systems

Novel Approach for Medeting Very Dynamic and Flexible Real Time Applications

Ismail Keatal Fabiredatne Ghagl Berrand Granado and Mohamed Abid

[New Thwee-level Rescuree Ma

Recontirable Devices

‘be! Belaid, Fabrice Muller Maher Benyemaa

smtent for Offline Placement of Hardwate Tasks 00

Exploration of Hetorogencous FPGA Architectures

Umer Faroog Hasan Paves, Zid Marrakech and Hobsh Mekrez

Session 3: Sel-A

tive Reconfigurable System Dynamic Online Resonfiguration of Digital Clock Managers on Nilins Vitex

Vitex TePro FPGAS A Case Study of Distnbuted Power Management

(Christian Schuck, Bastion Hacer Sirgen Becker

Practial Resource Constants for Online Syrhesis

Stfin Dobrich, Chetan Hochberger

ISRC: a runtime system for heterogeneous reconfigurable architectures

Session d: Fault Tolerant Systems

AA Self-Checking HW Journal fora Fail Tolerant Processor Architecture

Mohsin dmin, Camille Dion, Fabrice Montero, Abbas Ramazan, Abbas Dandache

‘A Task-aware Midalew are for Faultoterance and Adaptivity of Kan Process Networks

‘on Netwerk-on-Chip

Onur Devin, Beka Diken

Dynamic Reconfigurable Computing:

the Allemauive 19 Homogeneous Muldeores under Massive Deest Rass

‘Monica Mogatiaes Pereira, Livgi Care

Session E: Analysis of FPGA Architectures

[An NoC Tratfie Compiler for efiient FPGA implementation of Parallel Graph

Applications

Nowhilss Kupre Andre Detlon

laestigtion of Digital Sensors for Variability Characterization on FPGAS

Floreat Brugwer; Pascal Bevo, Lionel Torres

Investigating Self-Timod Cireits forthe Time- Triggered Protocl

Marin Ferner

Fist Evaluation of FPGA Reconfiguration for 3D Ulnssound Computer Fomoxtaphy

Manthios Birk Clemens Hogner, Matias Balzer Neate Renter, Michae! Finer,

ienaen Becker

Session 6: Security on Reconfigurable Systems

ECDSA Signature Processing over Prime Fields for Reconigurable Embedded Systems

Bonjanan Glas, Olver Sander, Vital Stacker Klans D Miler4laser Jurgen Becker

A Secure Kep Mashing Framevsorh for Access Systems in Highly Mobile Devices

Alexander Klann, Benjamin Glas Muavos Wachs, Jargon Becker, Klas D Miller

Session 7: Reconfigurable Computing and Recontig ble Education Special Sesion

‘Teaching Reconfigurable Processor: the Bisiow Appraseh

Lote Lagadee, Damien Picard, Prre-Tves Lacs

Behavioral modeling and C-V HDL co-simulation of Nenwar-om Chip on FPGA foe

Education

© Killian, C Tanougast Mk Monteiro, ©: Dion, A Bandache, S dewanonie

Experimental Fault Injection based on the Protatyping of an AES Cryptosystert

Jeaneopriste Rigaud, JeanMax Duerirs, Mice Agovany Brano Robison, Asia Ta

Poster Session

Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations

Ming La, Zhonghat Lu Wolgang Koeln, Ae Janse

“inning Synchronization for @ MuliStandard Reoeiver on 9 Muli-Procesor Ststem-on-

chip

Roberto dvoid Fabio Garcia and lars Nurmi

Mesh and Fat-Tiee comparison for địnapiesl reconfigurable applications

Lilove Devos Sehaston Pilement, Dail Chiles, Daher Demian’

Technology Independent, Eaibedded Lexie Cores

Unliving svnthostable cmbedded FPGA-cores for ASIC design validation

Joacim Knableis, Clana ischendors Er Marlen, LincR Howtet

A New Clisat Intsrface Architstre forthe Modified Fat Tree (MET) Network-on-Chip

(Not) Topology

Aldethaful Rowiraowe and Mubwommad FS Elvabua

linplementation of Conditional Execution on a Coarse-Grain Reconfigurable Ary

Fabio aria, Roberta darn, Jara Nurmi

Dynamically Reconfigurable Arhitotnes for High Speed Vision Systems

Omer Kise, Peer Lee

Viual SePC rhệ-hardening fo satlite applications

1 Barrandon, 7 Capitaine Lagades, Nedhdien, C Moy, 7 Monedre

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A Self-adaptive communication protocol allowing fine tuning between flexibility and performance in

Homogeneous MPSoC systems

cal Beno, Giles Sasi

emi Bussevil, Gabel Marches Nida, Samssr Vợ:

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in mowaays MPSOC, task migration tehniqes have Been

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‘se Tk 11] which ase an suagon fr ena Ti ast

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TU, provides simple packet sieing nctwork wal uxiane

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“astral sew of he NPU i depict in Fg

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andthe prcesing lage The Network layer i esently 3

Tàn reing expec OXY Poin), The poor Ie

Js bined on a simple an compact RISC micropono it

ate memory and few periph (a timer, a interop

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fartme malplesed execution of mali os (13

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she Hermes Networ-onchip [10 The igiweiht open

by te RTOS of Steve Ress (14, Despite Beng soa (5

K) this Keel aes preemptive schng heres ks a

ko provides thom wit asst of communion penis

tat ae pasented later, The OS Hs capable of youn ak

Inating apt dyamic ak migration,

B, Selfadaptive mechanomt

“The platform is ened to tke deine tint rete to

aplication implementation dough wsk pacer These d=

sons are taken Ina ull decenbalized fashion as each NPU

{Sendowed wih equate deins sưehihies E=h NPU,

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‘cae to ps or atta tasks which oats in eapestely

pli or seizing the conesponing sks eecition

Mapping decisions ave specified onan aplicationspesiie

basis 2 dented operating sytem service, Although the

fre ponuble Thee metnct are svmlabe the romaping

oli) Tor aking mapping de lione

1 FIFO guess filing ks

+ Thú distance

PU workload i messured athe amount of tine ws

fF hop a packet reas ogo through during a communication

ene wo tsk, Asthe Network sete ea 2D mesh, is

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ps wero For more information aout the isk migration iis, we ive the reader to read ov previous pape 13)

“The Network of HS-Sele i as on the NOC HERMES 110} provides ow aren oserhen packet mtcing network hanks ta simple Xwhon Fring dlgofBm Only 0 ele

‘ue seeded to encupslte 4 HERMES packet one for the Scoder and cet sess andthe second for the suber

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In the sandal usualy ual ltr enapsulaton mode

4 layers of functionality ate provided the lak ayer, the Treme ye the transport layer andthe ppt ye (16

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Sn soltvare = a6 OS series ~ahing the conept of TCR To cep eompaiiy tween HERMES and I, XY adense

OF HERMES hive boon stcally mogpod 1 TP address Transport ler was adapted to provide the tuc nen sẽ

‘TCP and UDP: Ue aati of prs have heen ase, een

hs been optionally made pode reliability in nom ehble reworks, As this network cam be considered a reliable, this feats fae nt been use but Himes the rowel tore are 2 shows the dierent protools implant in HS- Seale A RAW proto, simply wing Hermes nhúng aye

fd wih packets dey gent the OS hs Bee ade provide a base rte of the Bandi When 3 tsk no 2 ece the ieniy ofthe commision cans When the `

A ile pe of communication

A homogensoos an regula plato ike HSS ha

aplication dota move senee tan heemgencus ppc

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farmers fs to provide bth gener and perforce

‘We can sings Geren oe of communion in HS

See

+ Cunmticaton eaween uss rare, ide the

+ Communication between tks Iternide Ls between

tạo ileent nes

Service messes provided by the Operating syst of

+ Exception messiges provided hy a task to an Opecting system request a sevice

‘The opting stem provides some hase ptives of MPI

(Mesage Passing Ines Usk cates communica

For internode comico hts asks that pots

is move completed Figure 3 rpresens te cnoep of Be

robo Hint, weed opens conection betwee te oo

restr task, As RAW proms oes nx provide ny pening

tr else of conection, the TCP ree sep hank peo

SS wie Aer opening, we need to tanser te infomton

‘ihe bet peormince we have, wth mo noe of Goal

otcolswaupucn fee tak sb the Operating ster)

(Operating Sytem hs to check whee the meetdng tt

fon these ne abd

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Service nse relabiliy of he Network For ti pups,

caer

Bask Miran Communication dring ask migration rnin sue can be expres a olows:how to exp the manor perfomance hrng the tamer fk fren 4 NPU to soho, Without

Sf ckets i clove the communication durin ask igrton

‘Although Địc mebad cán be cemideel ae Ki, the pening and lasing proto! plus te loss ofthe eononction

“To ener no Is of packets dering mation, We have to focus or ateton on (Ho points: Sk We nea t chúc the secepon an the ere of the phe So tat n paket ae

‘hey po f te khong hoc Thư fears are ain part of

‘he TCP proc ro he Mea i alo ete owe TCP ena

‘he cali of te system

ure 4 shows the diferent sep of the communication rng 3 ask mipration hee, te eee, Before the mig

‘in, the tsk which want fo migrate sea message 1 the {asks communicating wih isl, avaig he Đạt ants {© coramunicle sod 3ã sưích tế counienion í TC eves at east ope TCP packet fom every sent tasks (2)

Ir packet aie doring mignon hey ae rede tthe sow NPU ich sien he uk 3) if he ak ad the Packt comued ao the pak i sted 2 fos ad Shaped when the fief, When the migration ie some,

‘he sk sends a messige fo the tsks communicating With {0 updates postion ant switch iy UDP again, As TCP provides woreritg if TCP packets aie aller Mca of

V, PraronsiaNee oF rk abra-aDarHtvE PROTOCOL

“The int purpose fat we es nfs om nob con caton protocol the bandh Indeed he Randi has {o be tuned wo ht the purpose of the chip gure 8 shows the anda for the to protools able, company them

‘nade wt diferent sizeof pockets and with ie amount

‘tdi nach ode menses the me tans,

compute te bandwidth, The RAW communication ca ahieve

nen bandh re tan 0 KB, en Be UDP cat

sche S50 Kat es and TCP 0 Ks, The perfomance

cm keveen RAW an UDP, less han 1, panes the ef

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Iara bua 30% xnale than RAN contnoneddon hi

this peleee bạ oor developed tobe wed on precise fe

‘sommanicaton pres ike OS messages, opening or losing

ft coneton oe tsk mignon,

“The xem pone red Py foe $s te anv

‘ariations sorted to the segmentation ofthe dts and the

“snot of data rans, in RAW he vaiaions sre quite

fo ty eat 9 ap to 48% for he UDP apt TCP pret

‘The low Kandi bined with ally smal pockets 100

19200 bytes can be explied y the fact hat epson

‘UDP and TCP i buge around 80 bytes, which aks the

` "

Fags posh hanhore vui ma capi of 9 NPU i

tho Jon orgie the whole packet inne ck which makes

the operating syston on aechedulg vi s owes the

navi,

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4s really geyenden of the platform a hutare Hist, ie

‘mil intocce the overall pocsting tive Time t process

2 packet wil sary in fonction of froqaney CPU archecore

fr Pressing Ut design with the sion of dedi

[Nese encoderecoder for esanple, But in stare, the

opting can greatly wan Indeed he imam depends on

tắc ven me beeen wo rescheduling of be commis

thn procedure, Depening on CPU caved communion

procedure rescheduling Wil procee fess often, ad so the

puma wil change, Hence, et pcsgaph wl how el

Shows nih sratons wi a CPU in hare

B Peformance in charge

As the CPUs oth wed for communication dcoing ant

compan, sis ieresting to see the nence of CPU

saute

tage an the landeilh, Tiyme B chat the hand of UDBMICB samnanietist wien = for fan TCP an 6) in UDP =the CPU sin commenicuton only ode, ts ete 4s no ober ask runing un te CPU and when ~ Tor) m

le when the CPU runs a mjpeg decoder ised on 3 iee- Aependee sks The pcs ed 10 750 yes, a he

‘menses ae made ona TOMB afer, We ean ti Bề '50 of ts nominal wale, This rection can be expsined by ‘he heavy compuation need o procs TCP ov UDP pocket

‘wit general purpose CPU like those ied i 1S-Sl veh ao the sllvare iplmenaton of TCP cnplebon and decision, responsible of towers fe nt had tice bee: as this protocol is considered «be used foe Sci purose communication, which can Be consigred 35 Jnirproces cormmoniation, te tieaphpe ise 3 cea Ise In his case, hs implementation semis more appropriate thn a havare one wich would consure ars

“The co pi stressed hy Fre 6 isthe me babeeen

‘wo rescheling of he communiaton proto The Opes sng System in HSScae uses simple ound robin estedling

‘wih ned sie tine she ealled eke: the roche peo

Fr considered se task, the ine to xechele vi vay im function of the los! of the CPL and of the sleeping tine paruncer Ths parameter th non cty keo hề inthe rund bin te Te cane tied rm | Hck, wick orrespon teach task Bing rescheduled only once Between {wo commaicaton rns to any potve nurs,

pure 7 Haante thi principle of cheng In) and) he CPL isin comma only ei tie

se, the rescheduling should be a oflen as pose,

“AM ng ah, lke ib) tae) std (te CPU &

in wy tae moe: ins sae, the revchedng ime

Si inuene the enmnpwation time, bu lo he anh

In term of compotion fe, the Fa of ie spent on te

“=erbDTf where eke mame ch and he hen the Tế

{en of bandwith al he vriatons aren more noone

ferns he urbe of Gok P we ave a sition wee the

Công pet eee pray ia Up 7 esa (sealer

“To where dhe average Hime peat Wt receive sige with Fer

ols than witout Tis snton can he observed neue

(fd ete te bap sige with 10 ks han Wath

tune aeurely deeming on the application the CPU

fava arable ea dytanically wade ibe neeheille

‘he cormuniaton, denny ot he aceang re thề

ily and adaptability «6 face the new challenges raked By

Cechoslogy shrinking and computing espemert For ths

purpose sy of ea savor depen des kt

{god oad haring sey

"Tis acl dosries an slp sommaniation proton

prposaly eto fase dye sk mignon tes ns

{o deal with the sopretroniety of sek nade with proving

Sequential Fetoor of eric codes, Por thi psp, ths

roto! hs ee hut súng inspiron of TCP and UDP fen

{trex Thanks to ter isovcally proved eli, senstion

arn tk grat shee paved, Falls prfrmance

Inset show the frst f sch prone ith realy sal

‘vee! foe UP tanec,

Instruetion Set Simulator for MPSoCs based on NoCs and MIPS Processors

‘Lean Maller!, André Rodrigue’ Ferrando Moraes, Leandro Soares Inn ake, Manfied Gleaner

" Darmstadt University of Technology - Institute af Mictostectroni Systems - Darmstadt, Germany Faculty of Informatics - Catholie University of Rie Grande do Sul - Porto Alegre, Bra

*Depuriment of Computer Science - University of York - York, United Kingdom

Em

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ot lọc aca, narcton Sr Stators (SS) f

rmination secs a some of he mart togered

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for inting ISS compote seh the MPS proceso

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compere since he rls fe nl Pente D

fe'200s [I] Sime tia, processor taoutstrs lạc

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systems a unique complex aplication oes ewe

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While communication lunduetre based on bas have

eon sulin for mupocesor spss 50 Tt the

freee of hero cats aml dita ante ns

this purpose Netwarks-on ip (N9C3)bave ase a6 2

‘Soll solution ofr ints of sur fc The te ofa NoC repress no et changes othe developer

SI the amples gHewom Bởi À con và tc

ty the Matoud Site Uaivemiy [3 Thi ISS mst onfeoed te RENATO NoC model J) which bac

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‘the Noa he 88 the Pony I [3] develope by

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‘Govt this wok Related Works

‘Snes the mast porn oration ofthese works {ads the work proposed in Ais apo presented in

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‘veloped in C++ and won wrppod to sonra with

‘hs MPSOC sioulted ia Systeme The platform allows wig mute pal uC Kernels om fepenont 'STMSC [7] ses Oponlise1 200 peocesors enn hough Wishbone hus Debugging is mplerent with he

(OR IKsin ISS, which inplenemid in C nghe TE<

‘Open yet ru yet spore

TIVE [8] suopos sev processors and teens

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ARM pete etetie a heitelglsspeniag ston

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proceson rs reported io be AMBA among ARM

Proceso ant Spots none nce proses

SoCs [9] i a projet developed joy by tt

Inborweies and & indus coempanes coals

‘Snlation tel fr provesor re Team 40d

Te comllers, cmb) and external memamV

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‘cates toc it exchanges daa heen oes by

‘ine he mai protvol ofthe NOC, terfre no exe

Table 1~ MPSoCs that hao tools for debugsing embedded softwar,

3 Background

‘This sein reigns the eid infastvtue to build

our MPSOCsilstion envionment

3.1 Ptolemy 1

Muley (5) a frework developed by he

Dpacinent of Elec aging and Comauer

SSeheecof the Univer of California Berkley apd

isimplenente Ja The hey sonesp behind Paty

‘Sompoosne, inthis work ony the Discrete Even (OE)

rod of omption was uses, fers re vale on

is times sonata an event What an actor ccs

seven, stad and retion nigh oi whch

"Ha change the internal site of te stor ano gece

ensicns The events are paces chronolsealy (8)

3.2, MARS Iss

[MARS [5] s MIS Ireegior Sd Simalsuc (159)

(be exec ty command ine Graphical User Incite: MARS was developed by Peer Sano at Xetsth Volo or he Miscou Sate Univers ond

is viten nie avn Sat a boot chế MIBE 52 ndeuedan sec là vi se abou 30 uct Äafuelins oự iauci sano, 17 egal cts fercomsle and le UO snd21 scl er,

33 RENATO NoC RENATO Not (4 ác đodopel túng the Poleny I Tamekoic and Re hehuiar and ting Sons sec tse on he HERMES NOC The asc elect of te NOC Ss five hess po rater, whch eanrecte 6 MEN te, The router enplgs «XY wing lgoridroubdrbin ation agai nd pt tars tac np por

suing tol ellot No Sep [LT NoCScope oes inpoved cheerabiy of RENATO qoutes tod overall onuees ise Senet sopos ane cute asl s1eaing te eẹ lọc and abo Ba spt, poe oncimption, baler veugwdun mọi mưc' ngạt {ral en te an pout pis cama

Si w 44 | —@ —

s⁄“

Pe Pe Fe

) 10 20 Processing Element (PE)

4 Communication among processors

uligeecsioe ISS Fie Usa ck gram of the

‘tem that wil eso in th es ssc ogee

‘iplanaton of ach somone

4.1, Provessor to NI

In the cumeot version of tis work, each proeson

sxccutes the AMPS essenbly code of one tsk of the

Sppkshon Comicon hetesen asks happens By

te fst sted fn te data tery of the proceso Tt

healer of the packet is composed by the odes ofthe

fags rvter whee the pressor 6 coc ond ths

"The send pct subtest ah tế se ít se

pocket sore in De (nen 10 4 fester and reds

Stoo else he erp ber is aval in he NL

Tit to the NL The process of"yeading”a it fom the NI

ses the Inston "ote Hom soproessn Uh

‘ste the proven af “ening ft to the NI anc the

¬- `

Figure 1 Bioek g3 ofthe proposed mi —— 88

42, NH Noc {Wish the packet strain the NI op ole, the NI

‘hs flow contol prota nase by the Ne a sig he Ang lye ston te NOC wl Boing exceed by Peery

43 NGC tø NI

‘When pakes ae bsg resid on tbe NaC ia the i.a dren boter ipa Bure) se thos allowing ural sending aed tong of packets, The rscving oF

‘NC and using i asi las sete De NOC rel

44 NE to processor tule cfthe Ni the NI knathet specie tg to the proce meaning that ne pacha has artved The MARS ISS wich an excowig ek sues fs uN

fd recewes the itemipion im the form of 3 Jit

‘recon The sandan rode fr hưng cteelom 1s Ses By Ue ID af the specie exception he cnet scepton i fu out to be Ihe “new smewage on emerk csp The spsiic sbrouine of is ception elcid, This sortie rin reds he

Soprcenor Oo) acto ho ead eich of the

packet Ale the consplcte poke và fea Pu the Nan

‘ove inthe peoves's meter the pet's conn

ie restr an cat ow coioucs wih he exes

Dowsing eda hws cv

5 Synchronization

‘The stirred slaion in Java to comet moxe

than one MARS 1 tthe NC i a rete a now MARS

teste opt for etry row MARS fase i the

NGC However, tis aemarne Fed df te at hat

MARS tas boca gan wing several te cases,

states nã tnehofs' AT af le an eafe, ch

The memory an the register bank are declared + so

‘Therto,shene ts fo mM Phúc hah one Msn oT MARS concurrent inode single Jove Viral Rhine

enn, which il lad wo expected bata,

‘One posible workaround for hs pole for ich

MARS tnsooe in det JVM Jo doc lọc st”

the etchang of essgastetwccn ret IV ony

posible by ning APIS such a6 Java Remote Mend

rscune te poblonais Mate tus an wake tem

tig Tor ch instance Hawever, th sain was ls

ot epi comenng the linge mame of sie

NWruon of MARS woul ao requ thse means

A bet stint instante slit Cade,

‘one for eck instance of MARS 4 be ade, This works

‘esse ste lent in Java i wo om nthe

Sones of «Clas anger tetre thet clement xi

feu inrere wih the ale hotancen uf MARS alld by

thr ChssLoodes BY sits this appoaeh, te sk of

‘ichanging messages Retwcen the MARS isu ad

Soresonting Naso Booms trial and can be done Siniy injecting Nest when nsuniine MARS

ane he NOC ave ecmidered ae ieee end by Jat,

“5d thị would rite es aigwidik Based wo and

"0ƒ inslvsx te mangin te line canenius floeel

W NgC As the maim gol of ss sa prods

xia alpotins, suming 3 aue smlnhen Fe 2

pecsnt pit of te most impor eves asc

Ds ogee rte Otte a Fare ant

MARS Z5 chngtel tử nh 2L, No cư De

‘Seth packs ote NI snot co (NI #1, exe sssplained ie Scion Teena he tele Mis oF packet no st the Ges 2 sepulation eyes, a he Hist of the pocket at ine S086 his sang behavior Splice flowing results: (1) MARS 21 treat vay cxeced 0 ines concenty 16 Polemny the Seren ics 3003003 sn 30865 (2) MARS te sn

3 am tưng 2 siaton cytes of Pale (2) MARS

‘ive wis not elle gain dog $3 simulation eyes (Gt 3098)Rebacen ns 2087 ane 3109 each ko he packet was sn omstatly every 2 simulation cles mn eho sequal tothe veal HERMES Not that nels 2 sock eyelet astra Musing hands ow cool Berwsen me 3712 and 3156 al thefts fom the pckst swe ase the No to NU#2 au espn! in the cot vesin fas ao posse to delves each Mt rey Ds cytes, Dut salon eyes i Hs

ne, Atte 3120 is psi ows that M2 dred She ft pst fi immaitly to MARS #2 cen

Bes 3166 and BI The reat of the bloat Mis were

deltsrel to MARS 42 2: deeb in Section 8 Hee

fg Tela comsat paterson the surel possible {0 se ha the dla Uns id ao

sa St lle of runing mull ava wth no oper

‘yt,

6 Conclusion and Future Work

‘This work resorted an ISS for mekgresior stn

fused othe MIPS proceso fa hin work the RENATO

NaC model wes conc to cw stances of he MARS

TSS ands rol? applications ned ơn moe then oe

peocenor can he emi debugged wit the peste

Sppooch The sua impact smbatnn the wok

Sim à more wails muliprocesigy ster made

‘Somposed by computation and cammuncaton, Tit urs reading ateacy between process

{spot to be afte ine cael ni orto

‘ae spool lens gee ast (1 back anna the

Ding eye ofeach assembly nstreion fom 2 ra

MIPS prover te MARS, (2) ald extassncvonizaton

No ws dlsgs sn preset in (3 Fare works wil

bereled steps | and

{1 Vollmur 6-and Stndoson, D-°A MIPS sry lang

(i) neon US! 0 02M Arc Ges

1) Elen Js Jamech I Lee Et, Je lin X Labi 3 (6l BeMm Lị BemugA Dị Boghok Ay Meni F IỚỊ Balbelem 5: Eeoemame etn bsnl

(a), Cen Ds Sheng, Ws Calon, Su A; Lene,

(oan, Nee A; Ma, APs, i

gel mst nl Deb of MPS Sec i ROD,

{i anos Ave ee open

Impact of Task Distribution, Processor

Configurations and Dynamic Clock Frequency

Scaling on the Power Consumption of FPGA-based

Multiprocessors

Diana Gockringet Jonathan Obie

Fraaboter10SB Engen, Gomiany {iin goctsinger jotta obs as ramhoferá

Abarat As only the caer segue RaeleIAHh s5

‘etter an is iafienes othe prforoance a he tte

‘dani os cna, fr uae ee

Imation stems in Ni FPGAR med rantine

pine arta for analving the perarece er poner

eka Powe Canumtn, Mawar Socom

‘pon Pag, Dad al Renato

Peandebahle Rmclom Muảs tneổ ức ERGA-kuel

system derstopmont, open at hie sigh spe which on oy

Hay he ounape bye er Heaps fort are

tihneie aeke ik Giver ar, sot Meme which

Torarthcde books, also som processor cars prsie

Tesuiemnes ofthe application to be rls! with he syst

Eqeily Nin offers wh the Micriare SofIP RISC

prorensor {2 vary of pos for character the care

Frias Those options ane wmongst stews cache

hunagement unit andthe number of pipeline aac

‘ore as mltprocesor on ane FPGA, Evry oplon nuy tam

‘Mich! Huebner Juergen Becker

I, Karate asin of Techaoogs (KET

Kosa, Gea twice msbner, becker fakiveds

he adsted oil an opi prameteiation ofthe pocesce sore in claton to the trust appiaton For oampl, 0 Speste cache sie can sped ap the apie trend

Bi alo he pina arn af functors ono te two oes

Syston, THe examples sh the huge design space oy oa

patamcters for system adjusted leas toa melidimensonal

“ôn ai problem, stick not af Isat ven holy fmameable fy the designer lt onder toga exper

"elie ngs of poser pata non

the performance and powerconsumption of an FPGA-based

‘Kit stot pumice The esl of ach an vegan frst tp for devleping standard pein: for desienem sd

fa apptach Soran abusuton of he design spaces FPGA theo sytem design Ths oper present fe rss of &

Ta FPGA whee the parameterization of the processor is ob a Xan Views

‘alused tk tans of power comunptun and poonrance oreo, the vatying parton ofthe iret application Sestanos fh valid in tem of power compton tir Fixed perfomance For this puss to! ow for analyzing

<Gunp (VCD) fe fom the post plae at toute solani

te vodhiced The presented low erates to generate the st fume power consmpton exist fiom this level of Sisriction Asker op of tbe protease Sreriew of the impact oF puraneteraton to Ie power

nel

pris close by presenting the conlsion and ftue work Section Vl

HL RELATED Wonk, LOptimieton ofthe dynamic an sic ower cansmption

is very important especialy Tor embed sys, beaise

The ghen se Bates “Therefore, many researchers ke for example Menus st se power sores,

412 explored te ower consmpion of Kins Viol Px, Xilim Spantas "and Alt ‘Cycle! FPGAs They

‘sma the power consumption t delgrdime vàng hệ

‘commercial tools provided by Xai and Alters They faethe

‘explore the diferences Benen te messued and cainael

power conuryption for tese FPGAS Uecker et al (3

Expl he dflerenc between measured and estate Power

“consmpion forthe Nine Vitex A000F FPO Tahermor,

Tào) exploved te Bchavir of the power ensunytion, when

ting dame reconfiguration Io exshange the FPGA sar

‘ier works foes onthe development of own tos and

rode for elicknt power estimation a dxigptine ee

FPGAbsed stems Poon etal [4 present a power mov! to

“estimate the hams, hor! crea a Teka power

‘Sandie FPGA architectures This power motel has boon

inet imo the VPR CAU Han, He te tmmmnan

‘ensiy signal model [5] 10 determine sina ates Nhìn

the FPGA Weis et al [present an approach fr delgtdie

power estimation for be Xing Vinex FPGA Ts estaon

retod works well for onal How orn aplications but

ovo wll or combinatorial Logie Degalal ct [7] present

4 methodology to estimate dynamic power consumption fo FPGAhasd ste They applied thi methodology to explore

"he power contunpion of te Nims Spartan’ device and to

compare the exited rsske sth the mewwvel powar

—

‘A hse approaches Fc either onthe propa of new

‘stimation nolo el forestmating the power cosumption

1 desigmtime or they compare thei own or commercial

‘satan models and tool wih the real esurod power

“Sonsumpion,The focus of he investigations preset in is

pure to show the impact of paraetereaton of ID-cotes,

ere spiel he Micrlize aot processor which ifs

fr th ypntechet msnhone abe where Ihe ic re

‘onto! development fr power sstnabon "The noel eo appre i oes om te egies

‘ofthe rg application apd wo propose 4 dsp gute foe

Suy developer of prosor Beans renling guidance in how to desiga a syet to tw FPGA stems Th

chive 2 good aden? between perfomance and power

onan Toe 8 Erge ago To dam beh

Buiidlne tie impact of the Tequeney, dierent processor

configurations andthe tak dination in 2 procesto bse

‘sign is lnvesigted ip this paper for eiferetapplicaion

Scenario, To the Best of or alge, sii work hs nat

done before

HH, TooL Flow FoR PonteR MEASUREMENT

Xin provides two Kinds of tos foe power consusion

‘timation Xiling Power Estmstor (XPE) [a and Nii 3

“The NPE to is based onan ctelgfexBledL l reetex information about the suber and pes of ase sours the repr sent by the mappine proces MAP) of he

ii ot Tow Alertatvely toe se en manly et he Values for the number and type of wed esoures THE Iregienes edwin the des hove toe manly ty the user The advange of this method is Đạt resto ae

‘tained vey fasts The dsavantage tte res eo ery acu, epi forth aie power sonsunpn

“his ip Bec the diferent tgeing aes of the seals ae fot taking nt account Aso, i oul teal acct,

‘sent te sed on ths BAD oor and on he pot

‘pice a ote (PAR) sp which eters the sem ed For generating te barca She XPower to estates the dhnamic and static power onsumpten for suns, ire sober a he Ste mse be! the reste of = pt pas an ote TAR) Sula This talc te ean el mich more acct compared tothe XPE ts Bene the Fis placed and rowed sytem ‘ cosiered forthe power Sen Bu chen mọc Tngorank di He smut of the PAR system with ol oyu data hệ ogling rats he Sivas con be ext an se tin he pos sina Far esa the power contin whe XPower fol the lowing pat fice a eque: * Native Cet Description (NCD) Hil, which specifi the sie resources

+Phniel Comin File (PCF, which seis the design + Value Changs: Dump (VCD) fe, wich species he Slated ey rat of te niga

‘The NCD andthe PCE le are abind aR he PAR phase ofthe Xi splementtion lol fw The VCD fe enced by sgt Sulton of he PAR sign with Be Modem sat Da to the higher aca the XPower oa ws sad ere

‘Ase ware xia the per eonempin Fo sae

‘ith ne or two VieaBlye txeeesur, le hadvare il he

“often stele of te Sion sem ore deste Stine Sine Pr Sao PSH Fae dược {he oe dara fr dans por estimation wis Powe or

‘Generale (Senn)

“Tine Sinulion and Geeatn ot V€Dfle(MooeSm) awerEainmtollsXEmar

Air the sytem has been design and implemented

wid the XPS ervionment te Sige [1D] ool fas to

erate the post PAR ming simulation Modelo he syst

“TH simulation del ihe used to seated belavine of

the system sth the MovlSinsimoltr and to generate the

{VCD ie th last step XPower I sed la ea the VCD,

the NED aad th PCF feof the design and to eximate th

{Synamic and state power consption Care sto be ake,

Iecase ia aomal Xia implementation Now the stare

‘xcetales fe iegrated ino the memories ofthe acess

Ser the bisteam fas been generat When using XPower

Sn the post PAR simolaon the meres ofthe provesor tive lobe lallaized la an eave sep Ths means tothe

pst PAR simulation model, hers the simulated system havior and the VED ile would othe acct

IV Nove system ancunecrune

“The system srt ofthe dl provesor system shown

in Figure 2 Thee new components have besn designed nd

Imglenelei, cúc Virwai.iO,” the Bridge andthe

RRevanigurble Clock Unt, All thee componeis tnve bos

inegrated nto a ary forthe XPS too Therefore, they ean

bens an prsneteized ưng le gaphiol ne mierace

{GUI ofthe XPS woo, which makes dem easy ueBe xi

ther NPS sins

‘Vintage ete ha

“The Vinwal10 revives dats rom the host PC and en

reals back to te host PC via the PCI The VimaiLIO

Communic vite Fast Sipe Links (FSLs 11} wih Micutlace proceson (180 and i) nHÓ chammanlcdes

tv se i the UART inert Rao bas timer, hich

ned wo meare the perfarmance ofthe overall stem The

two processors communicate wih each oher ia FSLs ever he

Bridge component Depending e the il evel ofthe FIFOs

‘within the Bridge reconiguaton signa are Sebd te the

Resonfiguable Clack Unit The Reconfigure Clock Unt

reconigues the clocks af the two proceso led an Đề

reeonfigwation sigals issued by the Bridge For the un

Provence syrem, which is use for compar, the Bile,

the Recnfiguble Clock Unit BI and thee comtestions

‘tere rmoved ae show it Fun 3

“The Virwal10 is 9 wrapper around 6 diferent oes

"he fst mle Vgial1O , nhch sen dân Bi to HH and thon fo BIT hen recsves the auld ress i he Sine onder The second modules Vial 0 2, bik rts đấm an 4o HD, Resale ae only reseed ver HBL

“Therefore, BD sens ress Yo HB, which then send he results o 80 togeer with its own esti back to the Vinal

1 2, The hind mode x Vinan-l0 3, whieh sends fre data

oy Acres tsps paral obs process 80

nổ NI te same data Fly sends some dita on lo HBL Ale the encation of the rescvee, hạn BD a the HBL snd thei ess back othe VirwsH4O 3 The four Trolul s Vital 0 4, hic only eames one of te processors, e@ HBO De os ts module used in al processor designs, Fora dial-poceso design ised ta 0 HBO which thee forwards pars of te data to BI ARSE xcetin HB) sends is ests lo to 80, whi Frans {eestor the execution ofthe two processors othe Via:

10 4 The ih pode Vimua10 8, which sends the same

‘ati bd processors in pra bursts the eal oly

‘ie wBO, The sith mole Wial.10 6, eis very sm 0

VirwsI40 5 The only diterence is that it resives the

zlation sul om 4B sea of 0

“The modules can be elected in the XPS GUL via the

params ofthe Vital 10 component Other parmetes ht fan be sot by the user a he tuber of input and pet

So foreach procenor separa, the number of comin

input words and the size of the nage (ony for tage

proves applications

B Bridge

‘The Bridge module is usal for the iter prosessor

omminiciion It cassie tao asjachonoe FIFOs

‘ond by FSM to support a communicate via c bạo

‘iret clock domains ofthe proceso as shown Figure So's Bridge component contols the fil level of De lào

FIFOs IF one FIFO ts to nearly fil is assumed thatthe

ove, hich ead fm hs FIFO is 1 low Asa tes,

4 reconfiguration signal to increase the cack ate oF is

rocerorsond tthe Reconfiguration Clock Unit,

ge era sso he i

Âeeonfiumile Chết Vit

“Th infemal srs ofthe Reconfigurable Clock Unt

shown in Figure 6-H consis of two Digi Clock Manages

(DEM) [1] to Cook Ber Mulilesr primitives

{ISUFGMUe) [1] andthe Lope compan, which conta

the reconfiguration ofthe DCM

“The Loge component rssnes the reconfiguration sna

‘of the Brus component It tien sans te esoniguration of

the DCMT prmitne for the slower proses Tor túc

Taeealeurtin te xpsdiñe pons quovded by Xin fir

‘ymame reconfiguration of the View DCM primitive ae ‘ol Dating the configura press the DEM has to Be

Kept va ree sate fora minim of 200 e.g this ne

Interval the uit of ts DCM aze not sles ea be

sed Instead of sallig the coresponding processor, the BBUFGMUX peimive uscd to provide CLIN, th egal input lock oF the two DCM, 1 the procesor Whose DCM Is iter recengunton The BUFGMUX i a spocal lock Iulupleser primitive which assures, tbat no aliches coour, thos seeing to a difleret cock Aer the canfisuraion of

‘he DCM sash the BUPGMIUX is used suleh bat lạ the DCM clock A aerate woul he to sl the processor, hls is eock Beng reonigute Because 200 ms are quite Ting bee croety Gr eps poem aise Who each WO hs ew inp ame seve om xi amoa: this would sul ina Toss of np dt,

To peevent a lao, he contol logic will stop inereaing the lok fsusne i125 Mz fr this Mico

ve hen echo wich nthe ms eqoency sported bythe Niclas dts penpals orf is clock eueney ae been inca for ước cowsevdee tmev ÍẾ túc Fetonigration sgl i sl seed mening the processor is SSiP too slow then the DCM of he faserprovesor "eeonigued wo provide a slower lok te Est process

‘Aeraivels, instead of yam renlgwing the DCM, diferent output pers of a DCM could be wed 19 epee diferet clocks, Using seteal BUFGMUNeS the Silent looks would be welt The aantage i» faster

‘Sch ewcen diferent cook and he dawack shat no 5 tam diferent, clovks we possible as when dynamic reeoniguation is uaed, This wll be iovesipated fu

‘son

Ve APHICAHIOXSCEMAMGE

“Tne len pplietions searos were aso explore

‘he impact ofthe pocesor configurations, the ask dsbuton and the dynamic clock fequency sealing ơn the powee onsuniion of FPGA-isad processor stems The thee Sierem algorithms are described in deal io the next Sbsectons The Tes agora i the với kasan song signin calls Quist (13 consis of ft of branches

“ni saefeasoe The euhl sim n megspteeeovax cgodim called Nonmalized Squared Concaion (NCC) ‘hich consi of many arhrei peratons, ei mel and iid The id daodllm te a vàialet Sf 4 boinfamhale igor edled DÍNHƠN |3, vhệh consis of many ampadsem smlaidions sa subctons These sige

“vith thei iret got mapiemets vụ hrnee Comparators, molly dvi, add name kg [pode w wer gulsline of designing a sysem with a geod

‘ertrrance pr power adeal for aapectie application: By Comparing te algorithm requirement fnew aphcatons vith the tne example agora, he system emfgeatione oft Thôn similar example algo is chosen as a staring system Such guideline wo mit he desig space fs very import to Save time and achieve a higher tineo-narkee.Beeause Đệ

“Sliton nthe power estimation with XPower ate sexy Tme-comsuming_ Also, the shear generation to messe hề Performance of the application en the target hardware Srctvtre sine cannuming Thess lng design times canbe

‘Shorten hy staring with an appropriate design, eg the right

‘process coaliguratony good task ston ns ell lost execution rogue

Regoseo 0D,

AL Sorting Algorithm: Quits

Quiksont [14 is wellknown sing ago with

ide and cưng xin, sen st by rocaily

Partoning te fist sound 0 pot and soning the resling

‘iste eit sn sverne compen f © la lap)

B mage Procosing Algor: Normalized Squared

and

20 Squured Normalized Coron (NCC! i fen wed

ideal an objet within a nage, The eae sxpreion

“Thị aigudlm tre a trplate T of the object 10 he

Searched for and moves this template over te xanh region 1

‘ofthe iige fy the sobwinow of he sear pon pint With same Hze s,s then comestd with 7 The ea of

this expression i stored at poit pin the result image C The

more inary and Tae the higher i the teu of the

<orlaon I hey are eal, terest is 1 The objets hen

‘etstod athe locuon with he igh vale

CBoinormatie Algorithm: DIALIGN

DIALIGN [15] bininfoonatics grit, which swe

forcomsison ofthe alignment of two geome sequence T

proluee the signmet ith the highest nanbe smilie

‘lames ad sheen the ghee corey shown ge 7

-—- iOS

For the poser consumption estimation and he perfomance

rmessremet Xin Vises FX 100 FPGA wae ye The

Prefonmance was mesied on the coresponding FPGA Bot

From Aja Data (16) As measuong the sưet power

‘onuumpion of the FPGA ons board at posable 8

‘tinsel a deslnsime using the XPower oo! Tow ae

‘estos in Seton I, The put ofthe chek Fequeey, the

‘onfguaon othe processor and the tr ðtilulan ooG tệ

[ower contmption andthe perfomance of the system has Beco explore andthe ronle fe presente i the Fllowing

“alsselome To each exploration some preter: hao Be

pt fixed to asa afar comparison, For the exploration of

the impact of the clock fequency the alge and the

Emessee cmlgondun ave hoch kept fined For the

Exploration ofthe impact of he contiguruton ofthe pressor The clock Eequee) vse lam sed, Healy for ie

‘exploraon ofthe sk dstbutn, dhe pressor configurason Shu the perlrmance were hep Ted to lower the over

System power consunpson whe maintaining he perfomance

‘ii tthe perfomance achieved wih = reernce

processor design runing af 100 MHz, which i a stand Tin chợ lạc Vind tse Misr sem

A pact of he lok quency Fins of ll she impact of the vadsion of the ook fhequeney oto the power consumption was explored fra ut prosesor sem, which exeeter the NCC algo on one Nicotine, Te Micoblze was configured lo me Stage incline an om rte nit Theres forthe dspam aod {escent power corsunpion forthe sore and the othe Components ak well asthe tol power consumption of He

‘Suton are piven in TABLE The glee power consumption {abo called state power consumption In he Tolowing cause I represen the power consumption of the

‘er configured FPGA witout any suiehing sev “Te impact ofthe clock quency ono the tte ~ and he marie power cosinpion speared in Figure ® ad

Fe 9, respectively As ca be seen te ste power samsenplenixoetev hy muyml 034 m 7 NH khít tục

‘Syamie power consunpuion Ietesses by around 426 mW Miz Out of this sels the, impact onto the wi power -onspion, which rend 3.8 mW! Me The pact on {he wel power consumption as Well as onthe perTomance shown inp 10

BL Impact ofthe processor comfgrations

For export, a uni-processor design consisting of

Single icrblaze rung at 100 MIB? ws used The ols

‘ere compar again a efxence configuration, which was &

Nghi vih Sstige pple apd no abet vui

Aineser divider and batel shifter, The "following

‘insu were explore

1 adding an athe uit (AU)

ii Feetion ofthe ppetine to Sstapes (RP)

Si Combination af tana a AUSRP)

“Ths inact om the power consmpton an the peformnse

vas Sg|xSl forall yee signs The segue very

<ifret forthe ire appleaden, dúc to he die!

igri requirments a8 mentioned in Section V abd AS

—— g1, sai TAĐLE shove the spac ofthe iret

<onfguatins forthe Quiekson algo Due te mule

‘rnehes inthe sort reds the pps stages We henefigal Hr tema of exesulod line and power

consumption The inget ofthe addin ofthe artnet i

‘tly provides minimal peovement st os of pfonnanee,

‘bur wih a stoner degradation of the power coumplon Depending othe perfomance ahd power cansunpion

caneninB, the thẻ sen và the AU"* RP othe RP

‘Sten woul be coe

Fie 12a TABLE IL show the pat ofthe dif

‘configuration for the NCC algerhin AS this algo

requires many antkmetc opestons, he alition of an AU

Improves the oral xccton tne, while He reuction a he

Pipsine stages resus stone degradation (over 50%) This

‘Eyraddon sd othe reason ha te execu of arnt

‘opertons ake ore clock els, if te pipeline i redo

‘Threfor, for his and si slo aster ah a8 AU

Eee eS ana 5-sogepipcine would be optimal fom a perfomance enpstee Ihe ower consamption needs Be rece ahd {ome performance degradtonfacegabl than he eersnee

‘Suto othe AU" RP system ld ea Boo ee,

+ NGCZ4100MPE

mente se

ly Figure 13 and TABLE IW the impact onto the

‘srfmanoe and power consumption of the tice diferent proces configurations compar othe reference str re meenl for We DIALIGN algo Adding” an” AU Improves the exeeton te only tte bit, wile neresing the overall poser consumgion compared to the ference

<lsgn, The Fedetion ofthe pipeline wo Stes mpraves he teat poser cosumpion by, but warsenng In exces tine by 25%, The combination Hf AUSRP shows nny the ‘Se impact the RP system, Therefore the ference sem isthe bos choice i pefomance sth most important ctr

om the eter a the ower consumption ore emp, than the RP sytem would be a goad shoie for tese Mids oF

—

4 D@lgnat 100 MHE

ay

Regoseo 0D,

PT 111 111đ

memos hss ok

Ipc of the tak dribution nd he frequency sealig

‘To measure the impact oma the power consumption the

lortins were partonad ono te Nheudlhze proces

‘The froqucaey fe De two pressrs Was ebose a such sey tht he exceaton Feo the Galprcssor design we

{sini as posible ta the ference stem coitg ofa

‘Single MicroBlaze runing a 100 Miz Fo all systems he

Configurations of the process were fined ta Sstge

Pei and noarikmet wit “TABLE V shows the resus for diniboting the Quicker

loctim on two processors instead ef one TWO partons

seers done, The nt one called Dal 2 (880 Mle, shih

mean đại te Viual1O 2 sạc sod sid WO was runing st

NOMiie while yBT was ening a 80 MEL The algorithm was

ai

So partion that yBO ween the whole at to be svt I

‘hen sds the dati 0 prs ad ens the scond pt

HD hn soe ht parton 0 Tora sored pst

OF the Hs 1 HBL which sends te foal combined sored Ts atthe Vial 6 2 tp he Bost PC With ths parton the

‘overall power consumption could be reduced by 643%

‘Sompared the Single pocessereleence stem,

"The sccond partion callod Dual'S CS Mita) wes the Vieual10 $0 send incoming data both processor: ning {ROS Mlle 0 searches th ist for lent sole aa gBT Searches th st fr elements bigger than the pve, When one

‘iss found an leat the postion of dhs element send othe

‘othe processor Bath processor theo pate the Tiss by Ssapping the owe found skool the one the our

‘roses has found At the end both proceso have 8

Tel: ss fs BD the sen is esing fst bak to

the bast PC vn the Vatal10 5 The ver eosin of

this version fe nea he sane as the rekrenss stom, le

TABLE VI sows dhe rs for de paridoing of thể

the Vitual4O $0 partion the incoming nage ints 00

is sea to both prosessrs simultaneously As he NCC &

Srindow-osed image procesing algorithm, th Borde pitls

Tirwecn the cots ave need! by both recess Each of

the provesne ne st SỈ MỜ, high ely In 9 sme

asthe reference desi The cond patton called Ou 2 (87S /S0 Mite) wes

Virlal10 2 fo Sond the whol me fo BO BO esa 87-5

ile and caluitoe the simple numerator and tie

nomic Then f forwards Doth to HB wi does the

“ison an sere theres ek tf Vira 2 gHÌ

tune at 30 Mit While th ceeuie fine sty the xen,

the wel power ssimpton serena shy by 2.2% THLE Vi shows th oul for exeeuing the DIALIGN,

Algorithm with ts pressor, Two partons were done The

TT

Sen hệ lndonin seVeecxq uth prssors runing 330

Dik pi cele oo a ou-hasa fasion ll aks above

the sin digo calelses om colo ose sho đÌ Vlbes be le mìn agonal The scores othe ait

Siagoal ze caleulted by Gath pgeesem Air MO tc Tale calculus ne ow and yl aoe cok espa,

they exchange the fist score nares fo te indigo sẽ

lề xe need by he proces fr calulting te next

roweolun respoetely” While te execution tise neatly

39s

The weve pation saad Da (50M), Hes the

Yigal 40 olsen th equebes wo tbe paces, which 8

fash a 50 Ml He sso sy aprons used fot

se vdng the DIATTON shuethe mật họa vu the Bl

Siement an he sone bck to thet PC” Wh pion The evel poster casumpion could Be raise 5) 212%

‘compass othe single processor fefetence tem

LI Cosetsons as OvTLO0

‘This pier reports the resuch an calaton of different

mengpnveror = parmecrion, sppliction and dit,

Pridonig on 2 duwocessor system The sale af thề

Experiments ss the ae the diTrem nạn metzvafor

‘nhs power somsunpion abd pertomance triton ose

‘of sles! plsafone Depending onthe appisation fe Ht

fun be acon ta dive porter conlguations, ee ‘Songun ofthe pressor an th ieucrcie, bú ow

ood appheion pation, ate ert he shia at

“meot wader? Betis performance and power costa

‘us a coin aplication seni The vison that ore

Toad ovsriew of the parameter pacts extol to

cxtond_crising nduore bemhmUfx fom ferent Spplcadon donins ia frm ef puncte pune ato forfsher FPGA series rom Xi Futlennoreth paper provide tea fre einai

‘ofthe omer cosanpton an 3 high level of abatacton bt Therein, other rescue io the area sạn Be done and

“The ators suuld eo đang Pro Alhg in M.A

de Mao a an Mendonca Comes for roving ts ith tit

‘Ccade npr fe DIALIGN algorithm,

Reronences 1¬ Rene Gate” Uo

BỊ K Peon, A Yan, SIE Wit:

Novel Approach for Modeling Very Dynamic and

Flexible Real Time Applications

Femail Kaa

ri, Bertrand Granado! snd Mohamed Abi

'ETIS Lahoraory: CNRS UMRSIS}, Universi of Corey-Pontose

“EASE4, # avon de Ponceay F9S000 Cergi-Pontoise, France

‘Computer & Embedled Sistem Laboratory (CES) Nathonel Schoo!

of Engineers of ft, (EMIS) B P.M 3088 Sax, Tulsa

Complex Mowover, a spe ef sb perfrmunce, ASICs

ompossd of ssveralerogecone asks vít erent

aici In aditon the growing complexity of real

‘ine apictions ody peas sport ehllngs,n rat

ppt ce fo thir dptamietebavoe and nocrtatcs hic

Sosk! Happen asinine [J] To vessome these prblens

c3 Sghen en lo use dynamically scoaiguabe bitten

(DKA) The developecat of the ltr opens ex bribe ia

the Bi of architecture design nde the DAS are sell,

Sia to deal wih th đan ef sew applets an

Silos Seer compromise Rolaeen su, ĐeuDg sat

free [DJ la palelhự fine vhined đụRahisuly Feconfguble areitclres (FGDRAI, a # hod of DAS,

an be ated 0 any application more gpimaly tha corse

gysin DIAS Ths fete makes tom today an iatcesing

nho when comes to andle computsonal tse in 4

Hh condrined contest, However ts type of athens

rakes the applications design very comple [3 expeily

‘th the Tak of stable sn efficent tos This compen

ol be abstract at some Revel int ys at sign ns

ty peiding design tous and al run ime by providing sperating sytem that abst the lover lel othe ser {EL Moreover sch archers requres the presence of x Sven ato effectively page dynamic appiations, has tere able 10 respond eapidy to even Ths cm be achcved

ty providing a sufable scheduling approach and dediat seovees ike “Tdvare peeempion ai dsereases coigursions ad contents trnfer ines To celize sH fee schodle of at appcaion, this operating yer {he pat here the donor en be epee on DRA,

In ths piper toate inresot in the mling of sypietons st coult be excited on stanly

‘ovvnfiginble artes, This hind of appistons se Sarnceind, in addon «Rs reiting sons by Sel ype of obi The purpose 1 to impeane the Pestmaste of he modsing tecbigues whic Tatas the

“be dalpnanelllelhelnls ppmaek The reese of ths per sce ax follows bn Sestion 2 hit review i hsen bot the cones) and the Felted work om malig fsbnkis sed on feent

‘oman "Seton 3 deeefles oor new kshnigue modsine fpliaions aygted to DRA The Seeimm 4 mưa 3 deaelgia of tie "proposed madeing metal and

‘omprisons th other model, while the last Soton ds

‘Sonclisons,

‘Context and problem deintion Today, embudlod sjtens age ure and are wel ia

‘connie resis Toe ervionment st rate posed Hy {tis smleamenl sel mewss tạm om the stvironmet responds o thse stim by aking abst of

‘pertons ad prodoces the ouputs used y te ean row a eset Dynamically seconsigurble wettest,

se netting sluon fr ht pe of eplcations, Die to

a emerping rae of applications with dyaaiie bela

yeamic scheduling (or reconiarable splemoaship

This paper dels with the conein bated Scheling or

Le The madglug dĩ the applicton kat shoal xb ts

{conan impor res-tie constraint

+ The runtime perfomance oft scheling algorithm hat

must be rsamable a lenm of overbead for a plea

“The diferent components schon problem ae the

task, he penal canstsins, the reseurces and the abjstve

Function, Tasks excision must Be programm oepimize

ssificobjstive wth the consierton of sever eter,

Mang vesoluton sttepes Ive hiện proposed a HVE

Is] Usally thee mets swam hat pocenng ites esa

bye modeled si deterministic values, They use peice

‘compote schedule to Be execked eat a planned is fw

TRỢ Thạc be of ạt ony artons, ba aso hee of

1 tof dts tha re only prevnons or estimations 8 the

cess t dsl with ues ov exit inte roses

dat Hene, for an edetivereslon we Ao 10 take 8

‘Sanieat reformulation of the problt and the solving

Bethode in seer to Bile the heogamdlan of thà

Sncern an apecson i scheling (7

UUncrinty in schedling may ace rm many sores [8

New esexect asks ay accu

*Cancstton a entiation of existing asks

4 Theerecation onlero aks on ose an be shang,

{Task evga ï 2 tk cold be dooe on te

rexnaros ale o uth the oie ots rxoare

be changed This Mai is pees if ch eer

becomes anocble resale tan hers

«+ Theabiy to ehangeexeclon this made incdes

lank ould he resume ot ot the overlap hebaeen tak,

‘honping the ange of aking asount ether or

fot a tine af presnion, chaning the munbor 0F

‘Rsoures needed fora takes:

‘Were considering il caves whet sme vriaions could

veur ad some dita ny change wer te fren The sods

toe (senile oda econ srl arts,

In gota tate are two main apwoaces dealing wih

uceraaty i a sebeuling enviroment aooceding to phe

In stich unceninte re Xen ona scent [8

+ set setodaling approve irs to bul a eabus

see sched tt protecied a much a6 posable

esoteric asc thes flo

‘scone onceranies only in denpn phase (ffi)

anette wins for all preter, ts impli

Fiatned Howse, thin eld Roce nie le dưỡng the Erection doe to the ‘Jy ewionmeal khốc Umsepsted evens cominlly acu Therefir, in this

se, reac approsh may be more appropiate

4 Inead of aotcpating fare unseraities, reactive scheduling thee dessins in restine wien sume Tmoapected events acer A reference deterministic Schoduling termined offing, i sometncs Unt and pinizei la general eactve methods nay Be ao torre foe high degecs of tnerlahf or when

‘Blomation bout he uncer at val sgprshox i called grace eactne schedng, Ths Istrid mete pss 2 ombintan of «prove stay for generating a protected busting schedule wit 4 reactive aay ho resolve the schedule ineaslites caused Wy th

<stuaness dat occur day schedule exceatin Heo is

‘ehlolingreschaluling method permit 0 take ie socount celia user th execution proess ad eases be etomaneeI] I0 Eor raeheiolng the luenle rovided rescheduling, The fou segs fs mia wa eH kes Le

ti an presto sytem salty [1

‘Sohedlin ehnges te quite dierent depending on de anu of the problem ab ihe type oF dstubance corse: esources fli, the dation of raraton sthe et ai few tats can oocar, ete The mainly aed ivethode ae Abutching sles ears, metaieaities an steal lnlignce teimigus (12) In [13] ators comet s Sehedaling.prblon where some sks (elle

Alsgn cero Thy ws an opinion me oệclog hosed fon stoshasie dynamic programming In (13) and [15] kholne peblem with uncertain escurce avilable as cute Aahors used proactivereactve satis and heuristic techniques Anotier uncewaaty ease, which Is tasenai le đượon, hai becp studied in (V6) and [17

‘Authors dieu properties of robust schedules, sid develop

‘rat and hehe slon proaches,

`

‘To sty a syst we need mods to dese inca signican sstin chutes of gomely infenuton fae dyeinsn The lane sera system hari a

St ere to somes baw a atin Beles al changes

‘iter nmin fr tne very pene the very apse [IS], Model types have diferpresomation as shown HL gure some ue text-based using symbols whi oes Have

‘ssociaed digrans

+ Grophical models ase o dingrom technique with mumed smb tat represent press and Tne ha oto te Symbol an represect relationships and varios her aphical mations orqseat consis (igre Tới tị (a

4 Texas! models ypialy use standanlized keywords companied by purrs (ute He

ta edition, soe mle have sal fom, whereas hes

ve stl asta dig node execton 35s Fe 1 {G1 The old ele a token) roves trogh the network and

‘represents te excisional ce of fe appt,

In he domain of mbadded sysoms a Lae numberof

sale bmamah have boon proposed (19) 20), [2],

Including exiendons 10 fnte sie aches, dat flow

rpls, communicating poceses, and Pull ey amon

Shs ths seta we present mắn nho gfcUmpuetloe

+ ne State Machines

‘The lassical Finite State Machine (FSMD resentation is

obbly the nos wel-kaown ol used for desing

‘inl systems, However, ae of he diadvanages of FSM

te exlicly captured in the del a the sytem eorplechy

snd amiyre [22] or dương sytem, the FSM

Fepresenaion 18 a appropriate Hecate ony 39 10

Ids} rich od of system isc create all theses ha

represent the dynamic behavior of the applicant hen

wahiraable do te 1 ạx the nan oY ses could be

olive

+ Dat Floe Graph

A dataflow graph (DEG) is 8 se of compute mass

connec by heed inks representing the How oF data 18

‘ery popular for modcling: daosoninated syste I

represented by a dieted grt whose nodes desuibe nề

[cessing ahd the sts romesen the pari nd flied By

The dit However, he conventional el inate fo

‘spree the contol ie of system [23], 1 proves

‘napprprat tạ model dni spears

Fev nei (PN) is & mosing formalism which combines a

welkiiual mabsmatell teuy witha graphical

‘epreseaton of He dyn Boar of stems S Pa

Netiva Stile PN (PT, W, No bane: Ps te sek

‘romans sich opreen tasks Fis a xe of are to

Fen} W: ED {102.3 | fsa weight incon, My he

ints marine Hower tioagh Pts ete welsh

for the design oP atic systems it lacks ippor for

snamilly mole systems [24] tn et the PN sete sens only the siaie popes of stem wile the

"namie ane el fom PN exceuton which requ the se

‘ttokens or rakigs (dente by de) ssc wth places [25], The corsenionsl model sire fam gd specie

oF camplee stems Ike nck o the poten oF ine which sa

AM ctor st embedded applications amd lack of Iisrrbicl composition 26) Thteore, several fornalistns hve inipendenly been proposed sn difren coments flee to overcome the problems cited above sich as Inoducing the concep‘ rch, tine, an valued have te duration nthe sti Sioshastc PN iste {he ay ¥o mae xpdomnese mason, ada low {ite asa element in the PN Colored PN alow the st and designer to wines he shangss in places ad tnstons dăoogi he anghadlan of clorspocc ken and

‘overeat theo the stem canbe peste hh the anacs colos [8 Most ot the methodologies memoael provide ao suliet spa or ysens wich tase arial dsc Kear Dimunie cetion of sks for inset supports By mont of the sss abuse merino [26 I [2h authors proposed an evension of ighevel Pet act model [27] i order 19 cape dyonmically modiTable fnbedied systons They coupled that mods! ith tanh Ceunsformsion tcheiqucs and used 4 double pashout -wwsch vhich cmist ofthe replacment cia etl nt by aloe mong dynamic tke cretion hạ vọt table

ML, Proposed metnod tore begining to deste our ming me, vs koe the constnins shat pally appear dynamic systems nour case, we considera fi resting context, Hew tor actly developed application, especialy

‘nulimed ani coauol apeations, turdines or desing Stolatons revs ony iw degradation of Quality of Service (Q3) witout affecting ood provesing tn this concn Irate ks are cherie yi Tsing artes

secu ine, Desane tD) Pests Precedence consains among aks,

“Tasks could be preemped Used sous of the DRA

a vel wor all ehaacentis may change: tsk (he rele sie, dealing and eeciion lis), sll x the

"ike wera unexpected shangss ad wales vation For

‘sti, ne wil consider tre cates of dynamic scheling problems for dynamic aptcations Lạ) The nmr of task sno He my hang rn iteration o anther

{hy Tho tsk xcs tie my’ change oo {c) The amber ot nda sours for ass excouin is sible (vale, the numberof aval resources ty Aeceae ater Ene eee

or thoes ces he goal 8 develop a tut shedting

`

be adaptable tothe possible

Aistutanees Thareloe, we cousider 3 prcitereastive

Simp Bin fr thesia pr) wed to aa the

xc ofthe restive sag oni, x0 tot scheduling

{zvjons havea beter quality abd peediced i shorter time

‘Torrrent allthove constants the sr el and to Be

‘Aguas for the adoped sche proach, ou graph wl

‘be compat of two forms af odes The fst fe of nods

fer psa aks which ate kaa in ane and khoe

xsl & pean damp the hole application of the

Iieyele encoun The second type i He dane sks

ssh eld he exec et ad tn rs a ith

Storble umber of neat rsoens, Theres, the Fst

Sieg fs sgpu le the to pass f he appt sai and

wamiel ` The 4 piaffvbasal chelkle ls csublshed

‘line for sue an Suc a schedule serves very inporant

functions: The fiat so alles ells ofthe adware DRA to

‘he fret hardware asks The soc iso seve ge bas

Toe plating sks Unt may acc ds exceabion The hse

ie so sort sate tanks om the graphs schol them

reslenee conse opto onde Task ae ected

rte cries ponies hee equity Botecen see

‘sks, task which bác mm ckeevfon fine wil hive

Dory to be launchd bolo the ethers AT rutin thề

98/808 iso generate ane sco hat deviates fom the

Srp scbalule at ile as possible so hat the eps

Spertoas will Be sty sine Therefore, the online

‘eso ols for excesom), I os to prefetch canBaimatone

Sontxt of new asks the cols that are avaible for

{xceting ad find the possible wat eat thes nthe

‘ue schol witout eect on performace, This sels

pur sus fe) of pid alga sod oa 2 spe

2 leiulo8 teäoique s tt ca refamm cline exes

‘ith no cvered consis Finn able portonie

STN ks, forming th applicant exes wed on Naga

resource ofthe fardvanedviee Thain sks exceton

Sree ho met the rl fms eins Th eiedulng

problem i known 4 Be NP-hard (28) [2] In th cies

Reudlee Me shalc ngmùr tehole which offer fst and

Teuuoally aood solution but Jo mot uatance to find ah

‘pda schedule

ita the diferent elndiom comespoing to cur mel

For ths exams these (11, 12, TR.TS, 15, TT, TS

represent the i ask hich ae ays exes in sach

period nod (79,710, T11} are dynamic ase which ay be

‘xceted in some pind bụi to oes and ose number

fot resource eqdrementï vathbc Eạ tk l epeesrtod

‘ith tne thanktgisice Ci lạ te cieedion ng ad Di

the dealin

The Gist dye ete casldred in ths model tas

wh srishleexvuton te To reese thal ane, we ae

GPERT) Jo}, which ko dự mai ti ai0nx

Tanoniess in ati exes tines, For each ek, PERT

TndowMe a tat date and end ne atthe erie and Is,

The char denies the easel path whieh Jtcemines the

ninimam dation of te projst Tasks ae represen by

srs wih asiosted number preset the aks dati

con of sks (gute 2) fn hie model, e replace the release lime ete hy the xu re woul be change ens scettion, and we Kesp te dentine a wil fe wet 0 name the makespan (or the length of the asd) I figure 3 tasks wih saraleexctton tna ae 1.7, 7, Tis ll noted by the sew sesh

Torhe exvtod,hanas tasks esd 9 mi number

of resources The percentage of this mnimal number is Instat in labels ovr ks odes This eae seq found an some compute vsio applications whee fs task

is dteting objects and ten 9 prteulae proces is applied

fn ech dated objet To excite ule tstances otis frocess, the monieuin need number of sours ll be

"mulinladby!he nanberofimermeee la ñgee 3, tk T9 vi {he minum sede numberof resourses nde 0 th Ine! wil be tmalpled by mC the ins momer 9-0 tea

‘ask wil ot ascirThe Instance nner is unespeted Gon the sai ph al decison wil be taken cline The numbet

‘will depend on the previous executions athe eal np dha o be prosesod (st as Keyponsin ae robaGe vison Spliation) Thus ill be sale ec sen pedel, based on is previous vals For more del, we Lae a

pelclor to etseve TÔ, In the ñmg sesuien te Sliotion needs n=, =10 insanoes of T9 So fr the Second teaton te scheduler il pdt (© exs82 =

To instances of Twn raÍ executions a= = Boe the nent exceton my cauld be: the ma of precedent

le, te hight values of he average of vel a ale (Gen 8}, oF a Gmsin Uke probaly whi a yest reslsic dhtbuion, ste The choce wll depend om the

$Sppliition Forte exampe fs nwing rbot which sd 19

PS thedteston athe presence or absence of abo ñ NHÍ be pvefCred fake hele ol ace ith cet

‘weg nour mods the number nis represents above the cược The si eepeseat the dependencies etvooh sks Eo Stic (permanent) babs, we represen arcs isis,

le wpeeicuble dpcadences are reseed by dashed

‘the eesontirable device esses Cue nay oscar

wich wil aol the exoee sea Thus trecaioe

‘omar with ceded ones A sale, which ile 36

‘he tia somber of snares, wl ate the stunt of

emsinng resources From the realy Hissin

‘etemines the Đây Ha dm hệ exectted on the

recofigurble device, Tasks with the higher prion wil Be

placed fst unl the ane of device i fly occupied

WY, Comparison of models

When we compare with otter med (section 2-0), the

proposed technighe greens several alvantages, For

{dos ot eontininfrston aout the amber of stance

Dang exoeton oF he aplication, every tik eps By

‘he nals of DFG sect oe in each eration [1] Cy

‘hema ods hve Hho fei teeptbne 9 26 eon

‘ama Soe model hs, we ne to represent es of hề

Sime tsk, which reo tế sạc of fhe moe Gos ite

“XĐ) in our noel noun aout umber of instances of

2 en tobe exceed fs ped by he cide fort ofthe

(Gos Spee ayy, ares could be Label with ci eis

Folel are [22] fre ne slelnston scion 2-0),

‘nel are postive integer soi cat xen ñine

‘ith non ia easton eepreseting a sk That ayn De

sheeMed in sone Herons ta ite Kal © T9 and THO ate

fr exceed, chen shoul be al, wih is posible

PN defiaton, In atone re 1 ll ing places sould

ive at lest oe ther which wll he et psa #110

‘TH ws not exeat ire

‘Finny intron malt provide a powertl aw eure For Pet nets but nay not be pssbl it manpet coset withthe basi plosophy of Pat nts Research [33

or vesoueseprseation, PN modes is fete by an aed place wih 1 fied oubet af tokens, To begin [pecs ick in the ond of ckeetien However, thin dal

SS adeyine in our case ince the number of aaihble esouroes my lunge or the exciton

“heretore, the use of convertion todsting methods is

ạt efoctive in our eas, Tn fact with PN and DFG model (iu tere is distinction Retaeen sate aks and shame ones har may ot be executed), aor an expe

lo af tis arabe execution Sie se sks)

“The ngin nhac of the proposed method is the

posi to poset several dynam Tetures of eal Sime

Spplieatons withthe minim of nodes and ths na site

Feratsm Indeed, fom he fist sight of the mods can

‘wing out tc nan characterises ofthis mode:

The distinction eoween the static execution (which is

tem by the squared nodes) andthe dynamic exceuion

TS the iks whose execution and amber of isances

certain presented by the crled nes)

“The tasks howe exenton ime fs arable presented bythe

ste

~The pertentage, for cach abl of needed resoures for its

execution In ach eration, and depending onthe avalble

Tesarsex schol sable to decide bi ead tasks could

be exceed onthe deve

Those informations wl be useful fre forthe sched

Wercoaider 1D area ined as fa ctenonly ined

configurable resource ie, bl even 20 area mal cold

te conexant In that cơetieed 1D smd, sks ca be

alloted anywhere along the horizontal device dimension the

‘verted dimension is aod and spans the tot Heht of the

ardor task aes (oe figure 8)

axed on the proposed tanks model statically dined tasks

represent by sarod nodes, wil he shoe an ple

‘he reconfigmble device during he proactive phase, Whereas

<ynamicaly defined tasks, which ate represented by eld

odes, will be schedaled olin ip a eative phase Tis

‘online decison wl tke into account the variable paramere

au uy to i inthe et fea guratoed ass, dey lo ii th new dyn ake

Conclusion

This paper presened 2 piu moving problem ling withthe implementation of dynamic and exible plications on dynamically reconfigurable architecture The Pupese i to consider mos ofthe dynamic etuessupored bythe architeture and wo present them nan esy abd eiclens rmathd For tat pot we have proposed a ode, hase an ome fetes of existing modsing techniques, and whch is

‘tore dedised to dynamic real tine splicaions, The ns

‘Srantge of our speciation enodel H the, posi to fin tore excl scheduling charceriicy fom the representation, Those characteristics include tbe distinction berween static and dynamic accrring sks, trang ot asks nse exceuton ime may ehinge over the time and Astemioe the number of resources acd or exceuing Tardvare sks S, we wil beable eter o ke dsssons of fot AS feoofguable architect, we trast OLLAF [4] (Operating system enabled Low LAtciey Eis), an orginal EGDRA spectealy designed to enhance the linc a RTOS series necesary To manage sich architecture Fare

‘works sill cont i integrating cor scheduling approach mong the servies of an RTOS faking ino account he es posses efered by OLLAP

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