A highly digital vco based adc for iot applications on skywater 130nm

Our work applied this method instead of pseudo-differential to reduce hardware complexity and power consumption; while the SNDR of ADC is improved in the single-ended mode for the bandwi

A Highly Digital VCO-based ADC for IoT

Applications on Skywater 130nm

Duc-Manh Tran, Ngo-Doanh Nguyen, Duy-Hieu Bui and Xuan-Tu Tran

The Information Technology Institute Vietnam Nation University

144 Xuan Thuy street, Cau Giay, Hanoi, Vietnam

16020772, doanhnn, hieubd, tutx{@vnu.edu.vn}

Abstract—This paper proposes a highly digital

Analog-to-Digital Converter (ADC) for various internet of things

appli-cations, which operates at the bandwidth below 50 kHz Our

goal is a highly digital ADC that can be integrated into the

low-power System-on-Chip (SoC) to adapt to IoT demands like audio

recording or sensor measuring The ADC is implemented using

only ring-oscillator and digital circuits that is based on

time-encoding technique and Delta-Sigma modulation In this work, we

optimize the Voltage Control Oscillator (VCO) for high linearity

and apply a Cascaded Integrator Comb (CIC) filter with the aim

of increasing the ADC’s resolution Our work is implemented and

verified by fully open-source tools on the Skywater 130 − nm

technology The ADC produces more significant than 12 effective

bits at the cost of 0.97 mW and occupies 0.08 mm2

Index Terms—VCO-based ADC, Sensor Readout, Open-source

IC design

I INTRODUCTION

Today, the IoT device requires various data nearby like

humidity, temperature, speech, and so forth for complicated

applications Therefore, analog-to-digital circuits play an

es-sential role in each IoT node, which converts the signals

of sensors to data for other process steps There are many

sensors and MEMS devices like thermistor bridges, MEMS

microphones, and so on Most of them require high precision

for a few hundred microvolts from several hertz to fifteen

kilohertz Moreover, to reach the IoT requirements, the ADC

must be a cost and power circuit As a result,

low-cost, low-power, high-resolution ADCs are essential for SoCs

that serve advanced IoT applications

In recent years, the Voltage Control Oscillator

(VCO)-based ADC has been developed to solve the problem of the

CMOS scaling However, the advantages of performances,

like consuming low-power and occupying a small area [1],

[2], are more attractive These advantages of the VCO-based

ADC are suitable for IoT applications Moreover, the

time-encoding technique applied in this ADC allows the digital

circuits to execute a lot of analog functions Thus, the

VCO-based ADCs are more scalable than pure analog circuits and

can be deployed at the new technology nodes in the less time

For the reasons below, the VCO-based ADC is appropriate to

integrate into low-power SoCs designed for IoT devices

The non-linearity of the Voltage Control Oscillator (VCO)

limits the Signal-to-Noise and Distortion Ratio (SNDR) of the

ADC In the prior work, VCO-based ADCs were typically

deploys the pseudo-differential architecture to reduce the ADC distortion However, this architecture performs in two branches

of ADC; thus, it spends twice the power and die size compared

to the single-ended mode By customizing circuits, the works

in [3], [4] increase the linearity of the VCO to decrease total harmonic distortion of the VCO-based ADC Our work applied this method instead of pseudo-differential to reduce hardware complexity and power consumption; while the SNDR of ADC

is improved in the single-ended mode for the bandwidth below

50 KHz

This paper introduces a continuous delta-sigma VCO-based ADC and the techniques to increase the resolution: customiz-ing VCO and applycustomiz-ing the special decimation filter This ADC

is designed to adapt to the desires of IoT similarly audio recording, sensor measuring, and any application for the band-width below 50 kilohertz The rest of this paper is organized

as follows Section II introduces the concept of the VCO-based ADC and applying the delta-sigma modulation for this ADC Section III briefs the research related to sensor readout circuits, VCO-base ADC and concludes with a few opinions about VCO-based ADC for IoT After that, in section IV,

we propose a VCO-based ADC structure and Ring Oscillator customization Section V presents the post-layout simulation results, also comparisons between our work and priory art

Finally, section VI concludes our work and defines the future work

II BACKGROUND

VCO

Sampling Clock

Fig 1: Basic structure of the VCO-based ADC

978-1-6654-1001-4/21/$31.00 ©2021 IEEE 549

Time-encoding is an exciting technique, which converts the voltage domain in analog processing to the time domain in digital processing One is the VCO-base ADC, which shows the fundamental conversion mechanism in Fig 1 Thanks

to the Voltage Control Oscillator (VCO), especially the ring oscillators, the voltage ofVin(t) is modulated to the oscillation frequencies of a square wave ϕ(t) After that, the number of ϕ(t) pulses is accumulated by the counter to ϕn(t) values

Finally, for each sampling clock, these values are dumped into the register to ϕq(n) and the counter is reset

21

11 phases

Analog signal

VCO

R1

R2 Inv1

Inv2

Inv2

Phase Readout Sampling clock

DFF 2 DFF 1

VCO

1bit

Fig 2: Phase readout circuit

In order to reach high resolutions, the number of pulses per sampled time should cover all values of bit levels exactly

As a consequence, the principal method requires the VCO

to operate at a wide-range frequency However, that raises the phase noise and the non-linearity of the oscillator, also creates error bits in the the flip-flop’s processes The delta-sigma(∆ Σ) modulator is applied to shape quantization noise rather than increasing the VCO frequency range Instead of using a counter to accumulate the numbers of pulse, the∆ Σ modulation uses the phase readout to catch the edges of pulse (falling, raising edge) In Fig 2, the phase readout includes two

D flip-flops and an XOR gate that captures raising or falling pulses, then dumps them into high logic bits at the output

This structure is first-order noise shaping, which is evidenced

by the below equations and the frequency response in Fig 3

ϕ = Z

V

(ω0, kV COx(t)) dt

ϕq[n] = ωqnTs+ kV CO

Z nT s

∞

(ω0, kV COx(t)) dt + q[n]

y[n] = ϕq[n] − ϕq[n − 1]

= q[n] − q[n − 1] + ω0Ts+

Z

V

(ω0, kV COx(t)) dt

N T F = q[n] − q[n − 1] = q[n](1 − Z−1

) Where:

x(t) is input signal

kvco is sensitive coefficient

ω0 is offset frequency ϕ[∗] is phase of signal

III RELATEDWORK

In IoT devices, the output signals of sensors are low-speed; thus, sensor readout circuits have low bandwidth The

Normalized Frequency ( rad/sample)

-60 -40 -20 0

(a) Noise transfer function response

20

Fs

(b) Block diagram Fig 3: Delta sigma modulation principle

bandwidth of readout circuits is below one kilohertz in [5], [6] It is also between a kilohertz and ten kilohertz such as [7], [8], and also up to hundred kilohertz in [9] Additionally,

in speech recording applications, the bandwidth of ADC is either20 KHz or 24 KHz [10]

The VCO-based ADC has been becoming popular, along with plenty of applications Five main classes are mentioned

in [11] In this context, these ADCs are allocated to two main applications:

1) The first are high-speed ADCs, the bandwidth above ten megahertz, and that is usually put into wireless operations [11], [12]

2) The second are low-speed ADCs, the bandwidth be-tween a few hertz and hundred kilohertz, that are applied

in sensor readout and speech recording [10], [13]

The ∆ Σ modulation is applied to increase the signal

to noise (SNR) ratio in the whole low-speed VCO-based-ADCs The close-loop δ σ structure gain SNR of the ADCs;

it also gains the implementation’s complexity Moreover, the non-linear voltage control oscillator is a critical problem that limits the effective resolution of ADCs by distortion In the hardware implementation, the whole priory work approached the architecture method to reduce distortion In [10], [13], [14]

design the ADCs based on closed-loop differential structure

As mentioned before, this structure spends twice the power and die size compared to the single-ended mode and gains the complexity in the hardware implementation In this work, we focus on increasing the effective resolution without the com-plex architecture for low-bandwidth ADC The next section presents a detailed proposal of our VCO-based ADC

2021 8th NAFOSTED Conference on Information and Computer Science (NICS)

550

IV PROPOSAL

A Proposed structure

The structure of the proposed VCO-based ADC is presented

in 4 In this structure, the ring oscillator, which includes 11 delay cells, is used to convert input signal x(t) to 11 pulse signals from ϕ0(t) to ϕ10(t) with different delay time The phase readouts, which is mentioned in section II are combined into a multi-phase readout to read 11 pulses from the oscillator

After that, all digital output from multi-phase readout from

y0(n) to y10(n) are summed by an adder tree that becomes

a 4bit signal Y (n) Finally, A Cascade Integrated Combine (CIC) filter is applied to reduce the sampling rate and increase the signal-to-noise ratio (SNR) of the ADC The final output D(n) is 32-bit data written out to the memory for testing

The whole system operates at 25 M Hz, while the data D(n) frequency is 24.4 KHz and 48.8 KHz at the oversampling rate 512 and 256, respectively

21

Phase Readout

Sampling clock

DFF 2 DFF 1

VCO

1bit

11 phase readout circuits

Adder tree

CIC filter

Ring oscillator 11 delay cells

4bit@25MHz

32bit@(<50KHz)

Fig 4: Proposed structure m

B VCO customization

The ring oscillator (RO) is the most suitable time-encoder because it has less phase-noise, multi-phase output and is highly digital The RO could be designed easily based on the inverters (delay cells) In order to achieve fitting RO

for encoding, one needs to care about the number of delay stages and delay time of each inverter Unfortunately, at the normal supply voltage (1.8 V ), the simple inverter (Inv) has an exceedingly small delay time, unfitting for low-speed circuits

As an alternative, the cross-coupling Inv is suitable for this case It could obtain a longer delay time and low-power consumption at low speed As shown in Fig 5, the cross-coupling delay cell is constructed based on differential inv, which includes two main Invs (Inv1) and two auxiliary Invs (Inv2) In our design, the PMOS and NMOS transistors of Inv1 are W/L = 10 µm/1.9 µm, whereas the PMOS and NMOS transistors of Inv2 are W/L = 5 µm/1.9 µm The

RO includes 11 delay elements, that operate from2.5 M Hz

to 10 M hz with tail supplies voltage of 0.5 V and 0.1 V respectively

The ring oscillators (RO) are non-linear devices that inject distortion into output signals and reduce effective bits There are two ways to resolve this issue In the first way, the research approach architectural level solutions, e.g by calibra-tion, feedback or signal swing reduction [12], [15], [16] The second approach is less common; it performs a circuit level optimization of the VCO core [3] Although the second way is less common, it has obtained significant results [3] According

to the method mentioned in a second way, our work uses two resistorsR1= R2 = 100Ω to feed the input signal into RO

Fig 6a illustrates the ring oscillator; an input signal feeds that through two resistors The simulations and measurements were done using NGSPICE based on Skywater’s PDK The measured voltage to frequency conversion curve of the VCO for 0.2V to 1.1V input voltage sweep is shown in Fig 6b

Clearly, the curve is visually linear The deviation of this curve from a best-fit line (i.e., the non-linearity error) is also shown in Fig 6b By the results are shown above, the linearity range of VCO from 2.5 M Hz to 10 M Hz The worst-case nonlinearity is 30 KHz , corresponding to 0.3% of the full scale

11 phases

Analog signal

VCO

VDD

R1

R2 Inv1

Inv1

inn

inp

outn

outp

Inv2

Inv2

Phase Readout

Sampling clock

DFF 2 DFF 1

VCO

1bit

Fig 5: Cross-coupling inverter

C Decimation filter and wrapper implementation

As we know, the ∆ Σ modulation is the oversampling method that should apply a decimation filter to downsampled rate The Cascaded Integrator–Comb (CIC) filter is a class of the decimation filters, which downs sample rate also shapes the noise of output signal In this work, a third-order CIC

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11 phases

Analog signal

VCO

VDD

R1

R2 Inv1

Inv1

inn

inp

outn

outp

Inv2

Inv2

Phase Readout Sampling clock

DFF 2 DFF 1

VCO

1bit

(a) Tail supplies voltage resistors

0 0.5 1

Input voltage (V)

2 3 4 5 6 7 8 9 10

0 0.5 1

Input voltage (V)

-30 -20 -10 0 10 20 30

(b) Voltage to frequency curve and error frequency for voltage Fig 6: VCO customization and analysis

filter is implemented based on the structure is shown in Fig 7

to receive processed data, for the reason that the ADC can

be integrated into the SoCs The CIC filter includes three integral blocks, a down N time sample block, and the third-order Comb filter For the implementation, the delay blocks (Z−1

) are replaced by the 32 bits register As a result, the output is the 32 bits signal

The ADC operates at 25 M HZ; the Over Sampling Rate (OSR) is set equal to 512 and 256 Thus, the bandwidth of the ADC is equal to 24.4 KHz and 48.8 KHz respectively

In the test Wrapper, the output of the ADC is saved into 4

KB SRAM The chip could be taped out in a short time by using many IPs from the open-source hardware ecosystem

For example, the pad rings, the management SoC and the PLL are reused from the Caravel Test Harness, while the SRAM macros are from the OpenRAM project

V IMPLEMENTATIONRESULT

Thanks to the fabrication support of the Efabless Open MPW Shuttle Program, our work has been completed by fully open-source tools and the Open Source PDK published by Google That is based on SkyWater 130nm CMOS technology when the supply voltage is 1.8V The ADC is laid out in the Caravel User Project Wrapper with other configurations, test controller, and 4KB SRAM for testing The Wrapper and the analog domain (the VCO layout) are shown in Fig.8

The ADC occupies 0.08mm2

silicon area, while the voltage control oscillator occupies 0.013mm2

, and the rest is digital layout domain

21

11 phases

Analog signal

VCO

R1

R2

Inv1

Inv2

Inv2

Phase Readout

Sampling clock

DFF 2 DFF 1

VCO

1bit

Fig 7: The Cascode Integrator Comb

Our design is verified based on the Skywater 130nm Process Design Kit (PDK) by open-source tools and rules published in the open-source hardware ecosystem Mainly, the Magic tool performs the Design Rule Check (DRC), Netgen carries out the Layout Versus Schematic (LVS) The MAGIC tool is also utilized to extract the layout for the post-layout simulation

Finally, the Ngspice tools and 130nm Skywater library are used to analyze the performance of the ADC

(a) The layout of Wrapper

(b) The layout of the VCO Fig 8: The layout view The results are related to mix-signal simulation analysis

The Ngspice tool simulates the VCO and phase readout operation for switching the D-flip-flops exactly in the analog domain A Python program is written to convert these analog

2021 8th NAFOSTED Conference on Information and Computer Science (NICS)

552

signals to digital signals Finally, a Verilog test-bench

simu-lates the CIC filter with the input is converted below

The performance of ADC has been investigated by applying

the signal tone of 11 KHz to the input The nominal dc

voltage of0.6 V , the input signal swing of 0.4 Vpeak, and 0.1

Vpeak are applied for data conversion analysis Fig 9 shows

the spectrum of the output data with two voltage levels are

mentioned above when the oversampling rate is set equal to

512 As Fig 9a had exhibited, the SNDR obtain is 80 dB,

when the input voltage of 0.1 Vpeak Meanwhile, caused by

the VCO nonlinear at the input signal of0.4 Vpeak, the SNDR

is limited below 59 dB, which is visible in Fig 9b

Frequency (Hz)

-140

-120

-100

-80

-60

-40

-20

0

(a) Power spectrum at 0.1 Vpeak

Frequency (Hz)

-140

-120

-100

-80

-60

-40

-20

0

(b) Power spectrum at 0.4 Vpeak

Fig 9: power spectrum of the ADC output (OSR = 512)

Additionally, when the Over Sampling Rate (OSR) is set at

256, the SNDR of output decreases 6 dB, but the bandwidth

increases a second time Particularly, the SNDR obtained is75

dB, when the input voltage of 0.1 Vpeak Meanwhile, at the

input signal of 0.4 Vpeak, the SNDR reaches 54 dB Fig 10

shows the output spectrum of ADC with (osr = 256)

The power consumption analysis of the ADC would be split

into two domains First, The VCO has applied a sine wave of

0.8 Vpp with the offset of 0.2 Vdc and using Ngspice tools

to extract the average power of VCO from 5 µs to 10 µs

Second, the PrimeTime tool is utilized to approximate power

consumption of the phase readout and the CIC filter at the

clock of 25 M Hz, and supply voltage is 1.8 Vdc In general,

total power consumption of 0.97 mW , the analog domain

Frequency (Hz)

-140 -120 -100 -80 -60 -40 -20 0

(a) Power spectrum at 0.1 Vpeak

Frequency (Hz)

-140 -120 -100 -80 -60 -40 -20 0

(b) Power spectrum at 0.4 Vpeak

Fig 10: Power spectrum of The ADC output (OSR = 256)

occupies 22.68%, and the rest is in the digital domain

By the results are investigated before, Table I shows a comparison between the key parameters obtained in this paper and with prior sensor readouts, audio converters in the close-loop differential operation mode From this comparison, our ADC has the highest SNDR, which proves our work obtained high effective resolution without complex architecture (close-loop differential) However, power consumption is higher than other work for two main reasons First, An CIC filter is embedded in the ADC core, increasing the power of the ADC Second, the ADC is implemented on standard high-density library CMOS, so the inherent power of the circuit is relatively high

VI CONCLUSIONS

This paper presents a VCO-based ADC for IoTs applica-tions The ADC is aiming for integrated into cost, low-power SoCs The proposed ADC consist of an oscillator, the ∆ Σ modulation phase readout, and Cascade Integrator Comb filter It works as single-ended converter, consumes 0.97 mW and occupies 0.08 mm2

in the Skywater 130

nm CMOS technology According to simulation results, our work can reach SNDR of 79 dB at 0.1 Vpeak and SNDR

of 58 dB at 0.4 Vpeak, which also obtain SNDR of 74

dB for bandwidth below 50 KHz Our ADC can adapt the demand of MEMS microphone and variety sensors with 13-bit ENOB at the bandwidth of 24.4 KHz and 12-bit ENOB

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TABLE I: PERFORMANCE SUMMARY AND COMPARISON WITH PRIOR ART

-for multi-application below the bandwidth of 50 KHz From

the comparison inV, our ADC has the highest SNDR, but the

power consumption is quite high In future work, we will focus

on reducing the power of this proposal to save energy for IoT

devices

ACKNOWLEDGMENT

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