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Báo cáo thực hành lap chương 6 thiết kế vi mạch theo chuẩn đại học bách khoa thành phố hồ chí minh

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Tiêu đề Báo cáo thực hành lab chương 6 thiết kế vi mạch theo chuẩn đại học bách khoa thành phố hồ chí minh
Tác giả Hoàng Văn Doanh
Người hướng dẫn Trương Quang Vinh
Trường học Trường đại học Bách Khoa Thành phố Hồ Chí Minh
Chuyên ngành Thiết kế Vi mạch
Thể loại Báo cáo thực hành
Năm xuất bản 2022
Thành phố Thành phố Hồ Chí Minh
Định dạng
Số trang 61
Dung lượng 3,15 MB
File đính kèm thuc-hanh-lap-chuong-6.rar (2 MB)

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Nội dung

Báo cáo thực hành lap chương 6 thiết kế vi mạch theo chuẩn đại học bách khoa thành phố hồ chí minh Báo cáo thực hành lap chương 6 thiết kế vi mạch theo chuẩn đại học bách khoa thành phố hồ chí minh Báo cáo thực hành lap chương 6 thiết kế vi mạch theo chuẩn đại học bách khoa thành phố hồ chí minh Báo cáo thực hành lap chương 6 thiết kế vi mạch theo chuẩn đại học bách khoa thành phố hồ chí minh

Trang 1

ĐẠI HỌC QUỐC GIA TP HỒ CHÍ MINH

TRƯỜNG ĐẠI HỌC BÁCH KHOA

Trang 2

Thí Nghiệm Số 4:

THIẾT KẾ MẠCH AOI22

Tên người thực hiện PROJECT: HOÀNG VĂN DOANH_1912858

1 Tổng Quan Lý Thuyết

Giới thiệu sơ đồ mạch lý thuyết

Hình 1.2 Sơ đồ mạch lý thuyết cho mạch AOI22

Hình 1.2 Sơ đồ cổng Logic của AOI22

Trang 3

2.TRUTH TABLE:

2 Thực hiện thiết kế Schematic:

2.1 Mạch thiết kế cấp CMOS và PMOS

- Chọn NMOS và PMOS để thiết kế mạch AOI22

Hình 2.1 Mô phỏng mạch Schematic AOI22 với LP/N=180nm và WP/N=2um

Trang 4

Hình 2.2 Mô phỏng mạch Schematic AOI22 với LP/N=258nm và WP/N=5um

Hình 2.3 Mô phỏng mạch Schematic Symbol AOI22 với LP/N=180nm và WP/N=5um

Trang 5

Hình 2.4 Mô phỏng mạch Schematic Symbol AOI22 với LP/N=258nm và WP/N=5um

2.2 Thực hiện mô phỏng Transient để khảo sát dạng sóng của tín hiệu ngõ ra thay đổi như thế nào khi 4 ngõ vào thay đổi (có tất cả 16 trường hợp cần khảo sát khi 4 ngõ vào cùng thay đổi) trong 2 trường hợp sau:

TH1: LP/N = 180nm, WP/N = 2um và Cload = 58 fF

Mạch mô phỏng, kiểm tra

1 Cung cấp điện áp vào symbol thiết kế, tạo thành sơ đồ mạch testbench mô phỏng

- Nguồn cấp cho AOI22là DC: 1.8V

- Nguồn xung cho tín hiệu là xung vuông

Trang 6

Hình 2.5 Mạch testbench mô phỏng AOI22 TH1

Hình 2.6 Kết quả dạng sóng ngõ ra theo Tran

Trang 7

TH2: LP/N = 258nm, WP/N = 5um và Cload = 58 fF

Mạch mô phỏng, kiểm tra

1 Cung cấp điện áp vào symbol thiết kế, tạo thành sơ đồ mạch testbench mô phỏng

- Nguồn cấp cho AOI22là DC: 1.8V

- Nguồn xung cho tín hiệu là xung vuông

Hình 2.7 Mạch testbench mô phỏng AOI22 TH2

Hình 2.8 Kết quả dạng sóng ngõ ra theo Tran

Trang 8

3 Thực hiện đo Cell Rise/Fall Delay và Rise/Fall transition cho mạch AOI22 trong 2

trường hợp trên:

TH1: LP/N = 180nm, WP/N = 2um và Cload = 58 fF

- Thay đổi ngõ vào A:

Hình 2.9 Mạch thực hiện đo Cell Rise/Fall Delay và Rise/Fall transition AOI22 khi thay đổi ngõ

vào A

Hình 2.10 Kết quả đo Cell Rise/Fall Delay và Rise/Fall transition AOI22

Sóng ngõ ra:

Trang 9

File netlist:

// Generated for: spectre

// Generated on: May 28 11:43:02 2022

// Design library name: DoanhHoang_1812858

// Design cell name: AOI22_testbench_A_180

// Design view name: schematic

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmvar

Trang 10

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rtmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_disres

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfesd

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_mim

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_fmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfres_rpo

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmim

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_res

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_bip

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_bip3

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio3

Trang 11

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_3v

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_na

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio_m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfind

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio_3m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_bbmvar

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfres_hri

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_3vna

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio_dnw

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_3m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfjvar

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmos

Trang 12

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfsbd

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmvar_33

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmos33

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rffmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=stat_noise

// Library name: tsmc18

// Cell name: AOI22

// View name: schematic

subckt AOI22 A B C D GND OUT VDD

M10 (net25 B VDD VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M8 (OUT D net25 VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M1 (OUT C net25 VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M0 (net25 A VDD VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M9 (net27 D GND GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

Trang 13

M7 (OUT C net27 GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M3 (net26 B GND GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M2 (OUT A net26 GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

ends AOI22

// End of subcircuit definition

// Library name: DoanhHoang_1812858

// Cell name: AOI22_testbench_A_180

// View name: schematic

- Thay đổi ngõ vào B:

Hình 2.11 Mạch thực hiện đo Cell Rise/Fall Delay và Rise/Fall transition AOI22 khi thay đổi

ngõ vào B

Trang 14

Hình 2.12 Kết quả đo Cell Rise/Fall Delay và Rise/Fall transition AOI22 khi thay đổi ngõ vào B

Sóng ngõ ra:

File netlist:

// Generated for: spectre

// Generated on: May 28 12:12:00 2022

// Design library name: DoanhHoang_1812858

// Design cell name: AOI22_testbench_A_180

// Design view name: schematic

simulator lang=spectre

Trang 15

global 0

parameters Vin=1.8 VIN=1.8

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfres_sa

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmvar

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rtmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_disres

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfesd

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_mim

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_fmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfres_rpo

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmim

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_res

Trang 16

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_bip

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_bip3

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio3

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_3v

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_na

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio_m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfind

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio_3m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_bbmvar

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfres_hri

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_3vna

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio_dnw

Trang 17

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_3m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfjvar

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmos

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfsbd

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmvar_33

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmos33

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rffmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=stat_noise

// Library name: tsmc18

// Cell name: AOI22

// View name: schematic

subckt AOI22 A B C D GND OUT VDD

M10 (net25 B VDD VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M8 (OUT D net25 VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M1 (OUT C net25 VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

Trang 18

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0

M0 (net25 A VDD VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0

M9 (net27 D GND GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0

M7 (OUT C net27 GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0

M3 (net26 B GND GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0

M2 (OUT A net26 GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0

ends AOI22

// End of subcircuit definition

// Library name: DoanhHoang_1812858

// Cell name: AOI22_testbench_A_180

// View name: schematic

I8 (net02 INPUT 0 0 0 OUTPUT net9) AOI22

V19 (INPUT 0) vsource dc=Vin type=pulse val0=0 val1=VIN period=30n delay=0 \ rise=10p fall=10p width=15n

V20 (net02 0) vsource dc=1.8 type=dc

V4 (net9 0) vsource dc=1.8 type=dc

C0 (OUTPUT 0) capacitor c=58f

simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \

Trang 19

tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile=" /psf/sens.output" \

checklimitdest=psf

tran tran stop=100n write="spectre.ic" writefinal="spectre.fc" \

annotate=status maxiters=5

finalTimeOP info what=oppoint where=rawfile

modelParameter info what=models where=rawfile

element info what=inst where=rawfile

outputParameter info what=output where=rawfile

designParamVals info what=parameters where=rawfile

primitives info what=primitives where=rawfile

subckts info what=subckts where=rawfile

saveOptions options save=allpub

Trang 20

- Thay đổi ngõ vào C:

Hình 2.13 Mạch thực hiện đo Cell Rise/Fall Delay và Rise/Fall transition AOI22 khi thay đổi

ngõ vào C

Hình 2.14 Kết quả đo Cell Rise/Fall Delay và Rise/Fall transition AOI22 khi thay đổi ngõ vào C

Sóng ngõ ra:

Trang 21

File netlist:

// Generated for: spectre

// Generated on: May 28 12:20:44 2022

// Design library name: DoanhHoang_1812858

// Design cell name: AOI22_testbench_C_180

// Design view name: schematic

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmvar

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rtmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_disres

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt

Trang 22

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfesd

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_mim

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_fmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfres_rpo

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmim

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_res

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_bip

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_bip3

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio3

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_3v

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_na

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio

Trang 23

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio_m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfind

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio_3m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_bbmvar

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfres_hri

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_3vna

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_dio_dnw

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_3m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfjvar

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmos

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfsbd

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmvar_33

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rfmos33

Trang 24

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=tt_rffmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr018gpii_v1d0.scs" section=stat_noise

// Library name: tsmc18

// Cell name: AOI22

// View name: schematic

subckt AOI22 A B C D GND OUT VDD

M10 (net25 B VDD VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M8 (OUT D net25 VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M1 (OUT C net25 VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M0 (net25 A VDD VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M9 (net27 D GND GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M7 (OUT C net27 GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M3 (net26 B GND GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

Trang 25

M2 (OUT A net26 GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

ends AOI22

// End of subcircuit definition

// Library name: DoanhHoang_1812858

// Cell name: AOI22_testbench_C_180

// View name: schematic

I8 (net02 0 INPUT net04 0 OUTPUT net9) AOI22

- Thay đổi ngõ vào D:

Hình 2.15 Mạch thực hiện đo Cell Rise/Fall Delay và Rise/Fall transition AOI22 khi thay đổi

ngõ vào D

Hình 2.16 Kết quả đo Cell Rise/Fall Delay và Rise/Fall transition AOI22 khi thay đổi ngõ vào D

Trang 26

Sóng ngõ ra:

File netlist:

// Generated for: spectre

// Generated on: May 28 12:27:08 2022

// Design library name: DoanhHoang_1812858

// Design cell name: AOI22_testbench_C_180

// Design view name: schematic

Trang 27

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfmvar

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rtmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_disres

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfesd

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_mim

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_fmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfres_rpo

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfmim

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_res

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_bip

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_bip3

Trang 28

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_dio3

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_3v

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_na

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_dio

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_dio_m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfind

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_dio_3m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_bbmvar

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfres_hri

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_3vna

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_dio_dnw

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_3m

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfjvar

Trang 29

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfmos

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfsbd

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfmvar_33

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rfmos33

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=tt_rffmom

include

"/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spec tre/cr018gpii_v1d0.scs" section=stat_noise

// Library name: tsmc18

// Cell name: AOI22

// View name: schematic

subckt AOI22 A B C D GND OUT VDD

M10 (net25 B VDD VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M8 (OUT D net25 VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M1 (OUT C net25 VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

sca=0 scb=0 scc=0

M0 (net25 A VDD VDD) pch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \

as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \

Trang 30

sca=0 scb=0 scc=0

M9 (net27 D GND GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0

M7 (OUT C net27 GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0

M3 (net26 B GND GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0

M2 (OUT A net26 GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0

ends AOI22

// End of subcircuit definition

// Library name: DoanhHoang_1812858

// Cell name: AOI22_testbench_C_180

// View name: schematic

I8 (0 0 net02 INPUT 0 OUTPUT net9) AOI22

V23 (INPUT 0) vsource dc=Vin type=pulse val0=0 val1=VIN period=30n delay=0 \ rise=10p fall=10p width=15n

V22 (net02 0) vsource dc=1.8 type=dc

V4 (net9 0) vsource dc=1.8 type=dc

C0 (OUTPUT 0) capacitor c=58f

simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \

tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile=" /psf/sens.output" \

checklimitdest=psf

tran tran stop=100n write="spectre.ic" writefinal="spectre.fc" \

Ngày đăng: 06/02/2023, 15:48

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