ứng dụng công nghệ FPGA cho xây dựng hệ thống điều khiển đèn giao thôn

FPGA ra ddi nham biln tat ca mpt h| thong so co tflc do cao, tin cay vdi kha nang xu ly tin hilu sfl, thuc hien chuc nang logic, thuc hien he thflng nhiing va ddc biet vdi kha ndng tiiy

^^"^ X U^G DUNG C 6 N G N G H E FPGA CHO

/ O \ XAV DlTNG HE THONG DIEU KHEfeNBfeN GIAO T H 6 N G

°\ / FPGA TECHNOLOGY APPLICATION FOR

'"""^ CONTROLLING OF TRAFFIC LIGHT SYSTEM

Pham Thi Nggc Anh, Ll Bd Dung

Tru&ng Dgi hpc Suphgm Ky thudt Hung Yin

Tom tdt:

Bdi bdo trinh bdy ve cdu tnic FPGA hi thdng phdn cung thiit ki cho ung dung FPGA Viec dp dyng

hi xu ly da nhiem, phdn mim da tde vu th&i gian thuc duac tich hgp vdo FPGA la npi dung chu yiu cua bdi bdo Kit qud nghien euu dd dugc thu nghiim trin md hinh dieu khien mdt mit giao thdng vd ddp ung dugc yeu cdu de ra

Tir khda: FPGA, da nhiem, th&i gian thuc thudt todn diiu khiin

1 Mddau:

Ngdy nay, khi trinh dp khoa hpc va cong

nghe thi gifli dang phat trien manh me va rflng

khap mpi linh vuc dac biet ttong cflng nghe che

tao IC Mpt trong nhiing thanh qua dang ghi nhan

ciia su phat triln ay la su ra ddi ciia cac vi mach

logic kha trinli FPGA FPGA ra ddi nham biln tat

ca mpt h| thong so co tflc do cao, tin cay vdi kha

nang xu ly tin hilu sfl, thuc hien chuc nang logic,

thuc hien he thflng nhiing va ddc biet vdi kha ndng

tiiy biln cao ve phan cung vao ttong mflt chip; bin

canh dfl FPGA cfln dflng vai ttfl la cac phien ban

nay da dem lai nhdng lpi ich thiet thuc va to Ion

cho cac nhd thilt kl IC ciing nhu khach hang su

dung Chinh vi dieu dfl, FPGA ngay cang chilm thi

trin toan thi gioi Chinh vi vay viec dp dung cflng

nghe FPGA vao phuc vu dfli sflng ttd len rat hiiu

ich Bai bao trinh bay ve ung dung cflng nghi FPGA

xay dung h | thflng dilu khien den giao thflng Bai

bao bao gflm cac phan: l,Md dau; 2,HI thflng phan

Cling FPGA; 3,Phan mem da nhilm thdi gian thuc;

4,Thuc nghiim; 5,Kit luan

2 Hf thong ph^n cung FPGA

2.1 Cflng nghe FPGA

FPGA dupc dua ra gidi thieu ldn ddu tien

giiia nhimg nam 1980 bdi Xilmx FPGA la hi viit tdt

cua Field Programmable Gate Arrays - Mang cflng

cung nhu cac thiit bi PLD khac Nhiiu FPGA hien

dai cfl kha nang de lap trinh lai ttong khi dang boat

dpng, va dieu nay rat quan ttgng cho y tudng cua

phli hop cho cac boat dgng tilp theo Kiin true ca

ban ciia mgt FPGA gflm co:

• Cdc khoi logic cfl the cau hinh lai duoc

-CLB (Configuable Logic Blocks)

• Ma ttdn chuyen mach (Swith Matrix) de kit nfli cdc CLBs - kit nfli lap trinh dugc

• Cac khfli vao ra - lOB (In/Out Blocks) 2.2 H^ thing ph4n cihig thilt ke cho hi thi nghifm diiu khiin den giao thong

He thflng phan cung thilt kl cho hi thi nghiim dilu khien den giao thong co the thay tten hinh 1 bao gflm:

Hinh 1 Kit thuc hdnh FPGA FTKIJ 0

• FPGAXC3S250E

• LCD Character 1602M, LCD character cfl kha nang hiin thi 2 hang vdi 16 ky tu tten mfli hang LCD dugc kit nfli true tiip vdi FPGA qua 12 chdn tin hieu

• Hiin thi 3 sfl vdi LED 7 thanh, khfli hiin thi 3 sfl vdi 3 LED 7-thanh Cac LED 7-thanh su dung chung dudng bus 8-bit tin hieu diiu khiin hiin thj tu FPGA

• Ban phim ma ttdn 4X5

• Bd thuc hanh FTKII.O cung cdp mgt ban phim ma ttan 4 cflt 5 hang

• Hiin Ihi LED va cflng tdc JUMP cung cdp cho ngudi su dung 7 LED va 1 cong tdc jump xip thanh hdng ngang a vi tri phia dudi ben phai

• Bo chuyen dfli ADC 8-bit su dyng ADC0809 kit nfli vdi FPGA thdng qua cac bg chuyin ddi diln ap tu TTL sang LVTTL hoac

LVCMOS

3 Thiet ke he th6ng da nhi^m thdi gian t h g c

3.1 H^ thong da nhifm, da tdc vu thcri gian t h u c

Y tudng CO bdn ciia tbdi gian thuc t h i hien

d chfl, mpt he thflng phai cfl nhiing phdn ting thich

hgp, dung thfli diim vdi mfli truong ciia nfl Thfli

gian thgc cfl nghia "du nhanh" ttong mpt ngu canh,

ttong mflt moi truflng md he thflng dang hoat dgng

Thgc chdt ciia viec tinh todn thfli gian thuc khflng

chi d viec phan ung du nhanh ma cfln phdi dang tin

cay va chinh xac Viec xay dung mdi hoan toan mgt

he thong thdi gian thuc se mit rdt nhiiu thdi gian va

cflng sue [1, 2]

_ Y ttrong c a ban ciia da tac vy la: chiing ta

cfl thi phdn chia mpt vin d i ldn thanh cac nhdnh

nhfl va don gian hem d i giai quyit Mfli mflt vin d i

con trd thanh mdt tac vu - task Mfli mgt tac vu chi

lam mgt vile ciia chinh no Trin thuc t i , cac tac vu

khong bao gid chay song song neu chung ta khflng

cfl mgt he thong da vi xii ly Trong truflng hgp dang

xet, cac tac vu se chia se mOt bfl Vi dilu khiin

Ciing giflng nhu cac chuang ttinh khac, mgt

tac vu bao gflm ma lenh d l thuc hien cac chuc nang

ma tac vy phai thuc hien (do ngudi lap trinh thiit

ki) Ma lenh dugc chda ttong mflt ham tuong ty

nhu hdm main() trong ngfln ngir leip trinh C Dilu

lam nen sy khac biet ciia tac vy chinh la ngu canh

chua ttong ngan x i p cua no [3, 4]

Hinh 2 Cdu trdc cua Task

Nhu vdy, mflt tac vy bao gflm:

• Ma ngufln chda cac chdc nang ciia tac vy

• Mflt ngan x i p - stack de chua ngu canh

(context) cua dii lieu

• Mgt hop thu - mailbox (tuy chpn) d l phuc

vy cho vile truyin thflng vfli cac tac vu khac

Vi dy doan ma sau milu ta cau tnic ma

nguon cua mflt tac vy Dfli sfl data dung de tham so

doi sfl argv va argc ttong bam main() vfli ngfln ngii

C Dfli sd nay thuc su quan ttgng ttong trudng hgp

nhdt cua tac vy dugc thi hi?n bfli gid tri ciia dfli sfl

n a y

Void task (void *data)

{ init task();

While (TRUE)

{ Wait for message as task mainlbox();

Switch (message type) {case M E S S A G E T Y P E X ; Break;

Case M E S S A G E T Y P E ^ Y Break;

} } } 3.2 Lich trinh (Scheduhng) Cac tac vy (task) boat dflng dufli sy giam sat ciia nhan kemel thfli gian thyc Chimg bao gflm:

• Mpt tap hpp cac dich vy thyc hien cac cong viec nhu dflng bfl boa va giao tiip truyin thflng giua cac tac vu

• Mgt bp lap lich (scheduler) vdi chuc nang khang dinh rang chi cfl duy nhat tac vu vdi muc uu tien cao nhat dang dugc thyc thi

Bp lap hch xet cac tac vy nhu nhiing cai may trang thai (state machme) Tdt ca cac kemel diu cd mfl hinh ttang thai ciia nfl, tuy nhien, thflng thudng thi cdc mfl hinh ttang thai nay rdt phuc tap Hinh 3 chi ra cho thay mflt mfl hinh trang thai mang tinh khai niem cua tac vu

Hinh 3 Md td trgng thdi ciia cdc tdc vu

Trong hinh 3, ta thay cfl cac ttang thai:

• Dang t h u c thi (Running): Chi cfl duy nhat mpt tac vy la dugc nam ttong trang thai nay

Mpt tac vu cfl the ty dflng chuyin tu ttang thai Dang

thuc thi sang ttang thai Khoa (Blocked) bang viec

chd dpi mgt sy kiln xay ra Trong mgt he thong cfl

su chilm quyen thuc thi (chiing ta se de cap d i n

no sau), bfl lap lich co the bat mflt tac vy dang d

ttang thai Dang thue thi xuflng ttang thai Sdn sdng

(Ready) n i u cfl rapt tdc VTI VOI muc uu tien cao hon

chuyen den trang thai Sdn sdng Chung ta gpi no la

sy chiem quyen thyc thi (preemption)

• San sdng (Ready): NIu mflt tac vy da san sang de hoat dgng nhimg lai co muc uu tien thap ban tac vy dang thuc thi, tac vy do se dugc chuyen din ttang thai nay va chd Tac vu nay se

dupc chuyen den ttang thai Dang thuc thi neu nfl trd

thanh tac vy cfl muc uu tien cao nhat

• Khoa (Blocked): Mflt tac vu bi khoa la tac

vy dang dgi mpt sy kiln nao do xay ra, vi dy nhu

mflt ban tin, tin nhan dugc gui din hop thu cda tdc

vy dfl, hay thdi gian chd cda tac vu kit thiic

3,3, Tich hgp phdn mem da tac vu vao FPGA

3.3.1 Cac thuc the cua Vi dilu khiln

Cac Modules thyc the ciia bfl Vi dieu khiln

cdn cfl de nhung vao FPGA [4] bao gom:

• Modul thyc the chia tdn

• Module thyc thi Vi dieu khien

• Module thyc thi RAM

• Module thyc the chuang trinh da tac vy

Tuy theo thiet kl, cac Modules nay cfl the

viet tten VHDL, verlog, hoac viet tren C Trong

hi thi nghiem nay chung tfli su dyng 2 ngfln ngu la

VHDLvaC

3.3.2 Thiet ke cbirong trinh dilu khien da tdc vg

Tren Hinh 4 la milu ta so dfl thuat toan cho

hi thflng xu ly da tac vy

// Chap nhdn ngat // Tao TASK 1

}

4 iTng dung he da tdc nghiep cho dieu khien mot nut giao thdng danh cho ngirdi di b$ 4.1 Thiet ke phan cung cho thi nghiim

So dfl tflng quan ciia he thflng thiet ke phan cdng ttIn hinh 5

Bat Dau

" '

Khoi tao Salvo cung cac ttianh ghi

' '

Tao cac TASK

' '

Dmh thcri cac TASK

" '

Chay TASK thich hop

Hinh 5 So dd tdng quan ciia he thdng

De xdy dung mpt he xu ly da tac vy cho dieu Idiien cac den xanh do va bfl dim cho mgt niit giao thflng, chung tfli thyc hien nhu sau:

^ Hinh 4 Sa do thudt todn

So dfl dugc cai dat nhu sau:

void main( void)

{ //ciu hinh choTIMER)

//Chip nhan ngdt TIMERO

Khoa hoc & Cong nghe - S6 3/2014

Hinh 6 So dd thudt todn cho mdt tdc vu

* Mdi mflt hudng di la mpt tdc vu cho thuc

hien cdc cdng vile (Hinh 6)

- Bat den xanh hay do

- Thuc hiem dim lui theo mflt khoang thdi

gian nhdt dinh cho thdi gian dgi hay thdi gian duoc

phep di

* Mfli mflt nut giao thflng cfl the co den 5 tac

vy,

* Khd ndng thyc hien so lugng ldn cac tdc vu

phu thupc vao thdi gian xu ly cua bd Vi dieu khien

Trin bmh 7, 8 cho thdy kit qua thu nghiim

nhung he xii ly da tac vu vao FPGA chay tren phdn

cung thiet ke sir dung FPGA,

Hinh 7 Md td kit qud thuc hiin hai tdc vu tren kit

FPGA

Hinh 8 Md hinh kit ndi phdn cung bin ngodi

5 Ket luan

Bai bao trinh bay ung dung cflng nghe FPGA cho dieu khien den giao thflng trong cac thdnh phfl Ion Vile tich hgp he thong da nhiem da tac vy thflng qua xdy dyng thuat toan de dieu khien mflt diem nut giao thflng la mgt ttong cac nghien ciiu

ap dung cflng nghe FPGA hien nay Nghien cuu, dp dung cflng nghe FPGA la mflt hudng nghien cuu mfli, rat cfl y nghia ttong dieu khiln, cung nhu xay dung va thiet ke cac he thflng nhiing Tiep can tten cho phep khai thac dugc thi manh ciia ky thuat lap trinh va phan cung ciia cong nghi

Tli lieu tham khao

[1] Ll Ba Diing, Bg vi dieu khiin PIC16F84 vdphdn mem tdc nghiip thoi gian thuc cho thu thdp xir ly da lieu vd dieu khien Tap chi Khoa hpc cflng nghe (6 truflng DH)

[2] Le Ba Dung, Bui Nguyen Dai, A real time multitasking operating software based on IBM PC for data acquisition, processing and control', The Sixth National Conference on Automation VICA

6, Ha nfli, 2005 P

[3] LIBdDung, Bui Nguyin Dai, Trdn Thi Hoang, Xay rfimg/fe (/longn/zMng^flrt/i/ew vd thiit ki mdy tinh don Board vol vi xir ly Intel x86,Tuy&n tap Hoi thao CJ^TT, Hai Phong, 2005 [4] LeBaDung, Bdo cdo de tdi "Thiit ki Bd xu ty chuyen dung cho do luang vd dieu khiin",Yiea

KH&CN Viet Nam 2009

Abstract:

This paper presents the FPGA architecture, system hardware design for FPGA applications The

Khoa hgc & Cong nghf - So 3/2014 Journal of Science and Technology

application of multitasking, multiprogramming real-time software is integrated into FPGA that is the main contents of this paper The research results have been tested on a control model intersections and satisfies the request purposes

Keywords: FPGA multitasking, real-time, control algorithm

Ngudi p h a n bien: T S Bui lYung Thdnh

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