ứng dụng thiết bị mảng cổng khả trình FPGA của xilinx trên cơ sở sử dụng công cụ ise foundation

DAT VAN DE Da cd mdt sd kfi't qua nghifin cflu trong vific tridn khai flng dung cdng nghfi CPLD Complex Programmable Logic Device trong thuc tifin.. Chi'nh vi vdy vific ldm chu cdng nghf

Hd Ngi, 11 - 2005

.^ LJTNG DUNG THIET Bj MANG CONG KHA TRINH FPGA CUA XILINX TREN CO s d Str DUNG CdNG CU ISE FOUNDATION

Phan Qud'c Thdng, Phgm Tudn Hdi, Le Trgng Nghia

Hgc vien KyTfnidt Qudn Su

Tdm tdt:

Bdi hdo gidi t/deu mgt so cdng nghe cff bdn FPGA (Field Programmable Gate Arrays) cua Xilinx phucfng phdp trien khai thuc te'khi thiic hien bdi todn dieu khien, ndi ghep vdi mdy tinh xdy dUng chuang trinh, xdy dipig giao diin trong thUc tevd trien khai ifng dung trong hdi todn diiu khien dgng ca budc cung mgt sdket qud dgt dugc Trong bdi sit dung bo mgch Spartan3 Starter Kit de dieu khien ddng ca budc vdi md ta dugc chgn Id 7.5" budc, dien dp cdp cho dgng ca la 5V

I DAT VAN DE

Da cd mdt sd kfi't qua nghifin cflu trong vific tridn khai flng dung cdng nghfi CPLD (Complex Programmable Logic Device) trong thuc tifin Tuy nhifin, dd'i vdi cac flng dung phflc tap hon, cdng nghfi CPLD ddi khi gap phai mdt sd ban chd nhd't dinh Chi'nh vi vdy vific ldm chu cdng nghfi FPGA cQa Xilinx Id didu cdn thidt, giup cho cac nha thifi't kfi' cd them cdc giai phap tdi uu khi giai quydt cac bai toan flng dung phflc lap Xud'l phdt tfl thflc

te dd, bai bdo mud'n di sdu nghifin cflu vd cdng nghfi FPGA cua Xilinx, lim hidu mdi trudng thiet kd ISE Foudation cung nhu vific tridn khai flng dung trong thuc tfi'

n CONG NGHE FPGA CUA XILINX

Tfl nam 1985, bang Xilinx da dd xud't mOt y tudng mdi dd la kfi't hop gifla kha nang thifi't kd cua ngudi dung cdc chip cd mdt dd tfch hgp cao, gia thanh ma trdn cdng ha va rut

ngdn thdi gian dua san phdm PLD {Programmable Logic Device) ra thi trudng Ddy la

nhflng CO sd ddu tifin ra ddi cac thifi't bi FPGA Cho dfi'n nay Xilinx vdn la nha phdn phdi sd

1 trfin todn thd gidi vd hg thifi't bi nay

Cd'u true FPGA bao gdm cac cdng logic (Logic Cell) va cac khd'i module va cac dudng nd'i (hlnh 1) Cac dudng nd'i ddu dugc ngudi dung kidm soat, cd nghTa ngudi dung cd thd thidt kfi', lap trinh va thay ddi mach mdi khi cdn thie't Vdi hg FPGA ngay nay kha nang lich hgp da vugt qua gidi ban 10 trifiu cdng (Hg Xilinx Virtex™- II va Virtex™- 4 FPGA hifin dang giu ky luc)

Cd hai loai FPGA co ban: Loai SRAM (Static Random Access Memory) cd thd Idp trinh lai nhidu ldn va loai OTP (One - Time Programmable) ldp trinh mdt ldn

Hai loai nay khac nhau d chd thuc hifin cua cdc logic cell vd ky thudt tao kfi't ndi gifla chflng trong thifi't bi Loai hay dflgc dung hon ca la loai SRAM, vi cd thd lap trinh duoc nhidu ldn Thuc id thi FPGA SRAM dugc nap cd^u hinh Iai mdi khi bat ngudn, bdi vi FPGA loai ndy thuc chd't la mdt chip nhd

» -» -» m » '

" " • " " ! " * " I ' 1J^'.4-tir" ~m-~.'.'

m w » » * , m » •• * _»_

• • r : - - - i » - - - : _ > _ : : - _i» ;• * ; ; •

:fc|.ii:-i:;:]:l::::l::::

- 5 - 4 -»-{•• g - i - - - S •• -S •

Hinh 1 Cau true cua FPGA

CUA XILINX

ISE Foudation cua Xilinx cai thifin dang

ke thdi gian dua san ph^m ra thi trudng nhd

rut ngdn dugc thdi gian thie't kfi' ISE

Foudation bao gdm phdn mdm thifi't ke va cdc

phan mdm bd sung khac Vific thuc hifin thifi't

ke bdng cdng cu ISE Foundation gdm cdc

budc nhu sau:

Nhap thidt ke

Cac cfing cu hd trg dd tao ra mdt thifi't kd

bao gdm: Nhdp ihifi't kfi' bdng so 66 hoac bang

ngfin ngfl HDL, bang viec tfch hgp cac Idi IP

Cdc cdng cu thie't kfi' bao gdm; Schematic Editor, HDL Editor State Diagram Editor, Core Generator System, PACE (Pinout and Area Constraint Editor), Architecture Wizard (DCM - Digital Clock Management MGT - Multi-Gigabit Transceiver), Xilinx System Generator for DSP

Tdng hgp thidt ke

Sau giai doan nhdp thifi't kd se la budc tdng hgp thifi't kd

Dua trfin bd tdng hgp mdi, ISE cho phep td'i uu hod trong qua trinh tdng hgp thie't ke cac PLD Bd tdng hgp cd kha ndng ldi flu boa cao mdt thidt kd trong mdt thdi gian ngdn

ISE tfch hgp cac bd tdng hop nhfl sau: Mentor Graphics Leonardo Spectrum, Exempla, Synopsys vd Synplicity SynplifylPro ABEL, AST (Xlinx Synthesis Technology)

Thuc thi va n a p cau hinh

Vific thuc hifin thifi't kd logic kha trinh la gdn cdc chfle ndng logic dflgc tao ra trong qud trinh nhdp thifi't kd va tdng hgp chung vao trong tai nguyfin vdt ly cu thd Thudt ngfl

"Sdp ddt vd dinh tuyen " dugc sfl dung dd md la qua trinh thuc hifin cho FPGA, cdn "Ldp

dat " dugc sfl dung cho CPLD Thuc thi chi'nh la qua trinh nap cd'u hinh cho thifi't bj De

thuc hifin ndi dung nay cd cdc cdng cu hd trg sau: FloorPlanner, Constraints Editor, Timing Driven Place & Route, Modular Design, Timing Improvent Wizard

Tich hgp mflc Board

Phdn mdm ISE hd trg ngudi dung Ihuc hifin thifi't kd logic lap trinh lam vific trong hfi thd'ng vdi mdt loat kha nang nhu bd tri, sap dat board mach kd ca board mach phflc tap, tong hgp tfn hifiu, giao tiep bus td'c dd cao, xac dinh dd rdng dai thdng vao ra, nhidu difin

tfl D6 cd thd dfi dang thuc hifin cdc budc nay Xilinx da sfl dung nhidu cdng nghfi mdi tren

FPGA nhu:

- XCITE Trd khang didu khidn sd

- DCM Bd quan Iy ddng hd sd thdi gian hfi thdng

- EMI Bd quan Iy nhidu difin tfl trflfiing

- Thdng tin ddng gdi lich hgp d mflc Board

- Kifi'm tra mflc Board ISE

Cac cdng nghe trfin dugc thuc hifin nhd cac gdi phdn mdm sau;

- IBIS Models

- STAMP Models

- LMG Models

- ChipScope ILA

Phdn mdm ISE cho phep thuc hien kifim tra d tat ca cdc giai doan cua thie't kfi' bat ddu Ifl khau nhap thie't kd cho de'n khi tieh hgp board

* Kiem tru tuili: Cdng cu kidm tra tmh cho phep ngudi thie't kc kidm tra thiet ke

ngoai yfiu cau Viec kidm tra cd thd thuc hifin d mgi khia canh hoac kidm tra theo su chon lira, cho phep tim ldi trong qua trinh thuc thi Cdng cu kiem tra tinh cung cho phep thuc hien go rdi va phan tfch Cac cdng cu kifim Ira tinb gdm:

- Constraint Editor

- Delay Calculator

- Trace

- Timing Analyzer

- Prime Time

- X Power

- Formality

- Conformal " LEC

- D R C

- Chip Viewer

* Kidm tra ddng: Bao gdm cac cdng cu sau

- H D L Bencher'"

- ModelSim XE

- State Bench

- HDL Siinulalion Libraries

* Kiem tra mflc Board; Vific sfl dung cdng cu kidm tra mflc board nhdm dam bao viec thifi't ke dugc thuc bien diing theo du dinh va dugc tfch hgp vdi phdn cdn Iai ciia he Ihdng Cac cdng cu nay bao gdm:

- IBIS Models

- Tau

- BLAST

- Stamp Models

- Impact

IV T H U t HIEN NHIEM VU DIEU KHIEN DUNG CONG NGHE FPGA XILINX Phdn nay bai hao trinh bay viec flng dung cdng nghfi FPGA va phdn mdm ISE Foundation dd didu khifin ddng co budc cd ghep ndi vdi may tfnh Vific ghep nd'i vdi may tfnh ddi hdi chuong trinh phai dugc thie't ke mdt bd UART dd nhdn dfl lieu tfl may ti'nh PC Thdng Ihudng khi thifi't kfi' phan cflng, can sfl dung vi mach chuydn ddi mflc Max232, Max3232 UART 1640 hoac 1650

Chuong trinh dieu khien

Nhiem vu dat ra la can thiet ke' bd UART kfi't hgp vdi module didu khie'n ddng co budc nhu da nfiu d tren Chuong trinh sfl dung ngdn ngfl Visual Basic

Chiing ta cd thfi l;"iy du lieu tfl mach phan hdi ciia ddng co dd xfl ly trong mdy tfnh Trfin form chuong trinh, sau khi kfch chugt vao mil nhan thi chuong trinh se truydn cac

Byte du lieu qua cdng COM 1 vdi khudn mdu truyen ddt sdn la "9600.N,8,1" [Chifong trinh ndy dd diffft thd nghiem ghep nd'i vdi bd vi M} ly 89C51 vd FPGA Spartan3 XC3S200

-nhu trfin Chuong trinh difiu khidn nay dugc vifi't dudi dang mdt Form dan vdi sau mil nhd'n

nhu sau:

- Start: Khdi ddng Motor

- Left, Right: Dung dd dao chidu ddng co

Niit Slow/Fast; Dung dd tang giam td'c dd ddng CO

W B I ! i l H W ^ " l ^ ^ ^ * ^ ^ i ^ ^ l l ^

h4ok>r dk/nto/

-ji SLOW 1 FAST 1

LEFT RIGHT

St^ Motor fDontroH&r Ciestgnedt^

Fiwm Tuan Na/-MasterC>?iffse 16

MMa/y Tschn/ca!.Acadsn}/

START ^ ^ H

Hinh 2 Giao dien khdi dieu khien Motor va so do ghep noi

pm-rs232-td

Modul 1 0 XC3s200

Starl/Slop

Cnt-Dir

Inc/Dee

Modul Step-Motor

Led Sec [3:0] Led]

Hinh 3 So dd noi ghep Modul dieu khien vdi may tfnh

Thiet ke bd UART: De thie't ke' Modul UART, nhdm tac gia thifi't kd mdt Modul chi'nh va hai modul con vdi cdc tfin file nhu sau

- Modul UART.vhd: Modufi chi'nh chiia cac Module thanh phdn

- Modul Rx.vhd: Modue dung dfi lam bd thu dtt lifiu khdng ddng bd

- Modul Tx.vhd; Module diing dd thuc hifin bd phat dfl lieu khdng ddng bd

- Modul Counter.vhd: Dung de tao ddng hd Baudrate, khi thie't ldp td'c dd Baudrate vdi may tfnh PC

Modul UART chi thu du lifiu, sau dd xfl ly rdi dua cac dudng didu khidn nhu tren hinh sang khd'i Step-motor Cdng vific tifi'p theo la vifi't chuong trinh va md phdng cac bd Tx

va Rx Qua trinh xfl ly cdc tin hifiu dieu khidn cdn cd thfim mfit Process trong modul I/O Chflong trinh dugc thuc hifin vdi ngdn ngfl VHDL, sau dd se dugc ghep vdi modul didu khidn motor

Hinh 4 Luu do thuat toan cua bo dem thu TxD

Sau khi chay chuong trinh md phdng ta thu dugc tfn hieu trfin dudng Tx nhu hinh dudi ddy Gia sfl ta nap sd 04 Hex dfi truyfin di, khi dd tren dudng Tx cd dang xung nhu trong bidu dd:

i!jj|jjjj2^^

Hinh 5 Bieu do mo phdng bp dem phat

\ ^ HKiEl = C.BilpntJCI J

Hinh 6 Luu do thuat tuan bu dem thu dfl lieu

Bifiu dd md phdng cua bd dfim thu sau kbi cho dau vao Rx so 06 Hex, chay chuong trinh ModelSim la thu duoc cdc tin hifiu d ddu ra Data[7:0] sd 06 Hex nhu bidu dd dudi day:

Hinh 7 Bie'u do song dau ra ciia bd dem thu du lieu Rx

Sau khi vidt mdt doan Process xfl ly cac Byte nhdn tfl mdy tfnh sang dd dua ra cac dudng difiu khidn nhu hinh 3 Trong file lO.vhd khai bao thfim mdt sd tfn hieu ciia Module Top-Step Sau dd ldng hgp va thuc thi chuong trinh, nfi'u khdng cd ldi thi tifi'n hanh gan chdn trong chuong Irinh Xilinx PACE dung cho Board mach Starter Kit Board Spartan-3 vdi cac chdn dugc gan nhu sau:

E^i^S S«c<1>

r»232_ld

iiZ32_td

P u i h b t n

L e d l

Led

CLK

Output {CS

Output ee

Output R13

Input T13

Input UA

d u l p u l K12

Output ' P 1 4

Output LT2

Input i t s

1 Hi G r o u p l I / O Diiactioni Lew |

- 4 | S e c Output 1

BANKO BAN (CO SANKO BAHK4 BANK3 BANt;3' [BANKS , 1

i / O S M iVtal|Vcco|Driv«Sti.| Tsmmation | Slevj

! ' ^ j 1 Hinh 8 Bo'tri chan board Spartan 3

Sau khi djch chuong trinh se lao ra file I/O.bit, nap chuong trinh vdi tool iMPACT ten file 10.bit vao thie't bi Nhu vdy thuat loan didu khidn ddng co budc da dugc nap vao chip FPGA Spartan3

V KET LUAN

Bai bao gidi thieu cac budc tridn khai flng dung cdng nghfi FPGA cua Xilinx trfin mdi trudng ISE Foundation trong thuc te'

Trong tridn khai flng dung, nhdm tac gia da thuc hifin bai loan difiu khifin ddng co budc tren bo mach Spartan3 Starter Kit va sfl dung md to cd bfldc gdc la 7.5" , dien dp nudi dgng CO la 5V

Kdt qua thu dugc la vific didu khidn ddng co dugc thuc hifin td't Giao difin rd rang, dfi sfl dung Chuong trinh mdm deo, linh boat

Trfin CO sd kfi't qua thu dugc trong bai bao nay, chung ta hoan toan cd thd md rdng cac flng dung dd thuc hifin cac bai loan do ludng, didu khien luong IU trfin co sd sfl dung cdng nghfi FPGA cLia Xilinx

Tdi lieu tham khdo:

[[] Nguyen Tdng Cifdng Phan Qud'c Thdng

Cd'u true vd lap trinh cdc he xd ly dn hieu so Nhd xud't bdn KHKT 2004

[2J Nguyen Tdng Cifdng Phan Qud'c Thdng

Cd'u triu vd lap trinh hg vi dieu khien 8051 Nhd xudt bdn KHKT 2004

[3J Don Davis (Winter 2002), 'Architectural Synthesis: Unleashing die

Powei of FPGA System-Level Design ", )^ellJournal, (Issue 44),

Xilinx, United States of America

[4J Roger Lipsett & Carl Schaefer (1989), VHDL: Hardwaie Description and Design, Kluwer Academic Publishers, United States of America

[5] David Han is (1955) Structural Design With Verilog Harvey Mudd College