on device design for steep slope negative capacitance field effect transistor operating at sub 0 2v supply voltage with ferroelectric hfo2 thin film

In this paper, a practical device design guideline for low voltage operation of steep-slope negative-capacitance field-e ffect-transistors NCFETs operating at sub-0.2V supply voltage is

operating at sub-0.2V supply voltage with ferroelectric HfO2 thin film

Masaharu Kobayashi and Toshiro Hiramoto

Citation: AIP Advances 6, 025113 (2016); doi: 10.1063/1.4942427

View online: http://dx.doi.org/10.1063/1.4942427

View Table of Contents: http://aip.scitation.org/toc/adv/6/2

Published by the American Institute of Physics

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AIP ADVANCES 6, 025113 (2016)

On device design for steep-slope negative-capacitance field-effect-transistor operating at sub-0.2V supply voltage

Masaharu Kobayashiaand Toshiro Hiramoto

Institute of Industrial Science, The University of Tokyo 4-6-1, Komaba, Meguro-ku,

Tokyo, 153-8505, Japan

(Received 6 November 2015; accepted 4 February 2016; published online 16 February 2016)

Internet-of-Things (IoT) technologies require a new energy-efficient transistor which operates at ultralow voltage and ultralow power for sensor node devices employing energy-harvesting techniques as power supply In this paper, a practical device design guideline for low voltage operation of steep-slope negative-capacitance field-e ffect-transistors (NCFETs) operating at sub-0.2V supply voltage is investigated regarding operation speed, material requirement and energy efficiency in the case of ferro-electric HfO2gate insulator, which is the material fully compatible to Complemen-tary Metal-Oxide-Semiconductor (CMOS) process technologies A physics-based numerical simulator was built to design NCFETs with the use of experimental HfO2 material parameters by modeling the ferroelectric gate insulator and FET channel simultaneously The simulator revealed that NCFETs with ferroelectric HfO2 gate insulator enable hysteresis-free operation by setting appropriate operation point with

a few nm thick gate insulator It also revealed that, if the finite response time of spontaneous polarization of the ferroelectric gate insulator is 10-100psec, 1-10MHz operation speed can be achieved with negligible hysteresis Finally, by optimizing material parameters and tuning negative capacitance, 2.5 times higher energy e ffi-ciency can be achieved by NCFET than by conventional MOSFETs Thus, NCFET is expected to be a new CMOS technology platform for ultralow power IoT C2016 Au-thor(s) All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/) [http://dx.doi.org/10.1063/1.4942427]

I INTRODUCTION

Modern mobile computing including wearables and emerging Internet-of-Things (IoT) tech-nologies such as smart sensor network demand extremely low power Large-Scale-Integration (LSI) systems.1Especially if the power is supplied by energy harvesting sources, ultralow power consumption as low as µW or less will be required for a chip to conduct data sensing, data process-ing, and data communication At transistor level, the most effective way to reduce power consump-tion is lowering supply voltage (Vdd) However, if Vddis lowered, drive current of the transistor is also reduced If the drive current is reduced, the circuit delay is increased and off-state leakage current keeps flowing during the period, which is not desirable from the low power perspective For mobile computing and sensor network applications, it is preferable for the device to become active and complete program tasks in the short time period, and then stand by in sleep mode for the rest

of the time Therefore, for the given program tasks, switching energy is an important metric for low power devices In order to achieve energy-efficient switching at given Vdd, Ion/Io ff needs to be as high as possible.2

To increase Ion/Ioff, it is commonly understood that subthreshold slope (SS) needs to be small SS is generally expressed by SS= (∂Ψs/∂Vg)−1

(∂log10I/∂Ψs)−1, where Ψsand Vgare surface

a Address correspondence to: masa-kobayashi@nano.iis.u-tokyo.ac.jp

2158-3226/2016/6(2)/025113/10 6, 025113-1 © Author(s) 2016.

potential and gate voltage, respectively The first term of the right hand side of the equation of

SS represents the electrostatics of a metal-oxide-semiconductor (MOS) capacitor, meaning how

efficiently Vg can bend the silicon band On the other hand, the second term of the right hand side

of the equation of SS represents the conductance, meaning how much current can be driven by the band bending In the conventional MOS Field-Effect-Transistor (FET), ∂Ψs/∂Vg does not exceed one because of the voltage divider between the gate dielectric and silicon channel The second term is ∼2.3kT/q because the transport in subthreshold region is dominated by diffusion transport

of excess minority carriers, of which distribution is described by Boltzmann distribution, at the source side of the MOSFET It is therefore known that SS has the minimum limit of 60mV/dec To overcome the limit of 60mV/dec, there have been extensive researches to enhance the second term

by employing novel steep-slope transistors such as tunneling FET (TFET)3and impact ionization MOSFET (IMOS).4However, TFET and IMOS have their own issues such as low drive current, complicated process flow, and necessity of modifying circuit layout for TFET, and high on-set lateral voltage, reliability issue, and complicated process flow for IMOS

Then negative capacitance FET (NCFET) has been proposed by Salahuddin et al.,5as an alter-native steep slope transistor to overcome the classical limit of 60mV/dec, and has been extensively studied.5 11NCFET has the same structure as MOSFET except that ferroelectric thin film is used

as a gate insulator If ferroelectric material is used as a gate insulator, ∂Ψs/∂Vgcan possibly exceed one because of the nonlinear characteristics of the ferroelectric, so called, negative capacitance Negative capacitance has been, in fact, experimentally observed in ferroelectric thin film,10which paves the new road to the innovative device technology NCFET has the same electron transport mechanism of drift and diffusion as conventional MOSFETs, so that it can drive higher current than tunnel-based FETs thanks to the higher channel charge density brought by amplified Ψsat the same off-current Therefore, NCFET has been attracting more interests because it has possibility

to break the limit of SS=60mV/dec and exceed the drive current of conventional MOSFETs In addition, NCFET is a symmetric device with respect to source and drain upon device operation, which is beneficial in development and production of new device technology Standard pull-up and pull-down CMOS logic circuits as well as pass-gate CMOS circuits which flow current in both directions between source and drain can be built by NCFET It is not necessary to largely modify the logic circuit architecture and IP macro design from the conventional MOSFET

Although NCFET is a promising candidate of a steep slope transistor, there had been obstacles

in process integration If conventional ferroelectric materials such as Lead Zirconate Titanate (PZT) and Barium Titanate (BTO) are used, the thickness of the gate insulator needs to be several hun-dreds of nanometer in order to balance the large polarization charge density and FET channel charge density, which is not compatible to advanced scaled Complementary MOS (CMOS) frond-end technologies Moreover, the heavy metal contamination to the manufacturing line is also concerned Recently, ferroelectricity is discovered in Hafnium Oxide (HfO2) based thin films by controll-ing crystalline phase of the films.11 – 19The ferroelectric HfO2thin film has been already applied to Ferroelectric Random Access Memory (FeRAM) using 28nm CMOS technology.19If the ferroelec-tric HfO2thin film is used for NCFETs as well, the fabrication process will become fully CMOS compatible NCFET can be one of the low-cost solution for IoT power requirement without rely-ing on high-cost advanced CMOS technologies, because NCFET can be fabricated by any CMOS technology from the most advanced technologies to mature manufacturing technologies, just by introducing ferroelectric HfO2gate insulator process In order to promote research and development

of NCFET with ferroelectric HfO2 for IoT application, it needs to be demonstrated that NCFET can be designed at ultralow supply voltage with ferroelectric HfO2as well as with the previously reported ferroelectric material.5 , 6 A practical device design guideline to achieve sufficiently fast operation speed and reliable operation should be provided so that material parameters are appro-priately selected for process development Furthermore, it needs to be quantitatively estimated how much the energy per switching can be lowered by NCFET

In this paper, to target sub-0.2V Vdd operation for ultralow voltage and ultralow power IoT application, we study practical device design for an energy-efficient NCFET with a ferroelectric HfO2gate insulator by tuning its material parameters, based upon physics-based numerical simu-lations, with respect to operation speed, material requirement, and energy efficiency To verify the

025113-3 M Kobayashi and T Hiramoto AIP Advances 6, 025113 (2016)

FIG 1 A schematic of a NCFET with a ferroelectric gate insulator A ferroelectric MOS capacitor is modeled by series connection of ferroelectric and channel capacitance.

device design and its material requirement quantitatively, published ferroelectric HfO2 data are extensively surveyed and referred to as practical parameter range First, the operation principle

of the NCFET is reviewed and its simulation method will be explained Secondly, the simulation results will be shown and discussed with respect to the operation speed, material requirement, and energy efficiency Finally, this work will be summarized

II OPERATION PRINCIPLE OF NCFET AND SIMULATION METHOD

As explained above, the structure of a NCFET is basically the same as a MOSFET, except that the gate insulator is replaced by a ferroelectric material as shown in Fig.1 The basic operation prin-ciple of the NCFET is explained in Refs.5and6 A ferroelectric MOS capacitor can be modeled

by a series connection of a ferroelectric capacitance and a channel capacitance Fig.2(a)shows the ferroelectric polarization (P) - electric field (E) characteristics and channel charge as a function of

Vg In the ferroelectric MOS capacitor, the ferroelectric polarization charge density and the channel charge density should match Therefore, a static operation point of the NCFET is determined by the cross-point of the P-E curve and the channel charge load line The negative capacitance region

is where the slope of the P-E curve is negative If these two curves have a single cross-point in the negative capacitance region, the ferroelectric MOS transistor works as NCFET The operation principle of NCFET can be also qualitatively understood from band diagram of NCFET Fig.2(b-i)

shows the band diagram corresponding to the operation points of (i) in Fig.2(a) As Vg is applied,

a negative oxide field is induced on the gate insulator in the NCFET as opposed to conventional MOSFETs As Vgis increased, the operation point moves to (ii) in Fig.2(a), and the negative oxide field becomes even larger The silicon band bends more than the applied Vg, that is ∆Ψs/∆Vg>1 as

FIG 2 (a) A schematic of a P-E curve and a channel load line as a function of V g A cross point of these two curves is the static operation point of the NCFET The operation points (i), (ii), and (iii) represent low, middle, and high V g , respectively The corresponding band diagrams are drawn in Fig 2(b)

shown in Fig.2(b-ii) This means that the surface potential is effectively amplified against Vg, more channel charges are induced in the channel, and thus higher current is driven in the NCFET than

in conventional MOSFETs As Vg is even further increased, the operation point moves to (iii) in Fig.2(a), and the oxide field flips and the band diagram looks the same as conventional MOSFETs

as shown in Fig.2(b-iii)

Next, the simulation method used in this work is summarized below The ferroelectric MOS capacitor in the NCFET is modeled by series connection of the ferroelectric capacitance and the channel capacitance The modeling and simulation method of ferroelectric MOS capacitor have been established in Refs.5and6 The ferroelectric is described by the Landau-Khalatnikov equa-tion,5 , 6 , 20which is a time-dependent phenomenological equation for ferroelectric materials,

τdP

dt = −dG

where τ is the characteristics response time of the polarization and G is the Landau free energy G is expressed by,

G(P, E) = α

2P

2+ β

4P

4+γ

6P

where α, β, and γ are Landau parameters

In this work, the FET channel is described by the Poisson-Schrödinger equation to calculate electrostatics and quantum mechanical states The simple ballistic transport model21is used for the carrier transport in the NCFET

In the simulation, first, a channel charge density is given Then the Poisson-Schrodinger equa-tion is solved to obtain the depleequa-tion charge density, inversion charge density, subband energies, surface potential and Fermi level Next, the Landau-Khalatnikov equation is solved to obtain the ox-ide field Then Vg is determined by adding the surface potential calculated by Poisson-Schrodinger equation and the voltage across ferroelectric gate insulator calculated by (1) and (2) Then the channel charge density is incremented and the calculation is repeated until the final target of the charge density or Vgis reached The flatband voltage is arbitrarily chosen

In order to constraint ourselves to realistic material parameters for practical device design, the literatures on the recent ferroelectric HfO2thin films were extensively surveyed to refer to Fig.3

summarized the representative material parameters such as remanent polarization (Pr) and coercive field (Ec) The data are distributed among 0<Pr<25µC/cm2and 0<Ec<2MV/cm Pr=9µC/cm2and

Ec=1MV/cm are about median values and chosen as reference material parameters of ferroelectric HfO2

FIG 3 Material parameters of ferroelectric HfO 2 thin films published in the previous literatures.8 14P r =9µC/cm 2 and

E =1MV/cm are chosen as reference parameters.

025113-5 M Kobayashi and T Hiramoto AIP Advances 6, 025113 (2016)

FIG 4 Ψ s -V g characteristics of the ferroelectric MOS capacitor as a function of the ferroelectric thickness V g is swept in both directions, from negative to positive and vice versa 4nm is chosen as a reference parameter.

For the reference material parameters, to find static operation points, the thickness dependence

of Ψs-Vg characteristics of the MOS capacitor of the NCFET with ferroelectric HfO2was studied

as shown in Fig 4 Vg was swept back and forth, from negative voltage to positive voltage and vice versa Ψsis certainly amplified without hysteresis in the thickness range of 3-5nm This is an encouraging result because the thickness of the ferroelectric is just a few nm, which is preferable

to the advanced scaled CMOS process integration Moreover, only 0.2V Vg is needed to amplify

Ψs, which enables low supply voltage operation This result is comparable to previously reported

Ψs-Vg characteristics5 , 6and thus ferroelectric HfO2can be regarded as a candidate for NCFET gate insulator material as well 4nm is chosen as a reference thickness Note that if the thickness is too thick, the static operation point is not properly set and the Ψs-Vgcurve shows hysteresis

III RESULTS AND DISCUSSIONS

First, the operation speed of NCFETs with ferroelectric HfO2is discussed to assess whether NCFET can satisfy speed requirement for microcontroller in IoT device In general, the spon-taneous polarization of a ferroelectric has a finite response time to an external field because it takes time for atoms to move from one site to the other site in the ferroelectric crystalline lattice Therefore, the electronic characteristics of the ferroelectric has time dependence to the applied field Fig.5(a)shows the sweep time dependence of P-E curves of a ferroelectric Metal-Insulator-Metal (MIM) capacitor The P-E curves show larger hysteresis for faster sweep and smaller hysteresis for slower sweep If the sweep time is slow enough, the curve becomes close to the static P-E curve Accordingly, Ψs-Vg curves of a ferroelectric MOS capacitor also show sweep time dependence as shown in Fig.5(b) The Ψs-Vg curves show larger hysteresis for faster sweep and smaller hysteresis for slower sweep If the sweep time is slow enough, the curve becomes close to the static Ψs-Vg

curve Therefore, this dynamic property of the ferroelectric can be another cause of the hysteretic behavior of NCFETs besides inappropriate static operation points, which was discussed in the previous section

Fig.6summarized the hysteresis voltage of the Ψs-Vgcurves with the x-axis of the sweep time normalized by the intrinsic response time of the spontaneous polarization From this figure, if the response time is 10-100psec, the hysteresis voltage becomes less than 1mV and almost negligible Thus the NCFET can operate at 1-10MHz with negligible hysteresis Some literatures reported the response time as fast as 10-100psec.221-10MHz clock speed is sufficiently fast for IoT sensor node device application In order to investigate dynamic operation speed and also to establish precise device modeling, it is suggested to measure and characterize the intrinsic response time of the spontaneous polarization for ferroelectric HfO by experiment

FIG 5 (a) P-E characteristics of the ferroelectric MIM capacitor with di fferent sweep speed of the electric field The electric field is swept in both directions, from negative to positive and vice versa (b) Ψ s -V g characteristics of the ferroelectric MOS capacitor of the NCFET with di fferent sweep speed of V g V g is swept in both directions, from negative to positive and vice versa.

Next, the material requirement for the design of highly energy efficient NCFETs is discussed

Prand Eccan be changed by adjusting Landau parameters in our simulation Fig.7(a-i)shows the P-E curves at fixed Ec and variable Pr, while Fig 7(a-ii)shows the P-E curves at fixed Pr and variable Ec In both cases, the negative capacitance is certainly modulated by Prand Ec Fig 7(b-i)

and7(b-ii) show the Id-Vg characteristics of the NCFET corresponding to Fig.7(a-i) and7(a-ii), respectively In all cases, the current slope of the Id-Vg characteristics in NCFETs is modulated

by changing the negative capacitance Especially, the slope of the Id-Vg characteristics is steeper above threshold rather than subthreshold region In fact, Id-Vg characteristics of Pr=5µC/cm2and

Ec=0.75MV/cm shows the significantly steep slope less than 60mV/dec It also appears that the subthreshold slope extends to the above threshold region

In order to understand the steeper slope above threshold rather than in subthreshold region, Fig.8illustrates the relationship among Ψs, oxide voltage Voxand Vgfor each charge density In the MOS capacitor, Vg-Vf b=Ψs+Voxholds The Ψsis amplified against Vgby accessing to the negative

Vox Note that the charge density should match between the ferroelectric and the channel In the MOS capacitor, the channel charge density is small (<1013cm−2) in subthreshold region and it

FIG 6 Hysteresis voltage of Ψ s versus sweep time of V g normalized by the intrinsic response time of spontaneous polarization.

025113-7 M Kobayashi and T Hiramoto AIP Advances 6, 025113 (2016)

FIG 7 P-E characteristics (a-i) at fixed E c and variable P r and (a-ii) at fixed P r and variable E c (b-i and ii) I d -V g characteristics of NCFETs corresponding to the P-E characteristics in Fig 7(a)

increases by√Ψs, while the channel charge density is high (>1013cm−2) in strong inversion region and it increases by exp(qΨs/2kT) To access the negative Vox, the channel charge density should

be sufficiently high to match ferroelectric polarization in strong inversion region rather than in subthreshold region This is the reason that steeper slope is mainly observed above threshold region Based on this understanding, for low Vdd operation, a qualitative guideline for the choice of material parameters Prand Ec can be described as follows, as well as Landau parameters:6 nega-tive Vo x should be accessed at as low charge density as possible For the fixed channel design, ferroelectric has to have low Prto make the slope of the P-E curve smaller in the negative capac-itance region However, low Pr value means that the channel charge density to be balanced is also small, which results in low saturation drive current In order to keep Pr but make the slope

of the P-E curve in the negative capacitance region as small as possible, one possible way is to increase Ec However, too large Eccauses too large negative Vo x, which, in turn, will not guarantee hysteresis-free operation point Moreover, if Ecis too high when the NCFET accesses to negative

Vo xin P-E curve, a large oxide field (>1MV/cm) is induced on the ferroelectric gate insulator The ferroelectric gate insulator is then highly stressed and has a risk of electric breakdown Therefore, the values of Pr and Ec need to be appropriately optimized for the steep slope operation at low supply voltage without hysteresis

FIG 8 Relationship between Ψ , V , and V at each charge density in the NCFET.

FIG 9 Contour plots of I on /Ioffand I d -V g slope factor at (a) V dd 0.5V, (b) V dd 0.3V, and (c) at V dd 0.2V.

Then the material parameters Prand Ecare quantitatively optimized for high energy efficiency

in NCFET The energy per switching is an important metric for energy efficiency Since the switch-ing energy of a transistor2is proportional to Vdd2(ξ+Io ff/Ion), Ion/Io ff is a simple metric that can be extracted from Id-Vg characteristics Therefore, Ion/Io ff is plotted in Pr-Ec two-dimensional space and contour lines are drawn at different supply voltage to be targeted Fig.9(a)shows the Vdd=0.5V case The contour plot of the minimum slope of the Id-Vg characteristics, which is defined in the same way as subthreshold slope, is also shown in the same graph Note that the right-bottom region does not guarantee hysteresis-free operation as explained in the previous paragraph From Fig.9(a), high Ion/Ioffcan be obtained in the wide area in Pr-Ecspace at Vdd=0.5V The material parameters can be chosen from this wide area for optimization Fig.9(b)shows the Vdd=0.3V case Although the Ion/Ioff contour shifts to low Pr region, high Ion/Ioff can be still obtained in the fairly wide area Fig.9(c)shows the Vdd=0.2V case Now high Ion/Ioffcan be obtained in the limited region in the Pr-Ec space around 0<Pr<5µC/cm2 and 0.5<Ec<1MV/cm In this region, Ec is low enough

to avoid significant electronic breakdown of the ferroelectric gate insulator For energy efficient design, material parameters should be chosen from this region

Material parameters Pr and Ec were chosen from the high Ion/Io ff region in Fig 9(c), and corresponding Id-Vg characteristics were shown in Fig.10 For the design such as Pr=2.5µC/cm2

and Ec=0.6MV/cm, high Ion/Io ffratio is certainly obtained in NCFET compared to the conventional MOSFET at drain-source voltage (Vds) 0.2V The switching energy is calculated with the optimum material parameters as a function of Vdd in Fig.11 The Vdd at the energy minimum moves from 0.2V in the conventional MOSFET down to 0.18V in NCFET The minimum energy is reduced and the energy efficiency is improved by 2.5 times Referring to Fig.3, there are existing material data of the ferroelectric HfO2thin films for the optimum Pr and Ec, and the material will be Si,

FIG 10 I d -V g characteristics of the material parameters chosen from the marked design points in the high I on /I o ff region

in Fig 9(c)

025113-9 M Kobayashi and T Hiramoto AIP Advances 6, 025113 (2016)

FIG 11 Switching energy of NCFET and the conventional MOSFET as a function of V dd

Al or Zr-doped HfO2 Vdd of the state-of-the-art CMOS technology is around 0.8V If the supply voltage is lowered from 0.8V to 0.2V in the conventional MOSFET and then NCFET is used, the total energy efficiency is improved by about 10 times Current commercial sensor node device consumes 10-100µW while energy harvesting technique using environmental energy source such

as thermoelectric, vibration, and environmental radio or 10 year lifetime Li ion battery can supply 1-10µW For given operation task, therefore, 10 times energy efficiency by NCFET should fill the gap between demand power and supply power of IoT device The highly energy-efficient NCFET can contribute to sufficing the power requirement of IoT as a new CMOS platform

IV SUMMARY

A physics-based numerical simulator was built for NCFETs with the use of material param-eters of ferroelectric HfO2 gate insulator The NCFET shows Ψs amplification with 3-5nm-thick ferroelectric HfO2gate insulator at low Vg<0.2V as well as previously reported ferroelectric mate-rials This thin ferroelectric HfO2 enables NCFET to be fully compatible to the current CMOS process technology NCFET can also operate at 1-10MHz with 10-100psec response time of the ferroelectric polarization Negative capacitance was modulated by adjusting Pr and Ec, and then

Id-Vg was modulated by the negative capacitance It was illustrated that steep slope appears above threshold rather than subthreshold region By optimizing material parameters of ferroelectric HfO2

gate insulator within the range of experimental material parameters, high Ion/Io ff was obtained in

the NCFET at Vdd0.2V and the energy efficiency is improved by about 2.5 times compared to the conventional MOSFET

ACKNOWLEDGEMENT

This work is partly supported by New Energy and Industrial Technology Development Organi-zation (NEDO)

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