25 inverter design for 2001 future energy challenge (thiết kế bộ nghịch lưu)

List of figures:Fig1 a Block diagram of the proposed inverter system, b Circuit diagram of the proposed inverter Fig2 Flat-topped pulse current Fig3 a Half-bridge Inverter under resistiv

PROJECT REPORT

INVERTER DESIGN FOR 2001 FUTURE ENERGY

CHALLENGE

College of Engineering and Computer Science

University of Central FloridaOrlando, FL 32816

Tel (407) 823-0185 Fax (407) 823-6334 batarseh@mail.ucf.edu

Student Team Members : Joy Mazumdar Manasi Soundalgekar

Duy Bui Nancy Saldhana Bassem Khoury Steven Pugh

Advisor: Dr Issa Batarseh

15th June, 2001

Signature Page The following students comprised the Future2001 EnergyChallenge team from the University of Central Florida under the guidance of Dr Issa Batarseh.

TABLE OF CONTENTS List of figures

2.10 Component values for 10kW inverter system

A DSP Sampling cycle

B ORCAD schematic for PCB layout

C Pspice schematic circuit for 1.5kW and 10kW inverter system

D Devices and IC datasheets

List of figures:

Fig1 (a) Block diagram of the proposed inverter system, (b) Circuit diagram of the proposed

inverter

Fig2 Flat-topped pulse current

Fig3 (a) Half-bridge Inverter under resistive load, (b) Switching and output voltage waveformFig4 (a) Half-bridge with inductive- resistive load, (b) Equivalent circuit, (c) Steady state

waveforms

Fig5 SPWM and Inverter Output Voltage

Fig6 Single SPWM pair of pulses

Fig7 Inverter control scheme

Fig8 (a)Waveforms for correction of dead time, (b) Inverter leg

Fig9 Input protection circuit

Fig10 RC Snubber Circuit

Fig11 Thermal resistance

Fig12 Power panel schematic

Fig13 Differential Voltage and current waveform under normal resistive load

Fig14 Phase 1 and Phase 2 voltage waveform

Fig15 DC positive and negative bus voltage

Fig16 Maximum voltage stress across switches MOSFET1, MOSFET2, IGBT1, IGBT2, IGBT3

and IGBT4

Fig17 Load current waveform under unbalanced load conditions

Fig18 Output Filter Capacitor voltage waveform under unbalanced load conditions

Fig19 Output Filter Inductor current waveform under unbalanced load conditions

Fig20 Voltage feedback waveform for DSP

Fig 21 Current feedback waveform for DSP

Fig 22 Voltage and current waveforms for 10kW system

1.0 Introduction

In this report, a design for a high power density 10kW inverter circuit is presented for conversion ofenergy from DC fuel cells to AC power to be used mainly for domestic utility applications Theconfiguration is achieved using a high frequency dc-dc push-pull converter at the input side followed by afull-bridge PWM inverter and a low-pass filter at the output side Due to the simplified power stage andthe application of DSP-based sinusoidal pulse width modulation technique, output voltage TotalHarmonic Distortion (THD) is reduced and a relatively smaller overall inverter size is achieved Theproposed practical circuit operates from a 48V DC fuel cell input and outputs a regulated 120V AC, 60Hz

sinusoidal voltage having 3-wire configuration[4] A complete circuit analysis, design and cost evaluation

is presented and supported by PSPICE simulation results As per competition guidelines, a low powerinverter has been redesigned, tested and prototyped, to deliver a 1.5kW load Operating waveforms,printed circuit board layout and measured efficiency of the actual circuit are also presented

2.0 Theory of Design Rationale

This project will explore the possibility of making alternate sources of energy utility interactive by means

of low cost power electronic interface (DC-AC inverter) The constraint towards the above scheme is theinput DC voltage from alternate forms of energy is very rarely stable hence the design of the proposedinterface has to produce an AC output, which is independent of the input fluctuations[3] The PWMinverter will be digitally controlled using a commercial DSP chip for AC voltage and frequencyregulation The implementation of the DSP will have a current controller, voltage controller and a feedforward controller The input voltage from the renewable forms of energy will be 48VDC with fluctuationlimit of 42-72V DC The output voltage will be 110/220VAC @60Hz clean sine wave suitable for homeapplications Since the inverter is for residential use, low cost, high reliability and safety are essentialdesign issues

2.1 Design Specifications for the 1.5kW prototype [1]

InverterStageAC-DC

Low-PassFilter

Total Harmonic Distortion : < 5%

Switching Frequency : 50kHz for push pull and 15kHz for inverter bridgeOperating temperature : 10° C - 40° C

2.2 DC-DC Converter Stage Design [14]

A block and circuit diagram for the proposed inverter implementation is shown in Fig (a) and the circuitschematic is shown in Fig 1(b)

Fig 1(a): Block diagram representation of the proposed inverter system

Fig 1(b): Circuit diagram of the proposed inverter system

Load Load Load 50kHz 50kHz

Iac Vac

Cin

R3

R4

To reduce the size of the system transformer, the first stage will consist of a high frequency push-pull

dc-dc converter The second stage consists of two half-bridge inverters arranged in a full bridgeconfiguration The control technique used in the second stage is sinusoidal PWM The third stagerepresents the low pass filter with passive components, due to the relatively high attenuation of the lowharmonic components for the output voltage waveform The input stage consists of power devices Q1and Q2, transformer T1, inductor L1, L2 and dc bus capacitors C1 and C2 The dc push-pull converterboosts the bus voltage to 240VDC for the inverter to produce 110VAC The output inverter stageconsists of power devices Q3 - Q6, output inductors L3, L4 and capacitors C3 and C4 Using the well-knownsinusoidal PWM technique, this circuit generates a sine wave output voltage

2.2.1 Basic Circuit Operation of DC-DC stage

The push pull converter belongs to the feed-forward converter family With reference to Fig 1(b), when

Q1 switches on and Q2 is off, current flows through the 'upper' half of T1's primary and the magnetic field

in T1 expands The expanding magnetic field in T1 induces a voltage across T1 secondary, the polarity issuch that D2, D4 is forward biased and D1, D3 is reverse biased D2 conducts and charges the outputcapacitor C2 via L2 and D4 conducts and charges the output capacitor C1 via L1 The components L1, L2

and C1, C2 form a LC filter network When Q1 turns off, the magnetic field in T1 collapses, and after aperiod of dead time (dependent on the duty cycle of the PWM drive signal), Q2 conducts, causing thecurrent to flow through the 'lower' half of T1's primary and the magnetic field in T1 expands Now thedirection of the magnetic flux is opposite to that produced when Q1 conducted The expanding magneticfield induces a voltage across T1 secondary, the polarity is such that D1, D3 are forward biased and D2, D4

are reverse biased D1 conducts and charges the output capacitor C1 via L1 and D3 conducts and chargesthe output capacitor C2 via L2 After a period, Q1 conducts and the cycle repeats

There are two important considerations to be made when it comes to the design of the push - pullconverter:

1 Both transistors must not conduct simultaneously, as this would effectively short-circuit thesupply Hence, the conduction time of each transistor must not exceed half of the total period forone complete cycle; otherwise, the conduction will overlap.

2 The transformer magnetic flux must be bi-directional; otherwise the transformer may saturate,and cause destruction of Q1 and Q2 This requires that the individual conduction times of Q1 and

Q2 are exactly equal and the two halves of the center-tapped transformer primary be magneticallyidentical

These design considerations must be handled by the control, drive circuit and the transformer

The average output voltage, Vout, equals the average of the waveform applied to the LC filter:

T = on time period of Q2 Seconds

The control circuit monitors and controls the duty cycle of the drive waveforms to Q1 and Q2 If V in

increases, the control circuit will reduce the duty cycle accordingly, so as to maintain a constant output.Likewise, if the load is reduced and V out rises the control circuit will act in the same way Conversely, a

decrease in V in or increase in load will cause the duty cycle to be increased Following given is the

derivation of all the inverter parameters

Relations between primary current, output power, and input voltage:

Since the maximum average input power Pin is 1.8kW and if we assume the efficiency of the push-pullconverter to be 90%, then the average output power Pout of the DC-DC stage is 1.65kW

where V DCmin is the minimum DC input voltage, 0.5 is the duty cycle and I pft is the flat-topped pulse

current as shown in Fig (2) The flat-topped pulse current is defined as ramp on a step The flat-toppedpulse current appears at the transformer center tap

Fig 2: Flat-topped pulse current

The relationship in Equation (3) is valuable since, it gives the equivalent peak flat-topped primary currentpulse amplitude in terms of what is known at the outset, the minimum DC input voltage and total input oroutput power This value is needed to help us select the MOSFET Finally, for the MOSFET selection themaximum voltage stress that the MOSFET has to handle should be known

Maximum voltage stress of the MOSFETs:

It can be shown that the maximum voltage stress across the MOSFET is given by the following formula,

1 3 2

where V DCmax is the maximum input DC voltage

The maximum stress voltage is 30% above twice the maximum DC input voltage Maximum stresscomes from the so-called leakage inductance spikes, these come about because there is an effective small

t

iTr

Ipft

inductance (leakage inductance) L l in series with each half primary At the instant of turnoff, current in

the MOSFET falls rapidly at rate

E ls = l at the bottomend of the leakage inductance The leakage spike may be as much as 30% more than twice the maximum

V = ( V )= 187 Volts at 50 % duty cycle

MOSFET Conduction losses

The total MOSFET loss consists of switching loss P t ( a c ) and conduction loss P DC and is given by

min max

min )

(

624 0 12

3

DC out s

DC DC

out dc

T V V

P P

P

2.2.2 Design of transformer stage for DC-DC[15]

The push-pull DC-DC converter design is one of the most critical issues in this project The detaileddesign is explained as below based on the following design parameters:

T = C (maximum temperature rise)

Skin depth of the wire is δ in cm

Based on A w calculated above, choose wire size AWG 23, heavy insulation copper wire

Output Power P out of the converter is given by

1446

out

The total apparent power is P app in VA is given by

Based on the value of core geometry, ferrite core from Magnetics Inc, OP 45530-EC is a suitable E core

for the above application The PC bobbin used is PC-B5530-FA

Datasheet of OP 45530-EC Core:

The core geometry of the above core is 2.206504 cm5 AL is defined in mH/1000 For more information

refer to [15]

For the secondary winding, 3 strands of AWG 23 heavy insulation copper wire were chosen.

2.2.3 Output inductor design of DC – DC stage

This inductor is required since the input is a voltage source and the DC capacitors also act as a voltagesource Hence, the inductor acts as a current link between two voltage sources For the purpose of charge

and voltage balancing in the DC capacitors, we require a coupled inductor The inductance value can be

calculated based on the MOSFET switching frequency and duty cycle as given by,

where D = 0.5 , L1=L2=L L1 and L2 are the coupled inductors Vout is the average output voltage, fs is the

switching frequency, ∆Io is the output current ripple (assume to be 10% of output current) Based on 1:5

transformer ratio, i.e output voltage of the push- pull is 240V, and using 750W power rating for each

stage, L = 2 mH The inductor was constructed using a powder iron core (26 material)

Construction of the coupled inductor[15]

The selection of the core was based on the following two main design parameters

• Inductance L required with DC bias = 2mH

The core geometry of the above core is 1.827264 cm5 AL is defined in mH/1000

The required number of turns, N, can be calculated as

where, A L=mH/1000turns and L=inductance in mH

We have chosen N=90 turns for the required inductance

For calculation of the wire size, the bare wire area required @ 450A/cm2, Awb, is obtained from,

Hence AWG 18 heavy insulation copper wire is suitable for the inductor Since the inductor is coupled,the construction requires 2 strands of AWG 18 wire wound 90 times inside a pair of E220-26 core.

2.2.4 Design of DC bus capacitors

It is assumed that all the energy for the inverter is supplied by the DC capacitor bank The ripplefrequency at the DC capacitor will be twice the switching frequency, i.e 100kHz These are bulkcapacitors and the ripple voltage across it is assumed to be 1% of maximum value The value of thecapacitors can be calculated using the following formula,

V =min ripple capacitance voltage

The DC bulk capacitors are chosen to be 560uF/ 500V

2.3 PWM DC-AC Inverter Stage Design[14]

Since the inverter is the most important aspect in this design, a detailed steady state analysis is presentedfor the half bridge inverter topology, which is used in our circuitry The analysis presents the equationsand supporting waveforms

2.3.1 Basic half-bridge inverter circuit resistive load

To illustrate the basic concept of a dc-to-ac inverter circuit we consider a half-bridge voltage-sourceinverter circuit under resistive load as shown in Fig 3 (a) Its switching waveforms for S1, S2 and theresult output voltage are shown in Fig 3 (b)

Fig.3 (a) Half-bridge Inverter under resistive load.(b) Switching and output voltage waveform

The circuit operation is very simple since S1 and S2 are switched on and off alternatively at 50% dutycycle as shown in the switching waveform in Fig 3 (b) This shows that the circuit generates a square acvoltage waveform across the load from a constant dc source The voltages, Vdc and –Vdc are across Rwhen S1 ON while S2 OFF and when S2 is ON while S1 is OFF, respectively One observation to be

made here is that the frequency of the output voltage is equal to f = 1/T and is determined by the switching frequency This is true as long as S1 and S2 are switched complementarily Moreover, the rms

value of the output voltage is simply Vdc Hence, to control the rms value of the output voltage we must

control the rectified Vdc voltage source Another observation is that the load power factor is unity since

we have purely resistive load That is rarely encountered in practical application

-Finally, we should note that in practice the above circuit does not require two equal dc voltage sources asshown in Fig 3 (a) Instead, large splitting capacitors are used to produce two equal dc voltage sources.The two capacitors are equal and very large so that RC is much larger than the half-switching period This

will guarantee that the mid-point, a, between the capacitors has a fixed potential at one-half of the supply

voltage Vdc

2.3.2 Inductive-Resistive load

Figure 4 (a) shows a half-bridge inverter under inductive resistive load with the equivalent circuit and theoutput waveforms shown in Fig 4 (b) and (c), respectively

Fig 4 (a) Half-bridge inverter with inductive resistive load.

(b) Equivalent circuit and (c) Steady state waveforms

D1 Q1

iD1

iD2

(a)

With Q1 and Q2 switched complementary each at 50% duty cycle with switching frequency f , then the

load between terminal a and a ′ is excited by square voltage waveform vin(t ) of amplitudes

=

T t T V

T t V

Multiple Pulse (Uniform) Pulse-Width-Modulation

In the uniform PWM technique, multiple pulses are generated, each one having the same width and aremodulated equally to control the output voltage In order to reduce the harmonic content in the single-pulse inverter, we can apply several pulses within each half cycle of the output voltage The number of

pulses increases when the control period decreases or its frequency, fs, increases K is the number of Tsperiods in one half of the output period, To The frequency of the reference signal sets the frequency ofthe output voltage fo It can be noticed as the magnitude modulation index, M, varies from 0 to 1, thewidth of each pulse varies from 0 to π / k, i.e.

2 1

The ratio between the carrier frequency and the output frequency is known as Frequency Modulation

In SPWM the output voltage signal can be obtained by comparing a control signal, vcont, against a

sinusoidal reference signal, vref , at the desired frequency as shown in Fig 5 At the first half of the output

period, output voltage takes a positive value (+Vdc), whenever the reference signal is greater than the

control signal At the same way, at the second half of the output period, the output voltage takes anegative value (-Vdc) whenever the reference signal is less than the control signal.

The control frequency fcontdetermines the number of pulses per half of cycle for the output voltage

signal Also, the output frequency fo is determined by the reference frequency fref The modulation

index Ma is defined as the ratio between the sinusoidal magnitude and the control signal magnitude

V,

ref p

Calculation of the output voltage as Fourier series expansion

The calculation of the SPWM output voltage is the same as it was done with UPWM output voltage.However, for SPWM the width of each pulse varies according to its position The expression for theoutput voltage is obtained using a Fourier series transformation for vo, given by,

∑∞

=

+ +

=

Κ

2 , 1

) sin cos

( )

(

n

n n

o

Since the inverter output voltage is an odd function, only odd harmonics exist

The calculation the output voltage harmonic components can be done using one single pair of pulses asshown in Fig 6

| ) cos (

) ( ) sin(

) ( ) sin(

) ( ) sin(

) ( ) sin(

1

) ( ) sin(

) (

θ π θ

θ θ π

θ θ

θ θ π θ π

θ θ

θ

θ θ π ϑ π

+ +

=

=

+ + + +

+ + + +

+ + + +

i i

wi i DC

n n

n

V

V

nwt nwt

n

V

V

wt d nwt wt

d nwt

V

V

wt d nwt V

wt d nwt V

V

wt d nwt wt

v

V

wi i i wi

i i

wi i i

wi i

i

wi i i

sin 2 cos

Factoring through, we obtain the harmonic component for a single pair of pulses,

i wi

i wi

Inverter controller scheme is shown in Fig 7 [10]

Figure 7:Inverter control scheme

The inverter modulates a dc bus voltage, Vdc, into a cycle-by-cycle average output voltage The amplitude

of the inverter output voltage is directly proportional to the commanded duty cycle of the inverter and theamplitude of the dc bus voltage Vdc It can range from + Vdc to - Vdc Current mode control is used for thisPWM inverter Current mode control is a two-loop control system that simplifies the design of the outer

PI 1 PI 2

PWM1 PWM2

ADCIN

ADCIN

GATE DRIVE

Voltage and current sense amplifier

+ _

+ _ Iout Vout

TMS320F240EVM

voltage control loop and improves UPS performance in many ways, including better dynamics and a feedforward characteristic that could be used to compensate DC bus ripple and dead-time effect, etc.

2.3.4 The Output Voltage

It can be shown that the average output voltage over TS period is given by,

1 0

t d kV

θ θ θ

ω π

2

2 1

width dc

rms

o

k V

rms

k

m k V

π

The rms of the output voltage is a function of the modulation index m a

2.3.5 Dead Time Compensation[13]

Normally PWM is generated by sampling the required signal at the corners of the sawtooth wave givingsamples s1 and s2 From these samples the desired output voltage should go low at 'a' and high at 'b' Ifthe current is positive the output voltage follows the edges of T1 When the output current is negative theoutput voltage follows the edges of T2 which are adjusted as shown to match the PWM intersectionsagain at 'a' and 'b' To implement the deadtime 'd' when both switches are OFF the additional edges at 'c'and 'e' must be generated One means of implementing a dead-time is to generate a nominal signal Tnfrom which T1 and T2 are formed For this scheme, T1 follows Tn but any turn-on is delayed by 'd' T2follows the inverse of Tn but any turn-on is delayed by 'd'

Fig 8: Waveforms for correction of dead time

The desired Tn for both directions of current is illustrated in the diagram and is generated by

Positive sawtooth edge

compare sawtooth with Vph for i>0 ; compare sawtooth with Vph- for i<0

Negative sawtooth edge

compare sawtooth with Vph+ for i>0 ; compare sawtooth with Vph for i<0

The sawtooth is usually between voltages corresponding to DC bus voltage Vs and for a desired deadtime

'd' the value of the offset is 2d V S

T

ε =

Including this correction to regular sampled PWM will give exact correction to deadtime error providedthe current is continuous For natural sampled PWM, the correction will not be exact but differences will

be less than the difference between natural and regular PWM

2.4 Output LC filter design[11,13]

A proper designing of the LC filter can result in a great reduction of the inverter output harmonics andhence provide very clean power for the load The designing of the LC filter is based on the Inverter outputvoltage and the minimum reactive power of the filter The design procedure involves some assumptions:

• The source DC voltage is ripple free

• All power devices behave ideally

• The load is linear

• Series resistance of the capacitance is negligible

As the exact voltage drop across the filter inductance is difficult to determine, it is assumed negligible.Thus, rms inverter output voltage is equal to the rms load voltage based on this assumption, themodulation index can be calculated as

From the value of the modulation index, the constant K, which has been derived from the Fourier analysis

of the output voltage, can be calculated as given below

2 1 6 5 4

2

1440

4

55

644

1

,

2 2 ,

41

avg or d S

r avg

or d S

f V

E K

= (35)where,

d

E is the input DC voltage to the inverter stage , V o is the output rms voltage , V or,avg is the average

output voltage , fris the fundamental output frequency , f Sis the switching frequency , Lf is the filter

inductance , Cfis the filter capacitance

Using the value of Ed to be 240V and the output RMS voltage to be 120VAC, we find the value of

required L to be 1.7mH and the value of capacitance to be 4.7uF These values give the corner frequency

of the LC filter to be 1.7kHz As far as the corner frequency selection is concerned, since we areregulating the low frequency current and voltage, we need to filter out the high frequency content Giventhat the switching frequency is 15kHz, the corner frequency should be 10-20 times lower than that(~1.5kHz) to be able to extract the fundamental frequency On the other hand, we do not want to attenuatethe fundamental frequency (60Hz) So, we need a need a corner frequency of 10 times higher than that(~600Hz) Given these constraints, the corner frequency should be <1.5Khz and >600Hz Half way inbetween will gives ~1kHz corner frequency This does approximately match with the range of value,which we derived from the theoretical calculations Hence, we choose the filter inductance value to be2mH and the capacitance value to be 17.5uF

2.5 Input Circuits, filtering, fusing and transient protection

Input Filtering

Capacitors C1, C2, C3 and Balun transformer T1 form an input Balun filter [13] A Balun filter is used toattenuate common mode noise generated by the converter and reflected back onto the power bus The Pi(¼) filter, which will suppress differential mode noise The filter components are chosen such that itpresents the highest impedance at the converter switching frequency The inductance value of the Baluntransformer chosen is 8uH This is manufactured by using 10 turns of AWG 18 heavy insulation copperwire wound on E220-26 micrometals iron powder core The value of the capacitors chosen is220uF/100V Practically speaking, this type of filter can reduce noise levels by about 10 to 12 dB

Input Fusing

As a general rule, the input lines to any power converter should be fused The fuse will limit input power

in the event of a catastrophic failure within the converter or the system the converter is supplying power

to The chosen fuse should be a slow-blow type with a current rating approximately 200% of the full loadinput current to the converter (for wide input range converters, 200% of the maximum input current must

be used) Having a slow-blow type will allow the converter short circuit protection circuitry time to react

to transient fault conditions For our application, an 80A fuse semiconductor fuse is chosen for inputprotection

Input Transient Protection

The avalanche Zener D2, clamps the input to a safe level in the event of a power line transient Theenergy contained within the transient is dissipated across the surge suppresser

Fig 9: Input protection circuit and output filter

2.6 Output Overload protection

Although the use of filtering will prevent excessive current at power ON, under normal conditions, thebest way to prevent overload at output is to use a fuse with sufficient tolerance to inrush current, so that itwon't blow at power ON A 15A semiconductor fuse is selected for the output phases

2.7 DSP Control Design[2,5,6,10]

Today’s low-cost, high-performance DSP controllers, such as the Texas Instruments (TI) TMS320F240,provide an improved and cost effective solution for inverter design The F240 has integrated peripheralsspecifically chosen for embedded control applications These include Analog-to-Digital converters (A/D),PWM outputs, timers, protection circuitry, serial communications, and other functions High CPUbandwidth and the integrated power electronic peripherals of these devices make it possible to implement

a complete digital control of inverters Most instructions for the F240, including multiplication andaccumulation (MAC) as one instruction, are single cycle Therefore, multiple control algorithms can be

220nF/100V

C2220nF/100V

+

C3+

220nF/100V 8uH

8uH