Nervous System on a Chip Patent

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US011347998B2

( 12 ) United States Patent

Narcross

( 54 ) NERVOUS SYSTEM ON A CHIP ( 56 ) References Cited

U.S PATENT DOCUMENTS

( 71 ) Applicant : Fredric William Narcross , Chillicothe ,

( 72 ) Inventor : Fredric William Narcross , Chillicothe , 2015/0120629 A1 * 4/2015 Matsuoka

OH ( US )

GOON 3/049 706/44 GO6N 3/063 706/25

GOON 3/04

706/25

GOON 3/049

706/25

2015/0248607 Al * 9/2015 Sarah ( * ) Notice : Subject to any discla er , the term of this 2015/0317557 A1 * 11/2015 Julian

patent is extended or adjusted under 35

U.S.C 154 ( b ) by 1009 days

( 21 ) Appl No : 15 / 905,730

( 22 ) Filed : Feb 26 , 2018

( 65 ) Prior Publication Data

US 2019/0266477 A1 Aug 29 , 2019

a

( 51 ) Int Ci

G06F 30/00 ( 2020.01 )

GO6N 37063 ( 2006.01 )

G06F 8/40 ( 2018.01 )

GO6F 30/323 ( 2020.01 )

G06F 30/34 ( 2020.01 )

( 52 ) U.S Cl

( 2013.01 ) ; G06F 30/323 ( 2020.01 ) ; GO6F

30/34 ( 2020.01 )

( 58 ) Field of Classification Search

See application file for complete search history

* cited by examiner

Primary Examiner — Suchin Parihar ( 74 ) Attorney , Agent , or Firm - Michael D Eisenberg

A method to translate a nervous system model into Hard

ware Description Language ( HDL ) is presented here The

nervous system model is that produced from the Nervous

System Modeling Tool , patent application Ser No 15/660 ,

858 , and the HDL translation downloads into either a Field Programmable Gate Array ( FPGA ) chip or an Application

Specific Integrated Circuit ( ASIC ) architecture The method supports the neurobiological realism of Ser No 15 / 660,858

and adds massive parallelism operating at adjustable micro

chip speeds A neurobiologically realistic nervous system embedded on a microchip achieves the goal of neuromor phic computing and thus embodies a nervous system on a chip The potential applications are extensive and cover the range of robotics , big data analysis , medical diagnostics and

remediation , self - learning systems , and artificially intelli gent applications such as intelligent assistants Intelligent

assistants can be applied to the fields of language and technology exposition , the Internet of Things ( IOT ) and security

8 Claims , 5 Drawing Sheets

1 Nervous System on a Chip

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& Sirnulation

Environment

5 Create Output for

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4 High - level Module HDL

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Runtime

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3 Nervous

System to HDL Translator

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Application

15660858

Constructs

Nervous System

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9 Hardware

Creation

Environment

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Hardware

7 High - level Module HDL

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15660858 Constructs

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2 Patent Application 15660858 Constructs Nervous System

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21 Neurons

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20 System

Builds

Neurons and

Astrocytes

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22 Astrocytes

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U.S Patent May 31 , 2022 9 Sheet 2 of 5 US 11,347,998 B2

3 Nervous System to HOL Translator

3

31 Build for

Simulation

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3

3 4 High - level

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Module HOL

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22 Astrocytes 2200 Astrocytes

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31102 Process

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31103 Process Axon

Inputs and Outputs

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31104 Process Astrocytes

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31105 Instantiate

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U.S Patent May 31 , 2022 Sheet 4 of 5 US 11,347,998 B2

32 Build for Hardware

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Inputs and Outputs

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31105 Instantiate

Astrocytes

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10 Nervous System HDL Runtime Modules

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US 11,347,998 B2

NERVOUS SYSTEM ON A CHIP In still a further variant , the Nervous System to HDL

Translator comprises : filtering neurons and astrocytes data

CROSS - REFERENCES TO RELATED bases for dynamic values ; and passing filtered values into

APPLICATIONS either of a Build for Simulation module or Build for Hard

ware module

In another variant , the Build for Simulation module U.S application Ser No 14 / 821,738 , entitled BRAIN comprises : a Build for Simulation I process ; and a Build for EMULATOR SUPPORT SYSTEM , filed Aug 8 , 2015 and Simulation II process

U.S application Ser No 15 / 660,858 , entitled NERVOUS In a further variant , the Build for Simulation I process

SYSTEM MODELING TOOL , filed Jul 26 , 2017 are each

hereby incorporated herein by reference in their respective 10 comprises : a Create Simulation Header , comprising gener ating a timescale compiler directive to set a clocking fre

comprising reading all filtered Neurons ; processing axon

TECHNICAL FIELD inputs and outputs ; processing astrocytes inputs and outputs ;

and an Instantiate Astrocytes process , comprising construct

The subject technology is in the technical field of mod- 15 ing instantiated astrocyte modules within the Build for

eling nervous systems on microchip computing hardware Simulation module

and encompasses the field of neuromorphic computing In yet another variant , the Build for Simulation II process

comprises : an Instantiate Neurons process , comprising con

BACKGROUND structing instantiated neuron modules within the Build for

20 Simulation module for every neuron ; a Create Simulation

The technology's background stems from earlier work in Begin process ; a Process Simulation PNS II , comprising the fields of nervous system modeling and simulation at the initializing PNS inputs and outputs to a default value ; a

macro and micro levels of biological realism on traditional Process Axons Initialization , comprising initializing layers

computing devices The tool presented here is the culmina of axon inputs per layer ; and a Create Finish process

tion of that research and further research on how to place the 25 In still a further variant , the Build for Hardware module

previous nervous system models directly onto hardware comprises : a Build for Hardware I process ; and a Build for Hardware II process microchip devices or solid state media In another variant , the Build for Hardware I process

comprises : a Create Hardware Header , comprising generat

SUMMARY

ing a timescale compiler directive to set a clocking fre The subject technology begins with the most comprehen quency and timing resolution ; processing Hardware PNS I , comprising reading all filtered Neurons ; processing axon sive , detailed and accurate reproducer of nervous systems inputs and outputs ; processing astrocytes inputs and outputs ; available in the public sector and permits it to operate at and an Instantiate Astrocytes process , comprising construct

microchip speeds It naturally integrates disparate input ing instantiated astrocyte modules within the Build for types and incorporates extensible hardware input and output 35 Hardware module

units It supports inexpensive delivery on reconfigurable In a further variant , the Build for Hardware II process FPGA hardware and has wide applicability into leading edge comprises : an Instantiate Neurons process , comprising con

technologies and artificial intelligence applications structing instantiated neuron modules within the Build for

In a variant , a method for modeling a nervous system on Hardware module for every neuron ; a Create Hardware

a chip , comprises , in a step ( a ) : translating a nervous system 40 Begin process ; a Process Axons Initialization , comprising

model into Hardware Description Language ( HDL ) and in a initializing layers of axon inputs per layer ; and a Create

step ( b ) : translating runtime modules into HDL

In another variant , the method comprises translating neu

In further variant , the method comprises translating astro- 45

In yet another variant , the method comprises translating components , creation and operating environment FIG 2 illustrates further detail of Constructs Nervous neuron runtime modules of step ( b ) into HDL

In still a further variant , the method comprises converting System 2 FIG 3 illustrates further detail of Nervous System to HDL floating - point arithmetic to fixed - point arithmetic Translator 3

In another variant , the method comprises translating FIG 4 illustrates further detail of Build for Simulation 31 astrocyte runtime modules of step ( b ) into HDL FIG 5 illustrates further detail of 311 Build for Simula

In a further variant , the method comprises the converting tion I

floating - point arithmetic to fixed - point arithmetic FIG 6 illustrates further detail of 312 Build for Simula

In yet another variant , a computer implemented method of 55 tion II

simulating a nervous system on a solid state storage medium FIG 7 illustrates further detail of 32 Build for Hardware

and a processor , comprises : a Nervous System to Hardware FIG 8 illustrates further detail of 321 Build for Hardware

Description Language ( HDL ) Translator receiving the input I

from a Constructs Nervous System process The Nervous FIG 9 illustrates further detail of 322 Build for Hardware

System to HDL Translator translates the input into HDL 60 II

code for an instantiated neuron and astrocyte modules ' FIG 10 illustrates further detail of 10 Nervous System

parameters in a High - Level Module HDL The method HDL Runtime Modules

comprises compiling by either a Create Output for Simula

tion process or by a Create Output for Hardware process DETAILED DESCRIPTION OF THE DRAWINGS

Nervous System HDL Runtime Modules are astrocyte and 65

neuron runtime routines and translating them into HDL FIG 1 illustrates Nervous System on a Chip 1 basic

modules components and construction processes First , input is

a

Finish process

50

a

10

25

System to HDL Translator 3 , which translates the input into Parameter Description

HDL code for the instantiated neuron and astrocyte mod- 5 2100151 A Pbdn Number of Synapses

ules ' parameters in either 4 High - Level Module HDL or 7 2100151 A PbdA AMPA value

High - Level Module HDL The difference between these two 2100151 A PbdN NMDA value

high - level HDL modules is that 4 is for when the user wants 2100151 A PbdGA GABA - A value

to simulate the resultant system in software without a 2100151 A PbdGB GABA - B value

2100151 A PbdD

delivery to hardware Whereas , 7 is for delivery to either an 2100151 A PbdS Dopamine value Serotonin value

FIG 3 Next , 10 Nervous System HDL Runtime Modules , 2100151 A Pbdd Dummy - user defined

whose components are detailed in FIG 10 , are the astrocyte

and neuron runtime routines that were translated from the

patent application Ser No 15 / 660,858 JAVA language ver- 15

either compiled by 5 Create Output for Simulation when the 2100 Neurons continued

user chooses to run a simulation as represented by 6 Simu

Hardware when the user chooses to create an FPGA or ASIC 20 210015 Pbd

Basal Dendrites Parameters hardware device as represented by 9 Hardware Creation 2100152 Pbd Basal Dendrites Parameters Layer 2

FIG 2 illustrates detail of the Constructs Nervous System

2 process 2 represents a basic goal of patent application Ser

No 15 / 660,858 to build a database of connected neurons 2100153 Pbd Basal Dendrites Parameters Layer 3

and a database of connected astrocytes FIG 2 consists of 20 2100152A Podp Short - term Synaptic Plasticity

System Builds Neurons and Astrocytes which is a basic

representation of the patent application Ser No 15 / 660,858

processes which create both the 21 Neurons database as well 2100156 Pbd Basal Dendrites Parameters Layer 6

as the 22 Astrocytes database 2100156A Pbdp Short - term Synaptic Plasticity

FIG 3 illustrates detail of 3 Nervous System to HDL

Translator The goal of 3 is first of all to examine both the

21 Neurons and the 22 Astrocytes databases for dynamic 2100156A Pbdd Dummy - user defined

values , as determined by 2100 Neurons and 2200 Astrocytes

respectively , which act as filters and pass those filtered 35

values into either of 31 Build for Simulation or 32 Build for The values from Table 1 , 21001 through 210014 , are

Hardware The filtered values for 2100 are detailed in Tables extracted per neuron from 21 Neurons and applied as HDL

1-3 module instantiation parameters in the high - level module for

either 4 High - Level Module HDL or for 7 High - Level TABLE 1 Module HDL The module instantiation parameters are

constructed by either 31 Build for Simulation or 32 Build for

2100 Neurons

Hardware respectively For each neuron module instantiated

Parameter Description within a high - level module , 4 or 7 , there is only one copy of

21001 Pa Spiking Dynamics these parameters , which basically represent neuron soma

21002 Pb Spiking Dynamics parameters or apical dendrite parameters common to all

21003 PvPeakBD Voltage Peak Basal Dendrite apical dendrites for this neuron On the other hand , Tables 2

21004 PvPeakSoma Voltage Peak Soma

21005 PcBD Conductance Basal Denedrites and 3 represent a collection of 96 permutations of the basal

21006 PcSoma Conductance Soma dendrites that 1 Nervous System on a Chip supports This

21007 Pc Spiking Dynamics 50 includes 6 possible layers of apical dendrites with 16 pos

sible basal dendrites per layer Table 2 lists the entire entries

21009 Pe Spiking Dynamics

210010 Pf Spiking Dynamics for the first layer and first basal dendrite Table 3 lists the

210011 Pg Spiking Dynamics repetitions for the remainder of the 6 layers as well a

shortened form for the 16 basal dendrites The filtered values

210013 Pi Spiking Dynamics

210014 Pj Spiking Dynamics 55 for 2200 are detailed in Table 4

30

40

45

TABLE 4

60

2100 Neurons continued Parameter Description

Parameter Description

210015 Pbd

2100151 Pbd

2100151A Podp

2100151 A Pbdt

Basal Dendrites Parameters

Basal Dendrites Parameters Layer 1 Short - term Synaptic Plasticity

Short - term Synaptic Plasticity Recovery

22001 Nn

22002 Nn

22003 Nn

22004 Nn

22005 An

22006 An

Neuron Neighbor 1 ID Neuron Neighbor 2 ID Neuron Neighbor 3 ID

Neuron Neighbor 4 ID Astrocyte Neighbor 1 ID Astrocyte Neighbor 2 ID

65

2200 Astrocytes

Parameter

22007 An

22008 An

3

US 11,347,998 B2

TABLE 4 - continued each occurrence is assigned a new output port line with a

name given by parameter 11070 1 OutNamel

FIG 4 illustrates detail of 31 Build for Simulation This

Description process creates 4 High - Level Module HDL which is the high

5 level HDL module to generate when the user wants to

Astrocyte Neighbor 3 ID construct a simulation and verify their design prior to

Astrocyte Neighbor 4 ID creating a high - level module for chip construction either in

FPGA or ASIC form 31 begins with 311 Build for Simu

Parameters 2201 Nn through 2204 Nn are the neuron ids of lation I , which is the first half of the processes which create

those neurons surrounded by some particular astrocyte The 10 4.311 is detailed in FIG 5 31 continues with 312 Build for

neurons ' synaptic activity or lack thereof is recognized by Simulation II , which is the second half of the processes the astrocyte , which in turn increases or decreases the which create 4 312 is detailed in FIG 6 Both of 311 and

surrounding capillaries diameter that in turn changes the 312 utilize input from 21 and 22 filtered through 2100 and volume of blood flow through the capillaries The capillaries 2200 respectively and detailed further in FIG 3 The infor blood flow provide a range of resources required for basal 15 mation gathered and filtered is used to create the instantiated modules ' parameters for 4 Also , both 311 and 312 utilize 11

dendrite growth or pruning which places astrocytes in the so as to distinguish which neurons from 21 might be either

position of managing this change by dynamically adjusting

blood flow This is the model of the tripartite synapse also PNS input or PNS output This was also described in the details of FIG 3 As well , 11 is used to invoke 31 rather than

known as the Neural Vascular Unit ( NVU ) Parameters 2205 20 invoking 32 Build for Hardware This was also described in

An through 2208 An are the astrocyte ids of the local FIG 3

astrocytes connected by gap junctions to this particular FIG 5 illustrates detail of 311 Build for Simulation I 311

astrocyte This supports the creation of an astrocyte network , begins with 31101 Create Simulation Header , which creates

which in turn provides for one astrocyte's activity to be the “ ? timescale ” compiler directive to set the clocking communicated to its neighbors and vice versa The thinking 25 frequency and timing resolution This is set to a default of

behind why astrocyte networks are an advantage to nervous 100 ns with a 1 ps resolution 31101 also sets 4's name to a systems is that the communication of neuronal activity or the default of " test_bench ” Next , 311 invokes 31102 Process

lack thereof provides advanced “ knowledge ” of neuronal Simulation PNS I 31102 reads all of the 21 Neurons filtered

activity which can modify capillary resources so as to through 2100 looking for both PNS inputs from 11 param

minimize the lag time of neuronal resource supply and 30 eter 11061 1 InTypel as well as PNS outputs from 11070 1

demand This minimization of lag time to increase capillary OutTypel Matching inputs receive a name of 11 parameter resources or its opposite to minimize the total local blood 11061 1 InNamel followed by an integer which is incre supply when there is no demand are both considered to be mented for each occurrence For example , the first such the result of evolutionary blood flow optimization The brain occurrence would receive a name of in1Name_0 and the

of humans , which account for about 2 % of total body mass 35 second would receive a name of in Name_1 Matching

followed by an integer which is incremented for each

glucose consumption benefits greatly from neurophysiologi

cal optimization of resource consumption by astrocytes occurrence For example , the first such occurrence would receive a name of out1 Name_0 and the second would

Finally , 11 Control Table is a 2 patent application Ser No 40 receive a name of outlName_1 , etc All PNS inputs and

15 / 660,858 JAVA class which must be customized by the outputs are declared as one bit registers : “ reg ” Next , 311

11 contains parameter 1101 SB which controls whether 31 for each neuron contained in 21 , 31103 sets up a maximum

or 32 is invoked Parameter 1102 contains the text name of of 6 apical dendrite inputs each of which accept a maximum

the high - level module’s Start name input port line , which is 45 of 16 axon inputs For example , for neuron id 0 there would

the name of the line that initializes or reinitializes the entire be 6 , 16 bit registers declared as reg [ 15 : 0 ] axon_0_in_1 for

system including all of the instantiated neurons and astro- layer I up to reg [ 15 : 0 ] axon_0_in_6 for layer VI Then cytes Parameter 1103 contains the text name of the high- 31103 sets up a single axon output per neuron id from 21 level module's Clock name input port line , which is the For example , for neuron id 0 the declaration would become name of the line that is passed to all instantiated neuron and 50 " wire axon_0 " The neurons ' axons are all declared with a astrocyte modules to control their clock signal and , in turn , " wire ” designation since they interconnect modules Next ,

the frequency of all module operations Parameter 1104 311 invokes 31104 Process Astrocytes Inputs and Outputs

Neuron Size contains the number of 21 records to inspect First of all , for each astrocyte contained in 22 , 31104 sets up This allows the user to select a subset of neurons generated a wire output with a text name of " astro_out_id ” where id is

by 2 as opposed to the entire collection Parameter 1105 55 replaced by the astrocyte id This output is used to commu

Astrocyte Size contains the number of 22 records to inspect nicate to connected astrocytes Then for each astrocyte This allows the user to select a subset of astrocytes generated contained in 22 , 31104 sets up a wire output with a text name

by 2 as opposed to the entire collection Parameter 11061 1 of “ arteriole_out_id ” where id is replaced by the astrocyte InTypel indicates the neuron type of the peripheral nervous id This output is used to communicate to connected neu system that will be delivered from external sources , i.e from 60 rons Next , 311 invokes 31105 Instantiate Astrocytes , which

sources external to the microchip This value is then constructs the instantiated astrocyte modules within 4 To

searched for within 21 and each occurrence is assigned a accomplish this , 31105 creates a unique module header for

new input port line with a name given by parameter 11061 each astrocyte consisting of the text “ astrocyte ” , which is the

1 InNamel Parameter 11070 1 OutTypel indicates the name of the astrocyte module , followed by the text

neuron type of the peripheral nervous system that will be 65 “ A_ID_id " where “ id ” is the astrocyte id number For

delivered to external sources , i.e to sources external to the example , " A_ID_O ” would be the astrocyte module instan microchip This value is then searched for within 21 and tiation for the astrocyte with id 0 Next , as required by HDL