Advanced Computer Architecture - Lecture 10: Computer hardware design

Advanced Computer Architecture - Lecture 10: Computer hardware design. This lecture will cover the following: pipeline datapath and control design; features of pipelined processor; pipelining lessons; pipelined processor design; pipelined registers included; multiple cycle verses pipeline – pipeline enhances performance;...

CS 704

Advanced Computer Architecture

Lecture 10

Computer Hardware Design

(Pipeline Datapath and Control Design)

Recap: Lecture 9 Single cycle verses multi cycle datapath

Key components of multi cycle data path Design and information flow in multi cycle data path

Multi cycle control unit design

Finite State Machine–based control Unit

Microprogram-based controller

What is pipelining?

Pipelining is a fundamental concept

It utilizes capabilities of the Datapath by

Pipelining is Natural!

Laundry Example!

Four loads: A, B, C, D

Four laundry operations:

Wash, Dry, fold and place into

drawers

Washer takes 30 minutes

Dryer takes 30 minutes

“Folder” takes 30 minutes

“Stasher” takes 30 minutes

to put clothes into drawers

Pipelined Laundry: Start work ASAP

Pipelined laundry takes 3.5 hours for 4

Features of Pipelined Processor

All the functional units operate independently

Multiple tasks operating simultaneously

using different resources

Pipelining doesn’t help latency of single

task, it helps throughput of entire workload

Potential speedup = Number pipe stages

……… Cont’d Next please!

Pipelining Lessons

Pipeline rate limited by:

- Slowest pipeline stage

- Time to “fill” pipeline and time to “drain” it

Five Steps of Datapath

Pipelined Processor Design

Execute/

Address

Memory Rd/Wrt

Write Back (Reg Wrt)

Instruction Fetch

ID/Reg Rd

Exe/Address

Memory Rd/Wrt

Pipelined Registers Included

A B

Execute/

Address Memory Rd/Wrt

Write Back (Reg Wrt)

Five Steps as Stages of Pipeline

.

Load

Multiple Cycle verses Pipeline – Pipeline enhances performance

   5   6   7    8   9    10 Clk

Multiple Cycle Implementation:

Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem

Ifetch

R­type

Reg Exec Mem

Load Ifetch Reg Exec Mem Wr

3 Instructions program reconsidered

Load

Store

R-type (ADD)

The cycle time of a single cycle machine is 45 ns, and of multi cycle and pipelined machines is 10 ns; and average CPI due to instruction mix on multi cycle machine is 4.6.

What is the execution time on each type of machine?

Ans:

Single Cycle Machine

– 45 ns/cycle x 1 CPI x 100 inst = 4500 ns

Multi Cycle Machine

– 10 ns/cycle x 4.6 CPI x 100 inst = 4600 ns

Pipelined machine

– 10 ns/cycle x (1 CPI x 100 inst + 4 cycle drain) = 1040 ns

Another Example

Consider a multicycle, unpiplined processor requires 4 cycles for the ALU and Branch operations and 5 cycles for the memory operation.

Assume the relative frequency of these operations is 40%, 25% and 35% respectively; and the clock cycle is of 1 n sec.

In pipelined implementation, due to clock skew and setup

processor adds 0.2 n sec to the clock

Pipelined Execution Representation

Program Flow

IFetch Dcd Exec Mem WB

Can pipelining get us into trouble? Structural hazards

– Data hazards

– Control hazards

How Stall degrades the performance?

The pipelined CPI with stalls =

Ideal CPI + Stall clock cycles per

instruction

How Stall degrades the performance?

CPI Unpiplined

1 + stall cycles per instruction

multi cycle datapath verses pipeline

datapath

Key components of pipeline data path

Performance enhancement due to pipeline Hazards in pipelined datapath

and ALLAH Hafiz