Advanced Computer Architecture - Lecture 5: Instruction set principles (Cont''d)

Advanced Computer Architecture - Lecture 5: Instruction set principles (Cont''d). This lecture will cover the following: encoding instructions and MIPS Instruction format; instruction set encoding; MIPS instruction set; instruction word types; hybrid length taxonomy;...

CS 704

Advanced Computer Architecture

Lecture 5

Instruction Set Principles

(Encoding instructions and MIPS Instruction format)

Prof Dr M Ashraf Chughtai

Today’s Topics

Recap Lecture 4

Instruction Set Encoding

MIPS Instruction Set

Summary

Recap: Lecture 4

Three pillars of Computer Architecture

Hardware, Software and Instruction Set

Instruction Set

Interface between hardware and software

Taxonomy of Instruction Set:

Stack, Accumulator and General Purpose Register

Types and Size of Operands:

Types: Integer, FP and Character

Size: Half word, word, double word

Classification of operations

Recap … Cont’d

Indirect

Classification of Indirect Addressing

displacement) and memory

Special Addressing Modes

Auto-increment, auto-decrement and scaled Control Instruction Addressing modes

Instruction set Encoding

Essential elements of computer instructions

code”, or the op-code , field of the machine language instruction

Possible locations are: CPU registers, memory cells, I/O locations, part of the instruction itself

Computer Instructions Encoding

3 Place to store the results

Possible locations are:

CPU registers, memory cells and I/O locations

4 Place to find the next instruction from

(this is the default case)

location

Instruction Word Types

Variable Length

- Operation is specified in one field, Op-code

- Can support any number of operands

- Each address specifier determines the addressing

mode and length of the specifier for the operand

- Generally, it generates the smallest code

representation as unused fields need not be included

Typical Examples: VAX, Intel 80x86

Operation and

number of

operands

Address Specifier # 1

Address Specifier #n

Address Field # n Address

field # 1

Variable length Encoding Cont’d

- The decision regarding the length depends upon the

range of addressing modes and degree of

independence between op-code and mode

- For example: immediate addressing requires one or

two address field whereas indexed addressing requires

3 or 4 fields

- The length of Intel 80x86 varies between 1 byte and 17

byte and is generally smaller than RICS architecture

Operation and

number of

operands

Address Specifier # 1

Address Specifier #n

Address Field # n Address

field # 1

Fixed Length Format

in Op-code

necessary Typical Examples: Alpha, MIPS, PowerPC, SPARC

Operation code

Address field # 1

Address field # 3 Address

field # 2

Third Alternative: Hybrid Length

- Multiple formats are specified by the op-code

- One or two fields are added to specify addressing

mode

- Similarly, one or two fields specify operand address

- It generally generates the optimum code size

Typical Examples: IBM 360/370, MIPS16, TI-TMS320c54x

Operation

code

Address specifier

Address field

Operation

code

Address Specifier # 1

Address field

Address Specifier # 2

Operation

code

Address specifier

Address field # 2 Address

field # 1

Hybrid Length Taxonomy

Based on number of Address Fields

4-address instructions

Specifies the two source operands, the destination operand and the address of the next instruction

3-address instructions

Specifies addresses for both operands as well as the result

op code destination source 1 source 2 next address

op code destination source 1 source 2

Hybrid Length Taxonomy Cont’d

2-address instructions

- Overwrites one operand with the result

- One field serves two purposes

Hybrid Length Taxonomy Cont’d

0-address instructions

the result

value on the top of the stack (TOS) and the second value on the stack (SOS) and the result is stored on the TOS

op code

Example

using 0- address through 3-address format

0-Address 1-Address 2-Address 3-Address

PUSH B LDA B LOAD F, B ADD F, B, C PUSH C ADD C ADD F, C MUL F, F, D ADD MUL D MUL F, D SUB F, F, E PUSH D SUB E SUB F, E

MUL STA F PUSH E

SUB POP F

Number of

Instructions: 8 5 4 3

Using different instruction formats, write pseudo­code to evaluate the following  expression:  Z = 4(A+B) – 16(C+58) : Your code should not change the source operands

3­Address 2­Address 1­Address 0­Address

ADDA 58 MULA 16

ADDA B MULA 4 SUBA s

PUSH C PUSH 58 ADD

PUSH 16 MUL

PUSH A PUSH B ADD

PUSH 4 MUL

SUB

Comparison of instruction formats

Assume that

A single byte is used for the op code

The size of the memory address space is 16 Mbytes

A single addressable memory unit is a byte

Size of operands is 24 bits

Data bus size is 8 bits

Use the following two parameters and compare the five instruction formats (O-4 address) mentioned

earlier

- Code size: Its effect on the storage requirements

- Number of memory accesses: It’s effect on execution time

4-address instruction

Code size = 1+3+3+3+3 = 13 bytes

# of bytes accessed from memory

13 bytes for instruction fetch +

6 bytes for source operand fetch +

3 bytes for storing destination operand

Total = 22 bytes

op code destination source 1 source 2 next address

1 byte 3 bytes 3 bytes 3 bytes 3 bytes

3-address instruction

Code size = 1+3+3+3 = 10 bytes

# of bytes accessed from memory

10 bytes for instruction fetch +

6 bytes for source operand fetch +

3 bytes for storing destination operand

1 byte 3 bytes 3 bytes 3 bytes

op code destination source 1 source 2

2-address instruction

Code size = 1+3+3 = 7 bytes

# of bytes accessed from memory

7 bytes for instruction fetch +

6 bytes for source operand fetch +

3 bytes for storing destination operand Total = 16 bytes

1-address instruction

Code size = 1+3= 4 bytes

# of bytes accessed from memory

4 bytes for instruction fetch +

3 bytes for source operand fetch +

0 bytes for storing destination operand

1 byte 3 bytes

op code source 2

0-address instruction

Code size = 1 bytes

# of bytes accessed from memory

1 bytes for instruction fetch +

6 bytes for source operand fetch +

3 bytes for storing destination operand

Total = 10 bytes

1 byte

op code

RISC and MIPS ISA

RISC and MIPS is a fixed length, 64-bit

LOAD/STORE Architecture

Contains 32 GPR each of 32-bit

Supports:

12-16 bits

RISC and MIPS ISA …Cont’d

Supports … cont’d

Instructions:

register-register move

call/return Designed for pipelining efficiency

MIPS Instruction Word format

Recap: MIPS types and size of operands

MIPS Instruction Word Format

11

Sht

Op-code = 000000

Rs and Rt : source operand registers

Rd : Result carrying register

Sht: Number of bit-shift –(left/right)

Func: ALU function to encode the data path operation

Example Encoding MIPS64

R-Type Arithmetic / Logical Instructions

Arithmetic Instructions

DADD R1, R2, R3 Add word (signed) Reg[R1]<-Reg[ R2]+Reg[R3] DADDU R1, R2, R3 Add unsigned Reg[R1]<-Reg[ R2]+Reg[R3]

11

30

MIPS Instruction Word Format

Op

31 26 25 21 20 16 15 0

Rs Rt immediate

Register-Immediate (I- Type)

Rt is the destination field for immediate data instructions

Rt  Rs op immediate; all immediate

Same format is used for Load/Store instructions

Rt  Mem [ immediate + [Rs]]; Load

Mem [ immediate + [Rs]] Rt; Store

MIPS Operations

Immediate Arithmetic / Logical Instructions

Load/Store Instructions

MIPS Instruction Word Format

Op

31 26 25 21 20 16 15 0

Rs Rt immediate

Branch /Jump Register

Conditional Branch Instructions:

(i) used after the compare or test BEQZ:

Rs is the register and Rt is unused;

(ii) Condition with the Branch; BNE

Rs and Rt are compared iii) Jump Register; Jump and Link Register

MIPS Operations

Branch/Jump Register

BEQZ R4, name Branch equal zero If Reg[R4]=0 then PC <- name

BNE R4, R3, name Branch not equal zero If Reg[R4]!=Reg[R3] then PC <- name

MIPS Instruction Word Format

Jump and Link (Procedure Call) place the return

address; the address of the next instruction in R31 used for Return from procedure

MIPS Operations

Jump/Call

J name Jump PC36 63 <- name

J/JAL

31 26 25 21 20 16 15 0

Instruction encoding

- Essential elements of computer instructions:

type of operands, places of source and destinations and place of next instruction

- Instruction word length

Variable, fixed length and hybrid

- Hybrid length taxonomy

4, 3, 2, 1 and 0 address format

- Comparison of hybrid instruction word format

Minimum number of memory bytes are required

in case of 1 address (accumulator) format and maximum for 4-address format

MIPS Instruction word format

- RISC and MIPS is a fixed length, 64-bit LOAD/STORE Architecture

- It supports: Size of Operand

Character (8-bit) Half word (16-bit) Single precision FP or Word (32-bit) Double precision FP or double word (64-bit)

- Instruction word formats

R-type, I-type and J-type

Allah Hafiz

and Asalm-u-Alacum