Microsoft powerpoint set 3 single stage amplifiers

Microsoft PowerPoint Set 3 Single Stage Amplifiers ppt V O T U A N M I N H Faculty of Electronics and Telecommunication Engineering University of Science and Technology The University of Danang Design of Analog Integrated Circuit  Giới thiệu Thiết kế vi mạch Đặc tính của MOSFET  Mạch khuếch đại đơn  Mạch khuếch đại vi sai  Mạch gương dòng  Bộ chuyển đổi tương tựsố  Vòng khóa pha Chủ đề DN, 2020 V T M 2 1 General Considerations 2 Common Source Amplifiers 3 Common Drain (Source Follower).

V O T U A N M I N H

Faculty of Electronics and Telecommunication Engineering University of Science and Technology - The University of Danang

Design of Analog Integrated Circuit

 Giới thiệu Thiết kế vi mạch & Đặc tính của MOSFET

 Mạch khuếch đại đơn

 Amplifiers are essential building blocks of both analog and digital systems.

 Amplifiers are needed for variety of reasons including:

 To amplify a weak analog signal for further processing

 To reduce the effects of noise of the next stage

 To provide a proper logical levels (in digital circuits)

 Amplifiers also play a crucial role in feedback systems

 We first look at the low-frequency performance of amplifiers

Therefore, all capacitors in the small-signal model are ignored!

Why Amplifiers?

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 Ideally, we would like that the output of an amplifier be a linear function of the input, i.e., the input times a constant gain:

Analog Design Trade-offs

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 In common-source amplifiers, the input is (somehow!) connected

to G and the output is (somehow!) taken from D

Common Source (CS) Basics

 We can divide CS amplifiers into two groups:

 Without source degeneration (no

body effect for the main transistor)

 With source degeneration (with

body effect for the main transistor)

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 Different types of loads can be used in an amplifier

 The region of operation of M1 depends on its size and the values

of Vin and RD

 We are interested in the small-signal gain and the headroom

(which determines the maximum voltage swing)

 We will calculate the gain using two different methods

 Large-signal analysis

 Small-signal model

Resistive Load

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 For M1, VGS = Vin, VDS = Vout

 If Vin < VTH, M1 is off and Vout = VDD = VDS

 If Vin becomes slightly larger than VTH, M1 turns on and goes into

saturation, because of VDS = Vout > VGS – VTH

 M1 converts an input voltage change DVin to a drain current

change g m DVin, and hence an output voltage change DVout = −gm

RDDVin

Resistive Load - Large-Signal Analysis

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 As Vin > Vin1, VDS decreases and M1 goes into triode region.

𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝑅𝐷𝜇𝑛𝐶𝑜𝑥 𝑊

𝐿 𝑉𝑖𝑛 − 𝑉𝑇𝐻 𝑉𝑜𝑢𝑡 −

𝑉𝑜𝑢𝑡22

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 The value of Vin that makes M1 switch its region of operation

 Assuming that the transistor is in saturation region and channel length modulation is ignored

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 Sketch ID and g m of M1 as a function of Vin.

 g m depends on Vin so if Vin changes by a large amount then the small-signal approximation will not be valid anymore

 In order to have a linear amplifier, the gain should not depend on

parameters like g m since this parameter depends on the input

 Increasing W / L leads to greater device capacitances

 Increasing V RD limits the voltage swing

 Decreasing ID leads to a greater time constant at the output

node since RD is increased

 Trade-offs between gain, bandwidth, and voltage swings, in

particular, with lower supply voltages

Resistive Load

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 Channel length modulation becomes more significant as RD

 If RD ≈ ∞ (current source as load) => A v ≈ -g m r O: intrinsic gain

 Today’s short-channel CMOS technology, gm r O is between roughly

5 and 10 => 1/g << r

Resistive Load – Channel Length Modulation

S

D G

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 Assuming that M1 in the figure below is biased in saturation,

calculate the small-signal voltage gain of the circuit

Example

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 Suppose the common-source stage of the figure below is to

provide an output swing from 1 V to 2.5 V Assume that V TH0 = 0.7

V, W / L = 50 / 0.5, RD = 2 kW and λ = 0

 Calculate the input voltages that yield Vout = 1 V and 2.5 V.

 Calculate ID and g m of M1 for both cases

 How much does the small-signal gain, g m RD, vary as the output goes from 1 V to 2.5 V? (Variation of small-signal gain can be

viewed as nonlinearity.)

Example

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 Often, it is difficult to fabricate resistors with tightly controlled

values or reasonable sizes on chip => replace RD with MOSFET

Body Effect R x (λ≠0) R x (λ=0)

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D G

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 This is a CS configuration with M2 being the load.

 Body effect of M2 needs to be considered

 Replacing R D in the Resistive load CS by R x

= − 𝑊/𝐿 1

𝑊/𝐿 2

1 1+𝜂2

NMOS Diode-Connected Load

R x

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 If the variation of 𝜂 with Vout is neglected, A v is independent of the

bias currents and voltages (so long as M1 stays in saturation) => the input-output characteristic is relatively linear

 A v is a weak function (square root) of the transistor sizes =>

change the dimensions by a considerable amount so as to

increase the gain

 The voltage swing is constrained by both the required overdrive voltages and the threshold voltage of the diode-connected

 Consider the circuit shown in the figure below In some cases, we

are interested in the impedance seen looking into the source, R X

Determine R X if λ = 0.

Example

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 This is a CS configuration with M2 being the load without body

 Find the gain of the following circuit if M1 is biased in saturation region

and I s = 0.75I1 Assume λ = 0.

- For fixed transistor sizes, using the current source increases A v by 2

- For fixed overdrive voltages, using the current source increases A v by 4

- For a given gain, using the current source allows us to make the size or the

overdrive voltage of the diode-connected load 4 times smaller => increases the

Diode-Connected Load - Example

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 Assuming a constant L, plot the intrinsic gain of a saturated

device versus the gate-source voltage if (a) the drain current is

constant, (b) W is constant.

 Assuming a constant L, plot the intrinsic gain of a saturated

device versus W/L if (a) the gate-source voltage is constant, (b)

the drain current is constant

Example

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 Using current-source as load to increase the load

impedance without dropping a large DC voltage

𝐿 ∙

𝑊𝐿

= 𝐿

2

𝑊

=> Increase L and W keeping the aspect ratio constant (so r O

increases while I D remains constant) However, this approach

increases the capacitance of the output node

 DC voltage of V out is not well-defined

Current-Source Load

Constant

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 Compare the maximum output voltage swings of CS stages with resistive and current-source loads.

Current-Source Load - Example

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 Lemma: In linear systems, the voltage gain is equal to −𝐺𝑚𝑅𝑜𝑢𝑡where 𝐺𝑚 = 𝜕𝐼𝑜𝑢𝑡/𝜕𝑉𝑖𝑛.

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 For large values of V in

 I D / V in of the input device becomes more linear

D G

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 Assuming λ = γ = 0, calculate the small-signal gain of the

circuit shown in the figure below (a).

 Calculate the voltage gain of the circuit shown in the

figure below Assume that I0 is ideal.

Example

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 CS amplifiers needs a large-impedance load to achieve high

voltage gain If the load is low-impedance, a buffer is used

 Source-Follower (SF) amplifiers can be used as buffers

 Ideal Buffer: R in = ∞, R out = 0, A v = 1

Why Buffers?

Z L

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 Examine the Source follower amplifier with two different loads:

1. As V in increases, g m increases and

the gain becomes: 𝐴𝑣 = 𝑔𝑚

𝑔𝑚+𝑔𝑚𝑏 = 1

1+𝜂

2. As V out increases, η decreases, the

maximum gain increases

3. Even if R S = ∞, A v is less than 1

4. A depends heavily on the DC level of V (nonlinear amplifier)

Resistive Load – Small-Signal Analysis

S

D G

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2 2∅𝐹 + 𝑉𝑆𝐵

 To avoid the problem of

nonlinear voltage gain, we

can use a current-source as

 Source followers have typically moderate output impedance,

large input impedance However, avoid using because:

 Source followers are nonlinear because of body effect

 Variable bias current which can be resolved if we use a

current-source to bias the SF => Dependence of r O on V DS in submicron devices

 Body effect can be resolved for PMOS devices, because each

PMOS transistor can have a separate n-well However,

because of low mobility, PMOS devices have higher output

impedance (In more advanced technologies, NMOS in a

separate p-well can be implemented)

Advantages and Disadvantages

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 SFs have voltage headroom limitations

due to level shift Consider the circuit that

a CS is followed by a SF

 If there is only the CS stage

𝑉𝑋 > 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1

 With the SF stage, 𝑉𝑋 > 𝑉𝐺𝑆3 − 𝑉𝑇𝐻3 + 𝑉𝐺𝑆2

 Therefore, adding the SF will reduce the allowable voltage

swing at node X

Advantages and Disadvantages

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