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A Wideband High Efficiency Ka-Band MMIC Power Amplifier for 5G Wireless Communications Duy P.. 2SISLAB, VNU University of Engineering and Technology, Hanoi, Vietnam Abstract — A compact

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A Wideband High Efficiency Ka-Band MMIC Power Amplifier for 5G

Wireless Communications

Duy P Nguyen1, Xuan-Tu Tran2, Nguyen L K Nguyen1, Phat T Nguyen1, and Anh-Vu Pham1

1Department of Electrical and Computer Engineering, University of California, Davis, CA, USA

2SISLAB, VNU University of Engineering and Technology, Hanoi, Vietnam

Abstract — A compact wideband Ka-band monolithic

microwave/ millimeter-wave integrated circuit (MMIC)

power amplifier (PA) is demonstrated using a 0.15-µm

pseudomorphic high electron mobility transistor (pHEMT)

Gallium Arsenide (GaAs) process The proposed harmonic

load-pull and radial stub matching technique have been

employed to achieve wideband and high-efficiency

performance The fabricated PA exhibits a measured output

power of 24 dBm, gain of 20 dB and 35% power added

efficiency (PAE) The PA has a wideband performance in

which the power maintains higher than 23 dBm, and the PAE

is higher than 30% over a wide frequency range from 25 to

34 GHz

Index Terms — Gallium Arsenide, Ka-band, MMIC, Power

Amplifier, Radial stub, Wideband

I INTRODUCTION The demand for mobile data has seen tremendous growth

in recent years which makes the sub-3 GHz spectrum

become increasingly crowded The current mobile network

is reaching the limits in bandwidth and speed, requiring the

next generation of wireless communications to deploy a

millimeter-wave spectrum which has wider bandwidth and

higher data rate [1], [2] Examples of these capabilities

include very high achievable data rates, low latency,

ultra-high reliability, and the possibility to handle extreme device

densities Among millimeter-wave frequency spectrums,

Ka-band (28 GHz) is a major contender for 5G applications

However, the low efficiency of Ka-band power amplifiers

(PAs) imposes a major thermal issue in the base station

where hundreds of PAs are used in a small area [3], [4] To

alleviate the issue, it requires high-efficient amplifiers with

very compact size [5], [6]

Millimeter-wave PAs have been the focus of research for

the emerging 5G wireless communications in recent years

Medium-power MMIC Ka-band amplifiers have been

reported using different technologies including Gallium

Arsenide (GaAs) [5], [7]-[10], Gallium Nitride (GaN) [11],

and complementary metal–oxide–semiconductor (CMOS)

[12]-[14] However, low power added efficiency (PAE) and

(a) (b)

(c) (d) Fig 1 Load-pull contours for a 8 x 75 μm pHEMT device at 28 GHz: (a) Power contours, (b) PAE contours of fundamental impedance, (c) PAE contours of 2 nd harmonic impedance, and (d) PAE contours of 3 rd harmonic impedance

large chip size are still posing a challenge in those designs

In addition, narrow bandwidth makes the amplifiers less attractive to the 5G network applications

This paper reports a wideband, compact and high efficiency Ka-band PA using a 0.15-µm GaAs pseudomorphic high electron mobility transistor (pHEMT) process A two-stage class AB amplifier employs a proposed radial stub matching technique to achieve wideband, high-efficiency performance The fabricated PA demonstrates a measured output power of 24 dBm with an associated peak PAE of 35%, and gain of 20 dB Higher than 23 dBm output power and 30% PAE is observed over the very wide bandwidth from 25 to 34 GHz

II RADIAL STUB FOR WIDEBAND MATCHING AND

HARMONIC TERMINATION

To achieve the target output power at Ka-band, an 8 ×

75 µm device is chosen for the output stage Harmonic

978-1-7281-0397-6/19/$31.00 ©2019 IEEE

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Fig 2 Proposed radial stub versus conventional open stub

load-pull simulation of the device under a drain bias voltage

of 6 V and dc current of 60 mA is performed to find the

optimum impedances for highest output power and highest

PAE Fig 1(a) and (b) show the power and PAE contours

at the fundamental frequency 28 GHz A maximum output

power of 24.5 dBm and 34% maximum PAE can be

achieved at the impedance around Zopt = 8.5 + j10 (Ω) To

further enhance the PAE, optimum impedances at the 2nd

harmonic and 3rd harmonic frequencies can be found from

the harmonic load-pull According to Fig 1(c) and (d), by

terminating the 2nd harmonic close to open circuit, the PAE

can reach a maximum value of 40% and is increased

another 2% by terminating the 3rd harmonic at its optimum

value In this process, at Ka-band frequencies, the 3rd

harmonic termination only contributes very little to the

efficiency enhancement [15] Therefore, to reduce the size

and losses of the matching network, only the 2nd harmonic

termination will be considered in the proposed design

The design of a class-F and class-J amplifiers to achieve

high PAE by terminating the 2nd and 3rd harmonic

impedances has been well presented in [16]-[18] However,

the output matching networks of the class-F and class-J

amplifiers requires several matching sections, thus are quite

bulky and lossy In our design, we propose to use microstrip

radial stubs in the matching network The high-quality

factor of the radial stubs can significantly reduce the

insertion loss and size of the matching network, as well as

satisfy the harmonic load conditions Fig 2 presents the

proposed radial stub and conventional open stub Both of

which has the same equivalent capacitance value at the

center frequency of 28 GHz The use of the radial stub can

reduce the length by 53%, making the matching network

more compact and lower loss

Fig 3 compares the simulated return loss and insertion

loss of the two output matching networks using the radial

stub versus conventional open stub The proposed radial

stub matching significantly improves the bandwidth and

has much lower loss In other words, the reactance of the

radial stub varies much less than that of the conventional

open stub Moreover, the radial stub has three independent

Fig 3 Return loss S11 and insertion loss S21 of the radial stub matching and conventional open stub matching

Fig 4 Fundamental impedance and 2 nd harmonic impedance of the radial stub and conventional open stub matching networks

parameters that can be optimized separately: radius (R o),

width (W), and angle (θ) [19] Therefore, the 2nd harmonic impedance can be easily tuned to achieve the optimum load-pull value that gives the highest PAE Fig 4 illustrates the fundamental and 2nd harmonic matching of the two output matching networks (radial stub versus open stub) Both matching networks provide good 50 Ω match at fundamental frequencies However, the radial stub provides the 2nd harmonic impedance close to the optimum value found in Fig 1(c), resulting in higher PAE

III POWER AMPLIFIER DESIGN The proposed power amplifier has two amplifying stages and is fully matched to 50 Ω system at input and output The schematic of the PA is showed in Fig 5 The MMIC

PA employs a 1:2 gate periphery drive ratios to provide sufficient power margins between stages while preserving high gain and efficiency The peripheries of the pHEMTs are 300 µm (4×75 µm) and 600 µm (8×75 µm) for the driver stage (Q1) and the output stage (Q2), respectively Both

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Fig 5 Circuit schematic of the Ka-band power amplifier

stages are biased in deep class AB in which the bias voltage

of the power stage Q2 is Vd2 = 6 V; I d2 = 60 mA and that of

the driver stage Q1 is Vd1 = 6 V and I d1 = 32 mA

The matching networks consist of radial stubs,

transmission lines, and metal-insulator-metal (MIM)

capacitors The proposed radial stubs are used in the both

the output and inter-stage matching networks to help

enhance the bandwidth, PAE, and reduce the chip size

Another benefit from using radial stubs is that we can avoid

the discontinuity from a large tee junction The inter-stage

matching employs a dual symmetrical radial stub, a dual

shunt stub, and two series transmission lines Compared to

the conventional matching topology, dual stubs provide

totally symmetrical design and enhances performance at

high frequencies In addition, it also allows balanced

biasing in which the dc current can be provided from either

side of the chip or both sides concurrently This additional

feature improves the PA reliability, especially at the drain

bias where high current is needed The input matching

employs a series MIM capacitor and two shunt stubs to

achieve a compact size

The design layout and full electromagnetic (EM)

simulation were carefully handled to ensure a balanced and

symmetrical design Bias pads were placed symmetrically

to allow current supplied from both sides This technique

guarantees current and heat are distributed equally, which

improves reliability All matching networks are designed to

guarantee unconditional stability from dc to 80 GHz

IV EXPERIMENTAL RESULTS

The process selected for our Ka-band PA is a 0.15-µm

GaAs pHEMT transistor This process has an f max of

185 GHz and f t of 90 GHz which make it attractive to

Ka-band applications The process is designed to operate with

a peak drain voltage of up to 6 V and provide relatively

high-power density The 0.15-µm PHEMT device can

deliver 870 mW/mm at 29 GHz in which I dmax= 620 mA/

mm and the breakdown voltage of V gd is 16.5 V Fig 6

shows a photograph of the fabricated MMIC PA The size

of the chip is 2.1 mm × 1.4 mm × 0.01 mm

Fig 6 Chip photo of the fabricated amplifier (2.1 mm × 1.4 mm)

Fig 7 Measured small signal gain and return loss at V d1 = 6 V;

Id1 = 32 mA; V d2 = 6 V; I d2 = 60 mA.

Fig 8 Measured output power, gain, and PAE at 28.5 GHz

Fig 7 shows the measured versus simulated small signal

performance of the MMIC PA at V d1 = 6 V; I d1 = 32 mA;

Vd2 = 6 V; I d2 = 60 mA The maximum small signal gain is

20 dB and maintains above 17 dB from 27 to 32 GHz The

PA achieves good input and output return loss in the frequency range The measured results are correlated with the simulation Fig 8 presents the output power, gain and efficiency of the PA at 28.5 GHz as a function of the input

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Fig 9 Measured output power and PAE as a function of frequency

power with the bias condition as mentioned above The

input power is swept from -15 dBm to +13 dBm with 1 dB

step The output power at 1dB compression point (OP1dB)

is 21 dBm, and the saturation power is 24 dBm The

maximum PAE 35% is achieved at 23.5 dBm output power

Maximum power and PAE across the frequency range

from 25 to 35 GHz is illustrated in Fig 9 The output power

maintains higher than 23 dBm from 25 to 34 GHz while the

PAE is higher than 30% in that frequency range The PA

exhibits excellent power and PAE flatness over a wide

bandwidth Fig 10 shows the measured output power, gain,

relative third order intermodulation (IM3) and third-order

intercept point OIP3 as a function of input power The

linearity data was obtained by a two-tone measurement

with equal amplitude and 10 MHz tone spacing at

28.5 GHz The amplifier demonstrates good linearity in

which 35 dBm OIP3 is observed in Fig 10 Table I

summarizes the proposed PA performance and compares

with other previously published Ka-band MMIC PAs Our

proposed PA achieves among the highest efficiency over a

wide bandwidth

Fig 10 Two-tone measurement at center frequency 28.5 GHz and

10 MHz tone spacing.

V CONCLUSION

We have demonstrated a wideband, compact MMIC

Ka-band PA The 2.0 × 1.4 mm2 amplifier exhibits a measured gain of 20 dB, output power of 24 dBm and peak PAE of 35% at 28.5 GHz Employing the proposed matching topology, the PA achieves a very wide band performance in which measured output power and PAE are flat from 25 to 34 GHz In addition, good linearity and compact chip size are observed, which makes the PA more attractive to the 5G millimeter-wave wideband wireless communication systems

REFERENCES

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[2] A Pham and M Darwish, "High efficiency power

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Global Symposium on Millimeter-Waves, 2017, pp 83-84

TABLE I

COMPARISON TO OTHER PUBLISHED MILLIMETER-WAVE POWER AMPLIFIERS Reference Frequency

(GHz)

Power (dBm)

Gain (dB)

Supply voltage (V)

PAE (%)

Die size (mm 2 )

Number of stages

Technology [7] 29 - 31.8 26.3 14 4.5 35 3.57 Doherty 0.15-um GaAs

[12] 34 19.9 13.8 2.4 25.8 0.365 Dual-mode 65-nm CMOS

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