Tài liệu CDMA truy cập và chuyển mạch P7 ppt

The proposedsystem design and procedures can achieve both access and synchronization in ageostationary satellite orthogonal CDMA for fixed service communications.As we described in Chapte

to a propagation distance of 460 meters), and the cell radious is 230 meters Thesynchronization subsystem to meet the above requirement may then be simple Onthe other hand, a wideband orthogonal CDMA requires a substantial effort in acquiringand maintainingsynchronization, especially in a mobile environment The abovereferenced systems, however, assume that a synchronization subsystem is in placewithout presentingone In this chapter we present such a synchronization subsystem.This work was originally presented in references [4] and [5], and is a new approachfor providingsynchronization in an uplink orthogonal CDMA system The proposedsystem design and procedures can achieve both access and synchronization in ageostationary satellite orthogonal CDMA for fixed service communications.

As we described in Chapter 3, the multibeam satellite common interface providessignaling control and user traffic channels within each satellite beam The controlchannels are used for the acquisition of the user traffic channel The downlink control

Copyright © 2001 John Wiley & Sons Ltd ISBNs: 0-471-49184-5 (Hardback); 0-470-84169-9 (Electronic)

164 CDMA: ACCESS AND SWITCHINGchannels are, the Pilot, the Sync and the Paging broadcast channels, and are identified

by PN and orthogonal codes In the uplink there is an asynchronous access channelwhich has an assigned beam PN-code The access channel operation is based on aSpread-Spectrum Random Access (SSRA) protocol described in the next section Thetraffic channels are defined by the user orthogonal code and the beam orthogonaland/or PN codes

The basic steps of the network synchronization are the initial acquisition of thesatellite downlink control channels, the access channel code acquisition, the system-wide synchronization of all traffic channels and the process of retainingand trackingthe network sync once synchronization has achieved Since uplink transmissions areasynchronous, the main part of this process is the synchronization of all uplink trafficchannels This is required in order to align all uplink orthogonal codes to a referencetime upon arrival at the satellite despreaders, and thus provide orthogonality betweenthe traffic channels This alignment, however, may not be ideal, but it is required thatthe time offset of each signal from the reference time does not exceed 10% of the chiplength The factors which prohibit perfect synchronization include the long satellitepropagation delay, the propagation delay variation due to satellite slow drift motion,

as well as channel conditions such as rain fade, etc The synchronization system alsohas to consider that the complexity of the on-board signal processing is limited by theavailable mass and power of the satellite

The proposed synchronization system, although it is designed and evaluated for thisparticular application, may also be adapted and used in other applications (terrestrial

or satellite) which have orthogonal CDMA for uplink access Limited user mobiltymay also be allowed, dependingon the CDMA spreadingrate and the properties ofthe codes used A particular set of quasi-orthogonal codes may be less sensitive toallignment jitter For example, preferentially phased Gold codes may allow timingjitter of up to 50% of the chip length; see Chapter 2

The system evaluation is focused on the performance of the access channel codeacquisition and the performance of the trackingcontrol loop The access channel carriescontrol messages from the end user to the satellite, while at the same time providesthe timingdelay (PN phase offset) of the user code for the purpose of synchronizingthe uplink orthogonal codes of the traffic channel The proposed code acquistion is aserial/parallel scheme adjusted to meet the packet delay requirements Related work onthe subject is found in references [6] and [7] The analysis of the trackingloop examinesthe loop stability and its steady state error Other work related to the trackingcontrolcan be found in references [8] and [9] The proposed feedback tracking-control loop,however, is quite different, since its trackingpart resides in the satellite receiver whilethe control part resides in the user’s transmitter Thus, the trackingloop model alsoincludes the satellite propagation delay

This chapter is organized as follows The synchronization procedures and the systemdesign are presented in the next section In Section 7.3 we provide the access channelperformance evaluation, and in Section 7.4 the performance TrackingContol Loop.7.2 System Description

The system architecture of the satellite switched CDMA system is illustrated inFigure 7.1 In describing the synchronization procedures of the system, we first identify

ACRU: Access Channel Receiver Unit

ACTU: Access Channel Transmitter Unit

CCU: Call Control Unit

CDS: Code Division Switch

CU: Control Unit

SBTU: Satellite Broadcast Transmitter Unit S&PRU: SYNC & Paging Receiver Unit SU: Subscriber Unit

TCRU: Traffic Channel Receiver Unit TCTU: Traffic Channel Transmitter Unit

SU

SATELLITE

PILOT CHANNEL SYNC CHANNEL

PA GING CHANNEL

TRAFFIC CHANNEL TRAFFIC

CHANNEL

ACCESS CHANNEL

CU A R U

S B T U ACTU

Figure 7.1 System architecture

the PN and orthogonal codes of each channel that we use in the process Thesecodes include the PN code gp(t), definingthe downlink pilot signal which has arate of Rc and is transmitted continuously in the frequency band of the downlinkcontrol channels, (gp(t) is transmitted with given phase offset ∆i correspondingtosatellite beam i) The uplink access channel in beam i is identified by the PNcode ai(t), which has a chip rate of Rc and operates in an assig ned frequencyband Traffic channels are defined by the user orthogonal codes Wk (k = 1, 2, ),the beam PN-codes gi(t) (i = 1, 2, ) and the beam orthogonal codes Wi (i =

1, 2, 3, 4) The traffic channel spreadingoperation shown in Figure 3.12 of Chapter

3 The beam codes Wi have a chip rate of Rc(Rc = 4Rc1) Beam PN-code gi anduser orthogonal code Wk have a rate of Rc1 All uplink traffic channel codes arerequired to arrive synchronously at the satellite despreaders in order to maintain theorthogonality amongusers within the beam, as well as amongbeams That is, thestarting time of all orthogonal codes should be aligned upon arriving at the satellitedespreader

166 CDMA: ACCESS AND SWITCHING

Array of Parallel ACDCs

Channel

-parallel Data Receivers

1 2 BBF

Figure 7.2 A The ACRU B An array of ACDC in parallel

will receive the orthogonal code Wi of the Paging channel (in the downlink)and the PN code ai of the correspondingAccess channel (in the uplink) The

SU then acquires and monitors the Paging channel

2 Access Channel Acquisition: the SU will then make an access attempt in theAccess channel The first message transmitted by the SUki(SU k in beam i)and received successfully at the Access Channel Receiver Unit (ACRU) will

be used to establish the time delay (phase offset) ∆τki from the referencearrival time (τo), i.e ∆τki= τki−τo This message may arrive at the satellitedespreader at any possible phase offset of the sequence ai(t) An array of Kparallel Access Channel Detection Circuits (ACDC) is then used to coverall phase offsets of the code ai (as described in Section 7.3) in order toacquire and despread the code ∆τki may provide a resolution of Tc (onechip length), Tc/2, Tc/4 (Tc/' is called the Chip-Cell, ' = 1, 2 or 4); that is,

∆τki = xkiTc/4 The value of ∆τki will then be sent back to the SU via aPaging channel

3 Traffic Channel Acquisition: the SU will use the value of ∆τki to establishcoarse synchronization to the satellite Reference Arrival Time This is done

by advancingor delayingx chip cells the startingpoint of the code from its

original position at the successful message transmission Then, the SU alignseach orthogonal and PN code of the uplink traffic channel to the code aiandbegins transmission (The traffic channel orthogonal and PN codes Wk, Wi,

gi in the uplink, and W, Wj, gj in the downlink, are supplied to the SU bythe on-board control unit.)

4 Fine Sync Control: after the SU begins transmitting on the traffic channel, afeedback trackingloop will provide fine alignment of the uplink codes with thereference arrival time at the satellite despreaders This feedback loop extendsbetween the satellite to the SU, and is described in detail in Section 7.2.2.Its transient and steady state response is derived analytically in Section 7.4

5 Sync Retention Control: after a steady state has been reached, another Synccontrol circuit will be used to retain the fine Sync attained in the previousstep This circuit consists of the downlink (traffic channel) trackingcircuitand uplink SYNC control described in Section 7.2.2

∆T c 1/2

1

1 γ

2 γ

∑

i1γ

Σ

( · )2i1γ

Σ

Figure 7.3 A The Access Channel Detection Circuit (ACDC), B Double dwell

decision logic

168 CDMA: ACCESS AND SWITCHING

DESPREADING AND TESTING (EARLY)

DESPREADING AND TESTING (LATE)

D E M O D

WkiE giE WiE

WkiL giL WiL

+ -

Z∆

SU SYNC CONTROL (TCTU)

ON BOARD SYNC TRACKING (TCRC)

Z

-Z+

CODE GENERATORS CLK

MOD SPREADERS

CODE GENERATORS

Figure 7.4 The tracking and SYNC feedback control loop

7.2.2 System Design

In step 1 of the above procedure, the synchronization requirements to the Sync andPaging Receiver Unit (S&PRU) are provided by the Pilot PN code, which is acquiredusinga serial search acquisition circuit (in the S&PRU) (The Pilot PN-code is acommon cover (beam) code for all other downlink control channels which are definedwith known orthogonal codes.) In step 2 of the procedure, the access channel providescoarse synchronization for the orthogonal uplink traffic channel This is an additionalfunction of the access channel which comes at no extra cost Its main function is toprovide access for call set-up signaling messages The access channel operates as anasynchronous random access channel Its transmissions obey the Spread SpectrumRandom Access (SSRA) protocol Accordingto SSRA, there is one PN code ai(t) forall users in beam i Each user may begin transmitting a message at any time instant(unslotted channel) Each message consists of a preamble (containing no data) andthe message information data field The transmitted preamble signal will arrive at thereceiver at any phase offset of the PN-code Signals arriving at the receiver more thanone chip apart will be distinguished and received Messages that have (uncorrected)errors due to interference or noise will be retransmitted randomly after the time outinterval, while messages that are successfully received will be acknowledged TheAccess Channel Receiver Unit (ACRU), shown in Figure 7.2-A, consists of a non-

coherent detector, an array of parallel Access Channel Detection Circuits (ACDC) and

a pool of parallel data decoders The array of parallel ACDCs, shown in Figure

7.2-B, provides a combination of parallel with serial acquisition circuits Each ACDC,shown in Figure 7.3-A, searches for synchronization of the message by correlatingover a window of w chips duringthe message preamble The serial search methodutilizes a typical double dwell algorithm, shown in Figure 7.3-B Given L chips, thelength of PN code ai, and K as the number of ACDCs, the window size will then

be w = L/K (1 ≤ w ≤ L) For example, if L = 1204 chips and K = 16, then

w = 64 chips The correlation process takes place duringthe message preamble Theactual number of parallel ACDCs K is determined by the required length of thepreamble interval In the serial search (double dwell) method, the length of the dwelltime γ1 and γ2, as well as the thresholds (Θ1 and Θ2), are determined so that therequirements for the false alarm and detection probabilities are met Also, the accesschannel is assumed to operate at low traffic load in order to offer a high probability ofsuccessful message transmission with the first attempt (see the performance analysis

in Section 7.3)

The proposed mechanism for fine sync trackingcontrol, used in step 4, is shown inFigure 7.4 It consists of the on-board SYNC-Tracking circuit, the downlink feedbackpath, the SU SYNC control circuit and uplink traffic channel timingjitter control Theon-board trackingconsists of an Early-Late gate that provides the timingjitter Z∆.The timingjitter value Z∆ will be inserted in a message and sent to the Call ControlUnit (CCU) in the SU via the paging channel The SU SYNC control circuit will thentake Z∆ as input to make the timingadjustment on the uplink traffic channel TheEarly or Late despreadingcircuits may rely on the highest chip rate beam code Wi, i.e

Wi(t± ∆Tc) (the other codes gi and Wk have a chip length of Tc2= 4Tc) Hence, thedesign of the proposed tracking loop differs from the typical design, since the timingadjustment takes place at the transmitter (SU), not the receiver This is nessassary inorder to align the transmitted orthogonal code to the reference time (at the satellite)

at which all other transmissions have been aligned with This tracking loop, however,introduces delays both in the feedback (downlink) as well as in the forward (uplink)path This delay is equal to the satellite round trip propagation delay, which is about

250 ms The delay also varies slowly because the satellite has a drift motion of about2.5 meters/sec The performance evaluation of this trackingloop have been provided

in Section 7.4

The last step of the process is required in order to maintain the fine synchronizationachieved in the previous step without makinguse of the the on-board sync trackingcircuit The on-board trackingcircuit will become available (after a steady state isreached) for reuse in another call, and thus reduce the on-board hardware The syncretention control circuitry consists of the downlink traffic channel trackingcircuit andthe SYNC control circuit, shown in Figures 7.5 and 7.6 As shown in Figure 7.6, thefeedback signal Z∆of the trackingcircuit of the downlink traffic channel will also feedthe input of the SU Sync control circuit Hence, any change in the satellite propagationdelay with respect to the established timing, by ∆τp (resultingfrom satellite driftmotion) will be indicated at the downlink traffic channel trackingcircuit The ∆τptimingjitter will then be used (by the SU Sync control circuit) to compensate forthe uplink transmission by advancingor delayingby ∆τp usingthe SYNC controlcircuit

170 CDMA: ACCESS AND SWITCHING

ACTU: Access Channel Transmitter Unit

S&PRU: SYNC and Paging Receiver Unit

TCRU: Traffic Channel Receiver Unit

TCTU: Traffic Channel Transmitter Unit

CCU: Call Control Unit

S&PRU ACTU

TCTU TCRU

CCU

Code Generators

SYNC Control Circuit

Access Channel (Uplink) Paging Channel (Downlink)

Traffic Channel (Downlink) Traffic Channel (Uplink)

Tracking Circuit

W ki , g i , W i W kj , g j , W j

Code Generators

Figure 7.5 The SU tracking and SYNC control circuits

7.3 Access Channel Performance

Consideringthe longround trip satellite propagation delay, the main performancerequirement of the access channel is to provide a high probability of success withthe first transmission attempt The probability of a successful message transmissiondepends (a) on the probability of PN code acquisition duringthe message preamble,(b) on the probability of message collision, and (c) on the probability of no bit errors

in the message after channel decoding (called the retention probability)

(a) The performance analysis presented in Section 7.3.1 determines the designparameters for a serial/parallel aquisition circuit which maximizes the probability ofsuccessfully acquiring(Pacq) within the preamble interval These parameters determinethe minimum preamble interval and the optimum window size ω for a given code length

of L chips and known interference noise conditions The probability Pacq, called theaquisition confidence, is g iven by

Pacq = P r[Tacq ≤ Th] =

 Th0

fTacq(τ )dτ = FTacq(Th)

where Tacqis the aquisition time for the window size of ω chips and This the minimumallowed length of the message preamble which satisfies the aquisition confidence Theprobability distribution fTacq or the cumulative distribution FTacq functions of theacquisition time have been derived in Section 7.3.1

CODE GENERATORS

Loop Filter VCO

DESPREADING AND TESTING (LATE)

D E M O D

+

-The Tracking Circuit of the Downlink Traffic Channel

Z ∆ (WkE , giE , WiE )

(WkL , giL , WiL )

MOD

CODE GENERATORS

Figure 7.6 The SYNC retention tracking control circuit

(b) Collision of two or more packets will occur if they are overlappingand havethe same PN code phase offset when they arrive at the despreader This is based

on the assumption that the channel is unslotted (continuous time) and a single PNcode has been used for all users in the channel Also, we assume that all packetsarrive at the despreader with approximately equal power The probability that ipackets collide given that ko packets are overlappingat any time instant is givenby

Pcoll(i|ko) =



koi

(1/L)i(1− 1/L)ko−i f or 2≤ i ≤ kowhere 1/L is the probability that i packets have exactly the same phaseoffset of the PN code The number of all possible phase offsets is assumed

to be L, equal to the length of the code (in terms of the number ofchips) (If the phase offset is less than a chip we assume that collision takesplace.)

The probabilty that ko packets overlap is given by

P (ko) =(2tpG)

ko

k ! e

−2t p G

172 CDMA: ACCESS AND SWITCHING

Figure 7.7 The cumulative distribution function of the acquisition time

In the above expression, tp is the packet length and G is the total offered trafficload which includes both the newly arrived and retransmitted packets (two or morepackets will overlap if they arrive in the interval 2tp)

The probability of collision will then be

Pcoll=

ko≥2

ko

i=2

Pcoll(i|ko)P (ko)

(c) The probability of packet retention, Pret, is the probability of havingno errors

in the packet’s information field after FEC That is, if the packet length is n bits, then

Pret= (1− Pe)n, where Pe is the bit error probability

The probability of successful packet transmission is then given by

Psucc= Pacq(1− Pcoll)Pret

In the above equation, however, we have assumed that there is always a receiveravailable to decode the data in the packet If there are ' parallel data receivers available(as shown in Figure 7.2-B), then the probability of not finding an available one is

Pun(') =

ko≥P (ko), where P (ko) is the probability of having kopackets overlapping

at the reception at a given load G (given above) Then, Psucc = Psucc[1− Pun(')].7.3.1 Packet Acquisition Performance Analysis

The PN code aquisition is based on the serial/parallel model shown in Figures 7.2and 7.3 The PN sequence of length L is divided into K subsequences of ω chips

each There are K double dwell serial search circuits operatingin parallel over each ofthese subsequences or windows The PN phase offset of each arrived packet in a givenwindow will be detected by the correspondingparallel searchingcircuit In general,the acquisition performance can be improved if the outputs of these parallel circuitsare processed jointly, therefore the performance of any of the circuits assumingthatthey work independently can serve as an upper bound.

In order to determine the false alarm and detection probabilities, we first assumethat each chip is further divided into l cells duringthe search This will give a finalpull-in uncertainty of Tc

2l for the code tracking For each searching window, a total of

ν = lω cells will be tested, amongwhich ν− 2l can lead to false alarms The falsealarm probabilities for noncoherent reception under unfaded AWGN channels can bewritten as (see [10])

Ec(j)

where Ec(j) is the energy per chip for user j and Ka is the number of simultaneouspacket receptions; mψis an interference constant dependingon the chip waveform Forthe 2l cells within one chip of the correct timing, we need to determine the detectionprobabilities The worst case corresponds to samplingtimes that differ from the correct(peak) time by

τj=j− (l +1

2)

l Tc, j = 1, 2, , 2lFor each of these samplingtimes, the detection probabilities are given by

PD1jPD2jzγ1 +γ2

j −1

i=1[(1− PD1i)zγ1]

HM(z) = z2lγ1

2l(1− PD1j) +

2l

PD1j(1− PD2j)zγ1 +γ 2

j −1[(1− PD1i)zγ1]