THIET KE CƠ BẢN
(phân 1)
BỘ so sánh 4 bit
Bộ giải mã BCD sang LED 7 đoạn ALU
Trang 2Bo so sanh 4 bit
A
—— B_` Al:iB —>
Trang 3LIBRARY leece ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY compare IS
| AegB, AgtB, AltB : OUT STD_LOGIC ); R(3 DOWNTO 0) ;
END compare ;
;
ARCHITECTURE Behavior OF compare IS
BEGIN
AeqB <=’1’ WHEN A = B ELSE ’0’ ;
AgtB <='1' WHEN A > B ELSE'0';
AltB <=’1’ WHEN A < B ELSE ’0’
3
Figure 6.34 = VHDL code for a four-bit comparator.
Trang 4Bộ giải mã BCD-LED 7 đoạn
—> BCD
LEDS
BCD
“0000”
“0001”
”0010”
“0011”
"0100"
“0101”
”0I107
"OLLI"
71000”
7I0UI”
LEDS
abcdef g
°1111110”
”01 10000”
”IIOTII0I7
“H[IIOOI” 0110011”
“1011011”
710111117
711100007 TỊITTEII”
“H10011”
Trang 5LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY seg7 IS
PORT (bcd : IN STD LOOGIC VECTOR(3 DOWNTO 0)
leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ; END seg7 ;
ARCHITECTURE Behavior OF seg7 IS
BEGIN
PROCESS (bed )
BEGIN
WHEN “0000” => leds <=”1111110";
WHEN OTHERS => leds <— ” - + END CASE;
END PROCESS ;
END Behavior ;
Trang 6ALU
cin
sel Operation Function Unit
0000 y<=a Transfer a
0001 y <= atl Increment a
0010 y <=a-l Decrement a
0011 y<-b Transfer b Arithmetic
0100 y <= b+l Increment b
0101 y <=b-1 Decrement b
0110 y <=atb Add a and b
0111 y <= atb+cin Add a and b with carry
1000 y<= NOT a Complement a
1001 y <=NOTb Complement b
1010 | y<=aANDb AND
1011 y <=aORb OR Logic
1100 | y<=aNANDb NAND
1101 y <=aNORDb NOR
1110 | y<=aXORD XOR
1111 | y<=a XNOR b XNOR
Trang 7a (7:0)
b (7:0)
y (7:0)
Arithmetic Unit
cin
sel (3:0)
Trang 8LIBRARY ieee;
USE leee.std logic 1164.all;
USE ieee.std logic unsigned.all;
ENTITY ALU IS
PORT (a, b: IN STD LOGIC VECTOR (7 DOWNTO 0);
sel: IN STD LOGIC VECTOR (3 DOWNTO 0);
cin: IN STD LOGIC;
y: OUT STD LOGIC VECTOR (7 DOWNTO 0)); END ALU;
Trang 912
13 ARCHITECTURE dataflow OF ALU IS
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BEGIN
- Arithmetic unit: -
arith <= a WHEN "000",
at+l WHEN "001",
a-1l WHEN "010",
b WHEN "011",
b+1 WHEN "100",
a†+b+cin WHEN OTHERS;
- Logic unit: -
AND b WHEN "010",
NAND b WHEN "100", NOR b WHEN "101", XOR b WHEN "110", NOT (a XOR b) WHEN OTHERS;
WITH sel(3) SELECT
logic WHEN OTHERS;
END dataflow;
Trang 10Bài tập: bộ shifter
Figure 6.56 — A shiRer circuit.
Trang 11LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shifter IS
PORT ( w :IÑ_ STDLOGIC VECTOR(3 DOWNTO 0) :
Shift :IN STD LOOIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;
K : OUT STD_LOGIC );
END shifter ;
ARCHITECTURE Behavior OF shifter IS
BEGIN
PROCESS (Shift, w)
BEGIN
IF Shift = ’17 THEN
y(3) <= "0" ;
y(2 DOWNTO 0) <= w(3 DOWNTO 1) ;
k<= w(0) ’
ELSE
ENDIF:
END PROCESS ;
END Behavior ;
Figure 6.59 = Structural VHDL code that specifies the shifter circuit in
Figure 6.56.