Tài liệu Useful Modeling Techniques part 2 pptx

... //Example 2 module top; bus_master b1(); //instantiate module unconditionally 'ifdef ADD_B2 bus_master b2(); //b2 is instantiated conditionally if text macro //ADD_B2 is defined ... specify that the particular portion of the code be compiled only if a certain flag is set. This is called conditional compilation. A designer might also want to execute certain parts of the Veri...

Ngày tải lên: 21/01/2014, 17:20

... stdout desc2 = handle2 | handle1; //desc2 = 32& apos;h0000_0006 $fdisplay(desc2, "Display 2& quot;);//write to files file1.out & file2.out desc3 = handle3 ; //desc3 = 32& apos;h0000_0008 ... 32& apos;h0000_00 02 (bit 1 set) handle2 = $fopen("file2.out"); //handle2 = 32& apos;h0000_0004 (bit 2 set) handle3 = $fopen("file3.out"); //handle3 = 32& ap...

Ngày tải lên: 26/01/2014, 14:20

... delay2 = 5, delay3 = 6 bus_master #(9, 4) b2(); //b2: delay1 = 9, delay2 = 4, delay3 = 7(default) //Parameter value assignment by name bus_master #(.delay2(4), delay3(7)) b3(); //b2: delay2 ... w1 //Parameter value assignment by name hello_world #(.id_num (2) ) w2; //pass value 2 to id_num parameter //for module w2 endmodule If multiple parameters are defined in the module, ....

Ngày tải lên: 21/01/2014, 17:20

... c1, c2; // Instantiate logic gate primitives xor (s1, a, b); and (c1, a, b); xor #(d_sum) (sum, s1, c_in); //delay on output sum is d_sum and (c2, s1, c_in); or #(d_cout) (c_out, c2, ... methods discussed in the book: Instance Delay Values fa0 fa1 d_sum=1, d_cout=1 d_sum =2, d_cout =2 fa2 fa3 d_sum=3, d_cout=3 d_sum=4, d_cout=4 a. Build the fulladd4 module with defparam...

Ngày tải lên: 26/01/2014, 14:20

Ngày tải lên: 13/12/2013, 20:15

... Example 4 -2 . Example 4 -2 List of Ports module fulladd4(sum, c_out, a, b, c_in); //Module with a list of ports module Top; // No list of ports, top-level module in simulation 4 .2. 2 Port Declaration ... environment as long as the interface is not modified. Ports are also referred to as terminals. 4 .2. 1 List of Ports A module definition contains an optional list of ports. If the...

Ngày tải lên: 15/12/2013, 03:15

... reset is asserted from 0 to 20 and from 20 0 to 22 0. initial begin reset = 1'b1; #15 reset = 1'b0; #180 reset = 1'b1; #10 reset = 1'b0; #20 $finish; //terminate the ... T_FF tff2(q [2] ,q[1], reset); T_FF tff3(q[3],q [2] , reset); endmodule In the above module, four instances of the module T_FF (T-flipflop) are used. Therefore, we must now define (Ex...

Ngày tải lên: 24/12/2013, 11:17

... Methylcellulose 27 .5–31.5 1.64–1. 92 — — — Hydroxypropyl methylcellulose 28 .0–30.0 1.67–1.81 7.0– 12. 0 0.15–0 .25 0 .22 –0 .25 Hydroxypropyl cellulose — — ≤ 80.5 — ≤ 4.6 Page 12 percentage of hydroxypropoxyl ... compression. 2. 3 .2 Acrylic polymers These comprise a group of synthetic polymers with diverse functionalities. Table 2. 2 Compendial designations of HPMC typess in t...

Ngày tải lên: 24/12/2013, 18:15

... most common example of level-sensitive UDPs. A simple latch with clear is shown in Figure 12- 3 . Figure 12- 3. Level-Sensitive Latch with clear In the level-sensitive latch shown above, if the ... described as a UDP as shown in Example 12- 7 . Note that the dash "-" symbol is used to denote no change in the state of the latch. Example 12- 7 Verilog Description of Level-Sens...

Ngày tải lên: 26/01/2014, 14:20